Commit 3b0c8d40 authored by Lennert Buytenhek's avatar Lennert Buytenhek

ARM: plat-orion: irq_data conversion.

Signed-off-by: default avatarLennert Buytenhek <buytenh@secretlab.ca>
Acked-by: default avatarNicolas Pitre <nico@fluxnic.net>
parent e9191028
...@@ -232,20 +232,19 @@ EXPORT_SYMBOL(orion_gpio_set_blink); ...@@ -232,20 +232,19 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
* polarity LEVEL mask * polarity LEVEL mask
* *
****************************************************************************/ ****************************************************************************/
static void gpio_irq_ack(struct irq_data *d)
static void gpio_irq_ack(u32 irq)
{ {
int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
int pin = irq_to_gpio(irq); int pin = irq_to_gpio(d->irq);
writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin)); writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
} }
} }
static void gpio_irq_mask(u32 irq) static void gpio_irq_mask(struct irq_data *d)
{ {
int pin = irq_to_gpio(irq); int pin = irq_to_gpio(d->irq);
int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
u32 u = readl(reg); u32 u = readl(reg);
...@@ -253,10 +252,10 @@ static void gpio_irq_mask(u32 irq) ...@@ -253,10 +252,10 @@ static void gpio_irq_mask(u32 irq)
writel(u, reg); writel(u, reg);
} }
static void gpio_irq_unmask(u32 irq) static void gpio_irq_unmask(struct irq_data *d)
{ {
int pin = irq_to_gpio(irq); int pin = irq_to_gpio(d->irq);
int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
u32 u = readl(reg); u32 u = readl(reg);
...@@ -264,20 +263,20 @@ static void gpio_irq_unmask(u32 irq) ...@@ -264,20 +263,20 @@ static void gpio_irq_unmask(u32 irq)
writel(u, reg); writel(u, reg);
} }
static int gpio_irq_set_type(u32 irq, u32 type) static int gpio_irq_set_type(struct irq_data *d, u32 type)
{ {
int pin = irq_to_gpio(irq); int pin = irq_to_gpio(d->irq);
struct irq_desc *desc; struct irq_desc *desc;
u32 u; u32 u;
u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)); u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
if (!u) { if (!u) {
printk(KERN_ERR "orion gpio_irq_set_type failed " printk(KERN_ERR "orion gpio_irq_set_type failed "
"(irq %d, pin %d).\n", irq, pin); "(irq %d, pin %d).\n", d->irq, pin);
return -EINVAL; return -EINVAL;
} }
desc = irq_desc + irq; desc = irq_desc + d->irq;
/* /*
* Set edge/level type. * Set edge/level type.
...@@ -287,7 +286,7 @@ static int gpio_irq_set_type(u32 irq, u32 type) ...@@ -287,7 +286,7 @@ static int gpio_irq_set_type(u32 irq, u32 type)
} else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
desc->handle_irq = handle_level_irq; desc->handle_irq = handle_level_irq;
} else { } else {
printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type);
return -EINVAL; return -EINVAL;
} }
...@@ -325,10 +324,10 @@ static int gpio_irq_set_type(u32 irq, u32 type) ...@@ -325,10 +324,10 @@ static int gpio_irq_set_type(u32 irq, u32 type)
struct irq_chip orion_gpio_irq_chip = { struct irq_chip orion_gpio_irq_chip = {
.name = "orion_gpio_irq", .name = "orion_gpio_irq",
.ack = gpio_irq_ack, .irq_ack = gpio_irq_ack,
.mask = gpio_irq_mask, .irq_mask = gpio_irq_mask,
.unmask = gpio_irq_unmask, .irq_unmask = gpio_irq_unmask,
.set_type = gpio_irq_set_type, .irq_set_type = gpio_irq_set_type,
}; };
void orion_gpio_irq_handler(int pinoff) void orion_gpio_irq_handler(int pinoff)
......
...@@ -14,31 +14,31 @@ ...@@ -14,31 +14,31 @@
#include <linux/io.h> #include <linux/io.h>
#include <plat/irq.h> #include <plat/irq.h>
static void orion_irq_mask(u32 irq) static void orion_irq_mask(struct irq_data *d)
{ {
void __iomem *maskaddr = get_irq_chip_data(irq); void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
u32 mask; u32 mask;
mask = readl(maskaddr); mask = readl(maskaddr);
mask &= ~(1 << (irq & 31)); mask &= ~(1 << (d->irq & 31));
writel(mask, maskaddr); writel(mask, maskaddr);
} }
static void orion_irq_unmask(u32 irq) static void orion_irq_unmask(struct irq_data *d)
{ {
void __iomem *maskaddr = get_irq_chip_data(irq); void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
u32 mask; u32 mask;
mask = readl(maskaddr); mask = readl(maskaddr);
mask |= 1 << (irq & 31); mask |= 1 << (d->irq & 31);
writel(mask, maskaddr); writel(mask, maskaddr);
} }
static struct irq_chip orion_irq_chip = { static struct irq_chip orion_irq_chip = {
.name = "orion_irq", .name = "orion_irq",
.mask = orion_irq_mask, .irq_mask = orion_irq_mask,
.mask_ack = orion_irq_mask, .irq_mask_ack = orion_irq_mask,
.unmask = orion_irq_unmask, .irq_unmask = orion_irq_unmask,
}; };
void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
......
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