Commit 3c66eb4b authored by Matthias Kaehlcke's avatar Matthias Kaehlcke Committed by Greg Kroah-Hartman

tty: serial: qcom_geni_serial: Fix wrap around of TX buffer

Before commit a1fee899 ("tty: serial: qcom_geni_serial: Fix
softlock") the size of TX transfers was limited to the TX FIFO size,
and wrap arounds of the UART circular buffer were split into two
transfers. With the commit wrap around are allowed within a transfer.
The TX FIFO of the geni serial port uses a word size of 4 bytes. In
case of a circular buffer wrap within a transfer the driver currently
may write an incomplete word to the FIFO, with some bytes containing
data from the circular buffer and others being zero. Since the
transfer isn't completed yet the zero bytes are sent as if they were
actual data.

Handle wrap arounds of the TX buffer properly and ensure that words
written to the TX FIFO always contain valid data (unless the transfer
is completed).

Fixes: a1fee899 ("tty: serial: qcom_geni_serial: Fix softlock")
Signed-off-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: default avatarEvan Green <evgreen@chromium.org>
Tested-by: default avatarRyan Case <ryandcase@chromium.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a8da3c78
...@@ -744,7 +744,7 @@ static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, ...@@ -744,7 +744,7 @@ static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
avail *= port->tx_bytes_pw; avail *= port->tx_bytes_pw;
tail = xmit->tail; tail = xmit->tail;
chunk = min3(avail, pending, (size_t)(UART_XMIT_SIZE - tail)); chunk = min(avail, pending);
if (!chunk) if (!chunk)
goto out_write_wakeup; goto out_write_wakeup;
...@@ -766,19 +766,21 @@ static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, ...@@ -766,19 +766,21 @@ static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
memset(buf, 0, ARRAY_SIZE(buf)); memset(buf, 0, ARRAY_SIZE(buf));
tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw); tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
for (c = 0; c < tx_bytes ; c++)
buf[c] = xmit->buf[tail + c]; for (c = 0; c < tx_bytes ; c++) {
buf[c] = xmit->buf[tail++];
tail &= UART_XMIT_SIZE - 1;
}
iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
i += tx_bytes; i += tx_bytes;
tail += tx_bytes;
uport->icount.tx += tx_bytes; uport->icount.tx += tx_bytes;
remaining -= tx_bytes; remaining -= tx_bytes;
port->tx_remaining -= tx_bytes; port->tx_remaining -= tx_bytes;
} }
xmit->tail = tail & (UART_XMIT_SIZE - 1); xmit->tail = tail;
/* /*
* The tx fifo watermark is level triggered and latched. Though we had * The tx fifo watermark is level triggered and latched. Though we had
......
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