Commit 3d2abda0 authored by Chris Brandt's avatar Chris Brandt Committed by Simon Horman

ARM: dts: r7s72100: update sdhi clock bindings

The SDHI controller in the RZ/A1 has 2 clock sources per channel and both
need to be enabled/disabled for proper operation. This fixes the fact that
the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and
that all 4 clock sources need to be defined an used.
Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent c1ae3cfa
...@@ -162,9 +162,12 @@ mstp12_clks: mstp12_clks@fcfe0444 { ...@@ -162,9 +162,12 @@ mstp12_clks: mstp12_clks@fcfe0444 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0444 4>; reg = <0xfcfe0444 4>;
clocks = <&p1_clk>, <&p1_clk>; clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>; clock-indices = <
clock-output-names = "sdhi1", "sdhi0"; R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
>;
clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
}; };
}; };
...@@ -488,7 +491,9 @@ sdhi0: sd@e804e000 { ...@@ -488,7 +491,9 @@ sdhi0: sd@e804e000 {
GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI0>; clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>;
clock-names = "core", "cd";
cap-sd-highspeed; cap-sd-highspeed;
cap-sdio-irq; cap-sdio-irq;
status = "disabled"; status = "disabled";
...@@ -501,7 +506,9 @@ sdhi1: sd@e804e800 { ...@@ -501,7 +506,9 @@ sdhi1: sd@e804e800 {
GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI1>; clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>;
clock-names = "core", "cd";
cap-sd-highspeed; cap-sd-highspeed;
cap-sdio-irq; cap-sdio-irq;
status = "disabled"; status = "disabled";
......
...@@ -49,7 +49,9 @@ ...@@ -49,7 +49,9 @@
#define R7S72100_CLK_SPI4 3 #define R7S72100_CLK_SPI4 3
/* MSTP12 */ /* MSTP12 */
#define R7S72100_CLK_SDHI0 3 #define R7S72100_CLK_SDHI00 3
#define R7S72100_CLK_SDHI1 2 #define R7S72100_CLK_SDHI01 2
#define R7S72100_CLK_SDHI10 1
#define R7S72100_CLK_SDHI11 0
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
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