Commit 3d305dbd authored by Vennila Megavannan's avatar Vennila Megavannan Committed by Greg Kroah-Hartman

staging/rdma/hfi1: remove RxCtxRHQS from hfi1stats

Removed the RxCtxRHQS counter being dumped into dev_cntrs
Reviewed-by: default avatarDennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: default avatarVennila Megavannan <vennila.megavannan@intel.com>
Signed-off-by: default avatarJubin John <jubin.john@intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 323fd785
...@@ -1587,8 +1587,6 @@ static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = { ...@@ -1587,8 +1587,6 @@ static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
[C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs, [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
RCV_TID_FLOW_GEN_MISMATCH_CNT, RCV_TID_FLOW_GEN_MISMATCH_CNT,
CNTR_NORMAL), CNTR_NORMAL),
[C_RX_CTX_RHQS] = RXE32_DEV_CNTR_ELEM(RxCtxRHQS, RCV_CONTEXT_RHQ_STALL,
CNTR_NORMAL),
[C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL, [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
CNTR_NORMAL), CNTR_NORMAL),
[C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs, [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
......
...@@ -722,7 +722,6 @@ enum { ...@@ -722,7 +722,6 @@ enum {
C_RX_TID_FULL, C_RX_TID_FULL,
C_RX_TID_INVALID, C_RX_TID_INVALID,
C_RX_TID_FLGMS, C_RX_TID_FLGMS,
C_RX_CTX_RHQS,
C_RX_CTX_EGRS, C_RX_CTX_EGRS,
C_RCV_TID_FLSMS, C_RCV_TID_FLSMS,
C_CCE_PCI_CR_ST, C_CCE_PCI_CR_ST,
......
...@@ -379,7 +379,6 @@ ...@@ -379,7 +379,6 @@
#define DC_LCB_STS_ROUND_TRIP_LTP_CNT (DC_LCB_CSRS + 0x0000000004B0) #define DC_LCB_STS_ROUND_TRIP_LTP_CNT (DC_LCB_CSRS + 0x0000000004B0)
#define RCV_BUF_OVFL_CNT 10 #define RCV_BUF_OVFL_CNT 10
#define RCV_CONTEXT_EGR_STALL 22 #define RCV_CONTEXT_EGR_STALL 22
#define RCV_CONTEXT_RHQ_STALL 21
#define RCV_DATA_PKT_CNT 0 #define RCV_DATA_PKT_CNT 0
#define RCV_DWORD_CNT 1 #define RCV_DWORD_CNT 1
#define RCV_TID_FLOW_GEN_MISMATCH_CNT 20 #define RCV_TID_FLOW_GEN_MISMATCH_CNT 20
......
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