Commit 3dc6faa3 authored by Marco Pagani's avatar Marco Pagani Committed by Stephen Boyd

clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling

The function of_clk_add_provider() has been deprecated, so use its
suggested replacement of_clk_add_hw_provider() instead.

Since of_clk_add_hw_provider() can fail, like of_clk_add_provider(),
check its return value and do the error handling.

The return type of the init function has been changed to void since
the return value was not used, and the indentation of the parameters has
been aligned to match open parenthesis, as suggested by checkpatch.
Signed-off-by: default avatarMarco Pagani <marpagan@redhat.com>
Link: https://lore.kernel.org/r/20221209152913.1335068-7-marpagan@redhat.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 00720a90
......@@ -63,7 +63,7 @@ static const struct clk_ops clk_pll_ops = {
.get_parent = clk_pll_get_parent,
};
static struct clk_hw * __init __socfpga_pll_init(struct device_node *node,
static void __init __socfpga_pll_init(struct device_node *node,
const struct clk_ops *ops)
{
u32 reg;
......@@ -73,13 +73,14 @@ static struct clk_hw * __init __socfpga_pll_init(struct device_node *node,
const char *parent_name[SOCFGPA_MAX_PARENTS];
struct clk_init_data init;
struct device_node *clkmgr_np;
int rc;
int i = 0;
of_property_read_u32(node, "reg", &reg);
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (WARN_ON(!pll_clk))
return NULL;
return;
clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0);
......@@ -103,12 +104,25 @@ static struct clk_hw * __init __socfpga_pll_init(struct device_node *node,
pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
hw_clk = &pll_clk->hw.hw;
if (clk_hw_register(NULL, hw_clk)) {
kfree(pll_clk);
return NULL;
rc = clk_hw_register(NULL, hw_clk);
if (rc) {
pr_err("Could not register clock:%s\n", clk_name);
goto err_clk_hw_register;
}
rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk);
if (rc) {
pr_err("Could not register clock provider for node:%s\n",
clk_name);
goto err_of_clk_add_hw_provider;
}
of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
return hw_clk;
return;
err_of_clk_add_hw_provider:
clk_hw_unregister(hw_clk);
err_clk_hw_register:
kfree(pll_clk);
}
void __init socfpga_a10_pll_init(struct device_node *node)
......
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