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Commit 3e461977 authored by Kukjin Kim's avatar Kukjin Kim
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Merge branch 'next/topic-cleanup-dma' into next-samsung-cleanup

parents 03a0edd1 81b69636
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arch/arm/mach-s3c2410/dma.c
View file @ 3e461977
...@@ -47,38 +47,26 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { ...@@ -47,38 +47,26 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
.channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID, .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
.channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
.channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
}, },
[DMACH_SPI0] = { [DMACH_SPI0] = {
.name = "spi0", .name = "spi0",
.channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
}, },
[DMACH_SPI1] = { [DMACH_SPI1] = {
.name = "spi1", .name = "spi1",
.channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
}, },
[DMACH_UART0] = { [DMACH_UART0] = {
.name = "uart0", .name = "uart0",
.channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
}, },
[DMACH_UART1] = { [DMACH_UART1] = {
.name = "uart1", .name = "uart1",
.channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
}, },
[DMACH_UART2] = { [DMACH_UART2] = {
.name = "uart2", .name = "uart2",
.channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
}, },
[DMACH_TIMER] = { [DMACH_TIMER] = {
.name = "timer", .name = "timer",
...@@ -90,12 +78,10 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { ...@@ -90,12 +78,10 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
.name = "i2s-sdi", .name = "i2s-sdi",
.channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
.channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
}, },
[DMACH_I2S_OUT] = { [DMACH_I2S_OUT] = {
.name = "i2s-sdo", .name = "i2s-sdo",
.channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
}, },
[DMACH_USB_EP1] = { [DMACH_USB_EP1] = {
.name = "usb-ep1", .name = "usb-ep1",
......
arch/arm/mach-s3c2412/dma.c
View file @ 3e461977
...@@ -50,64 +50,46 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { ...@@ -50,64 +50,46 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
.name = "sdi", .name = "sdi",
.channels = MAP(S3C2412_DMAREQSEL_SDI), .channels = MAP(S3C2412_DMAREQSEL_SDI),
.channels_rx = MAP(S3C2412_DMAREQSEL_SDI), .channels_rx = MAP(S3C2412_DMAREQSEL_SDI),
.hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA,
.hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA,
}, },
[DMACH_SPI0] = { [DMACH_SPI0] = {
.name = "spi0", .name = "spi0",
.channels = MAP(S3C2412_DMAREQSEL_SPI0TX), .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
.channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX), .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX),
.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
}, },
[DMACH_SPI1] = { [DMACH_SPI1] = {
.name = "spi1", .name = "spi1",
.channels = MAP(S3C2412_DMAREQSEL_SPI1TX), .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
.channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX), .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX),
.hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT,
}, },
[DMACH_UART0] = { [DMACH_UART0] = {
.name = "uart0", .name = "uart0",
.channels = MAP(S3C2412_DMAREQSEL_UART0_0), .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
.channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0), .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0),
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
}, },
[DMACH_UART1] = { [DMACH_UART1] = {
.name = "uart1", .name = "uart1",
.channels = MAP(S3C2412_DMAREQSEL_UART1_0), .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
.channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0), .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0),
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
}, },
[DMACH_UART2] = { [DMACH_UART2] = {
.name = "uart2", .name = "uart2",
.channels = MAP(S3C2412_DMAREQSEL_UART2_0), .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
.channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0), .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0),
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
}, },
[DMACH_UART0_SRC2] = { [DMACH_UART0_SRC2] = {
.name = "uart0", .name = "uart0",
.channels = MAP(S3C2412_DMAREQSEL_UART0_1), .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
.channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1), .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1),
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
}, },
[DMACH_UART1_SRC2] = { [DMACH_UART1_SRC2] = {
.name = "uart1", .name = "uart1",
.channels = MAP(S3C2412_DMAREQSEL_UART1_1), .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
.channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1), .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1),
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
}, },
[DMACH_UART2_SRC2] = { [DMACH_UART2_SRC2] = {
.name = "uart2", .name = "uart2",
.channels = MAP(S3C2412_DMAREQSEL_UART2_1), .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
.channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1), .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1),
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
}, },
[DMACH_TIMER] = { [DMACH_TIMER] = {
.name = "timer", .name = "timer",
......
arch/arm/mach-s3c2440/dma.c
View file @ 3e461977
...@@ -48,38 +48,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { ...@@ -48,38 +48,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
.channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID, .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
.channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
.channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
}, },
[DMACH_SPI0] = { [DMACH_SPI0] = {
.name = "spi0", .name = "spi0",
.channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
}, },
[DMACH_SPI1] = { [DMACH_SPI1] = {
.name = "spi1", .name = "spi1",
.channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
}, },
[DMACH_UART0] = { [DMACH_UART0] = {
.name = "uart0", .name = "uart0",
.channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
}, },
[DMACH_UART1] = { [DMACH_UART1] = {
.name = "uart1", .name = "uart1",
.channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
}, },
[DMACH_UART2] = { [DMACH_UART2] = {
.name = "uart2", .name = "uart2",
.channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
}, },
[DMACH_TIMER] = { [DMACH_TIMER] = {
.name = "timer", .name = "timer",
...@@ -91,31 +79,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { ...@@ -91,31 +79,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
.name = "i2s-sdi", .name = "i2s-sdi",
.channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
.channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
}, },
[DMACH_I2S_OUT] = { [DMACH_I2S_OUT] = {
.name = "i2s-sdo", .name = "i2s-sdo",
.channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID, .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
.channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
}, },
[DMACH_PCM_IN] = { [DMACH_PCM_IN] = {
.name = "pcm-in", .name = "pcm-in",
.channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID, .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
.channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID, .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
.hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
}, },
[DMACH_PCM_OUT] = { [DMACH_PCM_OUT] = {
.name = "pcm-out", .name = "pcm-out",
.channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID, .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
.channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID, .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
.hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
}, },
[DMACH_MIC_IN] = { [DMACH_MIC_IN] = {
.name = "mic-in", .name = "mic-in",
.channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID, .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
.channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID, .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
.hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
}, },
[DMACH_USB_EP1] = { [DMACH_USB_EP1] = {
.name = "usb-ep1", .name = "usb-ep1",
......
arch/arm/mach-s3c2443/dma.c
View file @ 3e461977
...@@ -54,68 +54,46 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = { ...@@ -54,68 +54,46 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
[DMACH_SDI] = { [DMACH_SDI] = {
.name = "sdi", .name = "sdi",
.channels = MAP(S3C2443_DMAREQSEL_SDI), .channels = MAP(S3C2443_DMAREQSEL_SDI),
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
}, },
[DMACH_SPI0] = { [DMACH_SPI0] = {
.name = "spi0", .name = "spi0",
.channels = MAP(S3C2443_DMAREQSEL_SPI0TX), .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
}, },
[DMACH_SPI1] = { [DMACH_SPI1] = {
.name = "spi1", .name = "spi1",
.channels = MAP(S3C2443_DMAREQSEL_SPI1TX), .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
}, },
[DMACH_UART0] = { [DMACH_UART0] = {
.name = "uart0", .name = "uart0",
.channels = MAP(S3C2443_DMAREQSEL_UART0_0), .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
}, },
[DMACH_UART1] = { [DMACH_UART1] = {
.name = "uart1", .name = "uart1",
.channels = MAP(S3C2443_DMAREQSEL_UART1_0), .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
}, },
[DMACH_UART2] = { [DMACH_UART2] = {
.name = "uart2", .name = "uart2",
.channels = MAP(S3C2443_DMAREQSEL_UART2_0), .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
}, },
[DMACH_UART3] = { [DMACH_UART3] = {
.name = "uart3", .name = "uart3",
.channels = MAP(S3C2443_DMAREQSEL_UART3_0), .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
.hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
.hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
}, },
[DMACH_UART0_SRC2] = { [DMACH_UART0_SRC2] = {
.name = "uart0", .name = "uart0",
.channels = MAP(S3C2443_DMAREQSEL_UART0_1), .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
}, },
[DMACH_UART1_SRC2] = { [DMACH_UART1_SRC2] = {
.name = "uart1", .name = "uart1",
.channels = MAP(S3C2443_DMAREQSEL_UART1_1), .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
}, },
[DMACH_UART2_SRC2] = { [DMACH_UART2_SRC2] = {
.name = "uart2", .name = "uart2",
.channels = MAP(S3C2443_DMAREQSEL_UART2_1), .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
}, },
[DMACH_UART3_SRC2] = { [DMACH_UART3_SRC2] = {
.name = "uart3", .name = "uart3",
.channels = MAP(S3C2443_DMAREQSEL_UART3_1), .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
.hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
.hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
}, },
[DMACH_TIMER] = { [DMACH_TIMER] = {
.name = "timer", .name = "timer",
...@@ -124,27 +102,22 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = { ...@@ -124,27 +102,22 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
[DMACH_I2S_IN] = { [DMACH_I2S_IN] = {
.name = "i2s-sdi", .name = "i2s-sdi",
.channels = MAP(S3C2443_DMAREQSEL_I2SRX), .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
}, },
[DMACH_I2S_OUT] = { [DMACH_I2S_OUT] = {
.name = "i2s-sdo", .name = "i2s-sdo",
.channels = MAP(S3C2443_DMAREQSEL_I2STX), .channels = MAP(S3C2443_DMAREQSEL_I2STX),
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
}, },
[DMACH_PCM_IN] = { [DMACH_PCM_IN] = {
.name = "pcm-in", .name = "pcm-in",
.channels = MAP(S3C2443_DMAREQSEL_PCMIN), .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
.hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
}, },
[DMACH_PCM_OUT] = { [DMACH_PCM_OUT] = {
.name = "pcm-out", .name = "pcm-out",
.channels = MAP(S3C2443_DMAREQSEL_PCMOUT), .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
.hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
}, },
[DMACH_MIC_IN] = { [DMACH_MIC_IN] = {
.name = "mic-in", .name = "mic-in",
.channels = MAP(S3C2443_DMAREQSEL_MICIN), .channels = MAP(S3C2443_DMAREQSEL_MICIN),
.hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
}, },
}; };
......
arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
View file @ 3e461977
...@@ -18,11 +18,6 @@ extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS]; ...@@ -18,11 +18,6 @@ extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
#define DMA_CH_VALID (1<<31) #define DMA_CH_VALID (1<<31)
#define DMA_CH_NEVER (1<<30) #define DMA_CH_NEVER (1<<30)
struct s3c24xx_dma_addr {
unsigned long from;
unsigned long to;
};
/* struct s3c24xx_dma_map /* struct s3c24xx_dma_map
* *
* this holds the mapping information for the channel selected * this holds the mapping information for the channel selected
...@@ -31,7 +26,6 @@ struct s3c24xx_dma_addr { ...@@ -31,7 +26,6 @@ struct s3c24xx_dma_addr {
struct s3c24xx_dma_map { struct s3c24xx_dma_map {
const char *name; const char *name;
struct s3c24xx_dma_addr hw_addr;
unsigned long channels[S3C_DMA_CHANNELS]; unsigned long channels[S3C_DMA_CHANNELS];
unsigned long channels_rx[S3C_DMA_CHANNELS]; unsigned long channels_rx[S3C_DMA_CHANNELS];
......
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