Commit 3e4f964d authored by Marek Vasut's avatar Marek Vasut Committed by Mark Brown

ASoC: dt-bindings: fsl-sai: Sort main section properties

Sort main section properties, no functional change.
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221104160315.213836-3-marex@denx.deSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent ef555955
...@@ -43,16 +43,6 @@ properties: ...@@ -43,16 +43,6 @@ properties:
reg: reg:
maxItems: 1 maxItems: 1
interrupts:
items:
- description: receive and transmit interrupt
dmas:
maxItems: 2
dma-names:
maxItems: 2
clocks: clocks:
items: items:
- description: The ipg clock for register access - description: The ipg clock for register access
...@@ -84,19 +74,37 @@ properties: ...@@ -84,19 +74,37 @@ properties:
- const: pll11k - const: pll11k
minItems: 4 minItems: 4
lsb-first: dmas:
description: | maxItems: 2
Configures whether the LSB or the MSB is transmitted
first for the fifo data. If this property is absent, dma-names:
the MSB is transmitted first as default, or the LSB maxItems: 2
is transmitted first.
type: boolean interrupts:
items:
- description: receive and transmit interrupt
big-endian: big-endian:
description: | description: |
required if all the SAI registers are big-endian rather than little-endian. required if all the SAI registers are big-endian rather than little-endian.
type: boolean type: boolean
fsl,dataline:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
Configure the dataline. It has 3 value for each configuration
maxItems: 16
items:
items:
- description: format Default(0), I2S(1) or PDM(2)
enum: [0, 1, 2]
- description: dataline mask for 'rx'
- description: dataline mask for 'tx'
fsl,sai-mclk-direction-output:
description: SAI will output the SAI MCLK clock.
type: boolean
fsl,sai-synchronous-rx: fsl,sai-synchronous-rx:
description: | description: |
SAI will work in the synchronous mode (sync Tx with Rx) which means SAI will work in the synchronous mode (sync Tx with Rx) which means
...@@ -115,26 +123,18 @@ properties: ...@@ -115,26 +123,18 @@ properties:
of transmitter. of transmitter.
type: boolean type: boolean
fsl,dataline:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
Configure the dataline. It has 3 value for each configuration
maxItems: 16
items:
items:
- description: format Default(0), I2S(1) or PDM(2)
enum: [0, 1, 2]
- description: dataline mask for 'rx'
- description: dataline mask for 'tx'
fsl,sai-mclk-direction-output:
description: SAI will output the SAI MCLK clock.
type: boolean
fsl,shared-interrupt: fsl,shared-interrupt:
description: Interrupt is shared with other modules. description: Interrupt is shared with other modules.
type: boolean type: boolean
lsb-first:
description: |
Configures whether the LSB or the MSB is transmitted
first for the fifo data. If this property is absent,
the MSB is transmitted first as default, or the LSB
is transmitted first.
type: boolean
"#sound-dai-cells": "#sound-dai-cells":
const: 0 const: 0
description: optional, some dts node didn't add it. description: optional, some dts node didn't add it.
...@@ -175,11 +175,11 @@ allOf: ...@@ -175,11 +175,11 @@ allOf:
required: required:
- compatible - compatible
- reg - reg
- interrupts
- dmas
- dma-names
- clocks - clocks
- clock-names - clock-names
- dmas
- dma-names
- interrupts
additionalProperties: false additionalProperties: false
......
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