Commit 3f02735e authored by Florian Fainelli's avatar Florian Fainelli Committed by David S. Miller

Revert "net: dsa: bcm_sf2: Also configure Port 5 for 2Gb/sec on 7278"

This reverts commit 7458bd54 ("net: dsa:
bcm_sf2: Also configure Port 5 for 2Gb/sec on 7278") as it causes
advanced congestion buffering issues with 7278 switch devices when using
their internal Giabit PHY. While this is being debugged, continue with
conservative defaults that work and do not cause packet loss.

Fixes: 7458bd54 ("net: dsa: bcm_sf2: Also configure Port 5 for 2Gb/sec on 7278")
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Reviewed-by: default avatarVivien Didelot <vivien.didelot@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bb0858d8
...@@ -616,9 +616,6 @@ static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, ...@@ -616,9 +616,6 @@ static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
if (state->duplex == DUPLEX_FULL) if (state->duplex == DUPLEX_FULL)
reg |= DUPLX_MODE; reg |= DUPLX_MODE;
if (priv->type == BCM7278_DEVICE_ID && dsa_is_cpu_port(ds, port))
reg |= GMIIP_SPEED_UP_2G;
core_writel(priv, reg, offset); core_writel(priv, reg, offset);
} }
......
...@@ -178,7 +178,6 @@ enum bcm_sf2_reg_offs { ...@@ -178,7 +178,6 @@ enum bcm_sf2_reg_offs {
#define RXFLOW_CNTL (1 << 4) #define RXFLOW_CNTL (1 << 4)
#define TXFLOW_CNTL (1 << 5) #define TXFLOW_CNTL (1 << 5)
#define SW_OVERRIDE (1 << 6) #define SW_OVERRIDE (1 << 6)
#define GMIIP_SPEED_UP_2G (1 << 7)
#define CORE_WATCHDOG_CTRL 0x001e4 #define CORE_WATCHDOG_CTRL 0x001e4
#define SOFTWARE_RESET (1 << 7) #define SOFTWARE_RESET (1 << 7)
......
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