Commit 3f066e88 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'for-5.16/parisc-7' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

Pull parisc architecture fixes from Helge Deller:

 - Fix a bug in the C code which calculates the relevant futex spinlock
   based on the futex virtual address. In some cases a wrong spinlock
   (compared to what is calculated in the assembly code path) was
   choosen which then can lead to deadlocks.

 - The 64-bit kernel missed to clip the LWS number in the
   Light-weight-syscall path for 32-bit processes.

 - Prevent CPU register dump to show stale value in IIR register on
   access rights traps.

 - Remove unused ARCH_DEFCONFIG entries.

* tag 'for-5.16/parisc-7' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: remove ARCH_DEFCONFIG
  parisc: Fix mask used to select futex spinlock
  parisc: Correct completer in lws start
  parisc: Clear stale IIR value on instruction access rights trap
parents 07400405 aacb2016
...@@ -85,11 +85,6 @@ config MMU ...@@ -85,11 +85,6 @@ config MMU
config STACK_GROWSUP config STACK_GROWSUP
def_bool y def_bool y
config ARCH_DEFCONFIG
string
default "arch/parisc/configs/generic-32bit_defconfig" if !64BIT
default "arch/parisc/configs/generic-64bit_defconfig" if 64BIT
config GENERIC_LOCKBREAK config GENERIC_LOCKBREAK
bool bool
default y default y
......
...@@ -14,7 +14,7 @@ static inline void ...@@ -14,7 +14,7 @@ static inline void
_futex_spin_lock(u32 __user *uaddr) _futex_spin_lock(u32 __user *uaddr)
{ {
extern u32 lws_lock_start[]; extern u32 lws_lock_start[];
long index = ((long)uaddr & 0x3f8) >> 1; long index = ((long)uaddr & 0x7f8) >> 1;
arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index]; arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index];
preempt_disable(); preempt_disable();
arch_spin_lock(s); arch_spin_lock(s);
...@@ -24,7 +24,7 @@ static inline void ...@@ -24,7 +24,7 @@ static inline void
_futex_spin_unlock(u32 __user *uaddr) _futex_spin_unlock(u32 __user *uaddr)
{ {
extern u32 lws_lock_start[]; extern u32 lws_lock_start[];
long index = ((long)uaddr & 0x3f8) >> 1; long index = ((long)uaddr & 0x7f8) >> 1;
arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index]; arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index];
arch_spin_unlock(s); arch_spin_unlock(s);
preempt_enable(); preempt_enable();
......
...@@ -472,7 +472,7 @@ lws_start: ...@@ -472,7 +472,7 @@ lws_start:
extrd,u %r1,PSW_W_BIT,1,%r1 extrd,u %r1,PSW_W_BIT,1,%r1
/* sp must be aligned on 4, so deposit the W bit setting into /* sp must be aligned on 4, so deposit the W bit setting into
* the bottom of sp temporarily */ * the bottom of sp temporarily */
or,ev %r1,%r30,%r30 or,od %r1,%r30,%r30
/* Clip LWS number to a 32-bit value for 32-bit processes */ /* Clip LWS number to a 32-bit value for 32-bit processes */
depdi 0, 31, 32, %r20 depdi 0, 31, 32, %r20
......
...@@ -730,6 +730,8 @@ void notrace handle_interruption(int code, struct pt_regs *regs) ...@@ -730,6 +730,8 @@ void notrace handle_interruption(int code, struct pt_regs *regs)
} }
mmap_read_unlock(current->mm); mmap_read_unlock(current->mm);
} }
/* CPU could not fetch instruction, so clear stale IIR value. */
regs->iir = 0xbaadf00d;
fallthrough; fallthrough;
case 27: case 27:
/* Data memory protection ID trap */ /* Data memory protection ID trap */
......
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