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Commit 3f5ba636 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-msm-next-2023-10-17' of https://gitlab.freedesktop.org/drm/msm into drm-next 

Updates for v6.7

DP:
- use existing helpers for DPCD handling instead of open-coded functions
- set the subconnector type according to the plugged cable / dongle
  skip validity check for DP CTS EDID checksum

DPU:
- continued migration of feature flags to use core revision checks
- reworked interrupts code to use '0' as NO_IRQ, removed raw IRQ indices
  from log / trace output

gpu:
- a7xx support (a730, a740)
- fixes and additional speedbins for a635, a643

core:
- decouple msm_drv from kms to more cleanly support headless devices (like
  imx5+a2xx)

From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvzkBL2_OgyOeP_b6rVEjrNdfm8jcKzaB04HqHyT5jYwA@mail.gmail.comSigned-off-by: default avatarDave Airlie <airlied@redhat.com>
parents 7cd62eab b08d26da
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Showing with 2365 additions and 1403 deletions
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
View file @ 3f5ba636
......@@ -114,6 +114,7 @@ properties:
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Output endpoint of the controller
properties:
endpoint:
......
Documentation/devicetree/bindings/display/msm/gmu.yaml
View file @ 3f5ba636
......@@ -21,7 +21,7 @@ properties:
compatible:
oneOf:
- items:
- pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
- pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
- const: qcom,adreno-gmu
- const: qcom,adreno-gmu-wrapper
......@@ -64,6 +64,10 @@ properties:
iommus:
maxItems: 1
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM
operating-points-v2: true
opp-table:
......@@ -213,6 +217,47 @@ allOf:
- const: axi
- const: memnoc
- if:
properties:
compatible:
contains:
enum:
- qcom,adreno-gmu-730.1
- qcom,adreno-gmu-740.1
then:
properties:
reg:
items:
- description: Core GMU registers
- description: Resource controller registers
- description: GMU PDC registers
reg-names:
items:
- const: gmu
- const: rscc
- const: gmu_pdc
clocks:
items:
- description: GPU AHB clock
- description: GMU clock
- description: GPU CX clock
- description: GPU AXI clock
- description: GPU MEMNOC clock
- description: GMU HUB clock
- description: GPUSS DEMET clock
clock-names:
items:
- const: ahb
- const: gmu
- const: cxo
- const: axi
- const: memnoc
- const: hub
- const: demet
required:
- qcom,qmp
- if:
properties:
compatible:
......
Documentation/devicetree/bindings/display/msm/gpu.yaml
View file @ 3f5ba636
......@@ -23,7 +23,7 @@ properties:
The driver is parsing the compat string for Adreno to
figure out the gpu-id and patch level.
items:
- pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
- pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$'
- const: qcom,adreno
- description: |
The driver is parsing the compat string for Imageon to
......@@ -203,7 +203,7 @@ allOf:
properties:
compatible:
contains:
pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$'
then: # Starting with A6xx, the clocks are usually defined in the GMU node
properties:
......
Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml
View file @ 3f5ba636
......@@ -38,12 +38,16 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,msm8998-dpu
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -52,6 +56,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,dsi-phy-10nm-8998
......
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
View file @ 3f5ba636
......@@ -44,18 +44,24 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,qcm2290-dpu
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,dsi-ctrl-6g-qcm2290
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,dsi-phy-14nm-2290
......
Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml
View file @ 3f5ba636
......@@ -44,18 +44,24 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sc7180-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sc7180-dp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -64,6 +70,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,dsi-phy-10nm
......
Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
View file @ 3f5ba636
......@@ -44,18 +44,24 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sc7280-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sc7280-dp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -64,12 +70,16 @@ patternProperties:
"^edp@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sc7280-edp
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
enum:
......
Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
View file @ 3f5ba636
......@@ -34,12 +34,16 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sc8280xp-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
enum:
......
Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml
View file @ 3f5ba636
......@@ -42,18 +42,24 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sdm845-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sdm845-dp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -62,6 +68,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,dsi-phy-10nm
......
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
View file @ 3f5ba636
......@@ -32,12 +32,16 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm6115-dpu
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
oneOf:
......@@ -50,6 +54,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,dsi-phy-14nm-2290
......
Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml
View file @ 3f5ba636
......@@ -43,12 +43,16 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm6125-dpu
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -57,6 +61,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm6125-dsi-phy-14nm
......
Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
View file @ 3f5ba636
......@@ -43,12 +43,16 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm6350-dpu
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -57,6 +61,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,dsi-phy-10nm
......
Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
View file @ 3f5ba636
......@@ -43,12 +43,16 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm6375-dpu
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -57,6 +61,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm6375-dsi-phy-7nm
......
Documentation/devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml
View file @ 3f5ba636
......@@ -47,12 +47,16 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm8150-dpu
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -61,6 +65,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,dsi-phy-7nm
......
Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml
View file @ 3f5ba636
......@@ -46,12 +46,16 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm8250-dpu
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -60,6 +64,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,dsi-phy-7nm
......
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
View file @ 3f5ba636
......@@ -48,18 +48,24 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm8350-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm8350-dp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -68,6 +74,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm8350-dsi-phy-5nm
......
Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
View file @ 3f5ba636
......@@ -38,12 +38,16 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm8450-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -52,6 +56,8 @@ patternProperties:
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -60,6 +66,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm8450-dsi-phy-5nm
......
Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
View file @ 3f5ba636
......@@ -38,12 +38,16 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm8550-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -52,6 +56,8 @@ patternProperties:
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
......@@ -60,6 +66,8 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sm8550-dsi-phy-4nm
......
drivers/gpu/drm/msm/Makefile
View file @ 3f5ba636
......@@ -106,6 +106,7 @@ msm-y += \
msm_gpu_devfreq.o \
msm_io_utils.o \
msm_iommu.o \
msm_kms.o \
msm_perf.o \
msm_rd.o \
msm_ringbuffer.o \
......
drivers/gpu/drm/msm/adreno/a6xx.xml.h
View file @ 3f5ba636
......@@ -1114,6 +1114,12 @@ enum a6xx_tex_type {
#define REG_A6XX_CP_MISC_CNTL 0x00000840
#define REG_A6XX_CP_APRIV_CNTL 0x00000844
#define A6XX_CP_APRIV_CNTL_CDWRITE 0x00000040
#define A6XX_CP_APRIV_CNTL_CDREAD 0x00000020
#define A6XX_CP_APRIV_CNTL_RBRPWB 0x00000008
#define A6XX_CP_APRIV_CNTL_RBPRIVLEVEL 0x00000004
#define A6XX_CP_APRIV_CNTL_RBFETCH 0x00000002
#define A6XX_CP_APRIV_CNTL_ICACHE 0x00000001
#define REG_A6XX_CP_PREEMPT_THRESHOLD 0x000008c0
......@@ -1939,6 +1945,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00
#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122
#define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f
#define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff
#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
......@@ -8252,5 +8260,6 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
#define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x00000039
#endif /* A6XX_XML */
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
View file @ 3f5ba636
......@@ -8,6 +8,7 @@
#include <linux/iopoll.h>
#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/soc/qcom/qcom_aoss.h>
#include "msm_drv.h"
#include "a6xx_hfi.h"
......@@ -96,6 +97,8 @@ struct a6xx_gmu {
/* For power domain callback */
struct notifier_block pd_nb;
struct completion pd_gate;
struct qmp *qmp;
};
static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
......
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
View file @ 3f5ba636
......@@ -360,6 +360,12 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
#define REG_A6XX_GMU_GENERAL_7 0x000051cc
#define REG_A6XX_GMU_GENERAL_8 0x000051cd
#define REG_A6XX_GMU_GENERAL_9 0x000051ce
#define REG_A6XX_GMU_GENERAL_10 0x000051cf
#define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d
#define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920
......@@ -471,6 +477,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
#define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101
#define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740 0x00000154
#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180
#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346
......
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
View file @ 3f5ba636
......@@ -882,12 +882,13 @@ static void a6xx_snapshot_gmu_hfi_history(struct msm_gpu *gpu,
}
}
#define A6XX_REGLIST_SIZE 1
#define A6XX_GBIF_REGLIST_SIZE 1
static void a6xx_get_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
{
int i, count = ARRAY_SIZE(a6xx_ahb_reglist) +
int i, count = A6XX_REGLIST_SIZE +
ARRAY_SIZE(a6xx_reglist) +
ARRAY_SIZE(a6xx_hlsq_reglist) + A6XX_GBIF_REGLIST_SIZE;
int index = 0;
......@@ -901,12 +902,20 @@ static void a6xx_get_registers(struct msm_gpu *gpu,
a6xx_state->nr_registers = count;
for (i = 0; i < ARRAY_SIZE(a6xx_ahb_reglist); i++)
if (adreno_is_a7xx(adreno_gpu))
a6xx_get_ahb_gpu_registers(gpu,
a6xx_state, &a6xx_ahb_reglist[i],
a6xx_state, &a7xx_ahb_reglist,
&a6xx_state->registers[index++]);
else
a6xx_get_ahb_gpu_registers(gpu,
a6xx_state, &a6xx_ahb_reglist,
&a6xx_state->registers[index++]);
if (a6xx_has_gbif(adreno_gpu))
if (adreno_is_a7xx(adreno_gpu))
a6xx_get_ahb_gpu_registers(gpu,
a6xx_state, &a7xx_gbif_reglist,
&a6xx_state->registers[index++]);
else if (a6xx_has_gbif(adreno_gpu))
a6xx_get_ahb_gpu_registers(gpu,
a6xx_state, &a6xx_gbif_reglist,
&a6xx_state->registers[index++]);
......@@ -948,6 +957,18 @@ static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu)
return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14;
}
static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu)
{
/*
* The value at CP_ROQ_THRESHOLDS_2[20:31] is in 4dword units.
* That register however is not directly accessible from APSS on A7xx.
* Program the SQE_UCODE_DBG_ADDR with offset=0x70d3 and read the value.
*/
gpu_write(gpu, REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 0x70d3);
return 4 * (gpu_read(gpu, REG_A6XX_CP_SQE_UCODE_DBG_DATA) >> 20);
}
/* Read a block of data from an indexed register pair */
static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
......@@ -1019,8 +1040,40 @@ static void a6xx_get_indexed_registers(struct msm_gpu *gpu,
/* Restore the size in the hardware */
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, mempool_size);
}
a6xx_state->nr_indexed_regs = count;
static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
int i, indexed_count, mempool_count;
indexed_count = ARRAY_SIZE(a7xx_indexed_reglist);
mempool_count = ARRAY_SIZE(a7xx_cp_bv_mempool_indexed);
a6xx_state->indexed_regs = state_kcalloc(a6xx_state,
indexed_count + mempool_count,
sizeof(*a6xx_state->indexed_regs));
if (!a6xx_state->indexed_regs)
return;
a6xx_state->nr_indexed_regs = indexed_count + mempool_count;
/* First read the common regs */
for (i = 0; i < indexed_count; i++)
a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_indexed_reglist[i],
&a6xx_state->indexed_regs[i]);
gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, 0, BIT(2));
gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, 0, BIT(2));
/* Get the contents of the CP_BV mempool */
for (i = 0; i < mempool_count; i++)
a6xx_get_indexed_regs(gpu, a6xx_state, a7xx_cp_bv_mempool_indexed,
&a6xx_state->indexed_regs[indexed_count - 1 + i]);
gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(2), 0);
gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, BIT(2), 0);
return;
}
struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
......@@ -1056,6 +1109,12 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
return &a6xx_state->base;
/* Get the banks of indexed registers */
if (adreno_is_a7xx(adreno_gpu)) {
a7xx_get_indexed_registers(gpu, a6xx_state);
/* Further codeflow is untested on A7xx. */
return &a6xx_state->base;
}
a6xx_get_indexed_registers(gpu, a6xx_state);
/*
......
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
View file @ 3f5ba636
......@@ -328,9 +328,8 @@ static const u32 a6xx_gbif_registers[] = {
0x3C00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xE3A, 0xE3A,
};
static const struct a6xx_registers a6xx_ahb_reglist[] = {
REGS(a6xx_ahb_registers, 0, 0),
};
static const struct a6xx_registers a6xx_ahb_reglist =
REGS(a6xx_ahb_registers, 0, 0);
static const struct a6xx_registers a6xx_vbif_reglist =
REGS(a6xx_vbif_registers, 0, 0);
......@@ -338,6 +337,27 @@ static const struct a6xx_registers a6xx_vbif_reglist =
static const struct a6xx_registers a6xx_gbif_reglist =
REGS(a6xx_gbif_registers, 0, 0);
static const u32 a7xx_ahb_registers[] = {
/* RBBM_STATUS */
0x210, 0x210,
/* RBBM_STATUS2-3 */
0x212, 0x213,
};
static const u32 a7xx_gbif_registers[] = {
0x3c00, 0x3c0b,
0x3c40, 0x3c42,
0x3c45, 0x3c47,
0x3c49, 0x3c4a,
0x3cc0, 0x3cd1,
};
static const struct a6xx_registers a7xx_ahb_reglist=
REGS(a7xx_ahb_registers, 0, 0);
static const struct a6xx_registers a7xx_gbif_reglist =
REGS(a7xx_gbif_registers, 0, 0);
static const u32 a6xx_gmu_gx_registers[] = {
/* GMU GX */
0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
......@@ -384,14 +404,17 @@ static const struct a6xx_registers a6xx_gmu_reglist[] = {
};
static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);
static struct a6xx_indexed_registers {
struct a6xx_indexed_registers {
const char *name;
u32 addr;
u32 data;
u32 count;
u32 (*count_fn)(struct msm_gpu *gpu);
} a6xx_indexed_reglist[] = {
};
static struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
......@@ -402,11 +425,43 @@ static struct a6xx_indexed_registers {
REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},
};
static struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
{ "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,
REG_A7XX_CP_BV_SQE_STAT_DATA, 0x33, NULL },
{ "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL },
{ "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL },
{ "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR,
REG_A7XX_CP_SQE_AC_STAT_DATA, 0x33, NULL },
{ "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL },
{ "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL },
{ "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL },
{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size },
};
static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,
};
static struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {
{ "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL },
{ "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,
REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2100, NULL },
};
#define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }
static const struct a6xx_debugbus_block {
......
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
View file @ 3f5ba636
......@@ -5,6 +5,8 @@
#include <linux/circ_buf.h>
#include <linux/list.h>
#include <soc/qcom/cmd-db.h>
#include "a6xx_gmu.h"
#include "a6xx_gmu.xml.h"
#include "a6xx_gpu.h"
......@@ -506,6 +508,88 @@ static void adreno_7c3_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
msg->cnoc_cmds_data[0][0] = 0x40000000;
msg->cnoc_cmds_data[1][0] = 0x60000001;
}
static void a730_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
{
msg->bw_level_num = 12;
msg->ddr_cmds_num = 3;
msg->ddr_wait_bitmask = 0x7;
msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0");
msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0");
msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV");
msg->ddr_cmds_data[0][0] = 0x40000000;
msg->ddr_cmds_data[0][1] = 0x40000000;
msg->ddr_cmds_data[0][2] = 0x40000000;
msg->ddr_cmds_data[1][0] = 0x600002e8;
msg->ddr_cmds_data[1][1] = 0x600003d0;
msg->ddr_cmds_data[1][2] = 0x60000008;
msg->ddr_cmds_data[2][0] = 0x6000068d;
msg->ddr_cmds_data[2][1] = 0x6000089a;
msg->ddr_cmds_data[2][2] = 0x60000008;
msg->ddr_cmds_data[3][0] = 0x600007f2;
msg->ddr_cmds_data[3][1] = 0x60000a6e;
msg->ddr_cmds_data[3][2] = 0x60000008;
msg->ddr_cmds_data[4][0] = 0x600009e5;
msg->ddr_cmds_data[4][1] = 0x60000cfd;
msg->ddr_cmds_data[4][2] = 0x60000008;
msg->ddr_cmds_data[5][0] = 0x60000b29;
msg->ddr_cmds_data[5][1] = 0x60000ea6;
msg->ddr_cmds_data[5][2] = 0x60000008;
msg->ddr_cmds_data[6][0] = 0x60001698;
msg->ddr_cmds_data[6][1] = 0x60001da8;
msg->ddr_cmds_data[6][2] = 0x60000008;
msg->ddr_cmds_data[7][0] = 0x600018d2;
msg->ddr_cmds_data[7][1] = 0x60002093;
msg->ddr_cmds_data[7][2] = 0x60000008;
msg->ddr_cmds_data[8][0] = 0x60001e66;
msg->ddr_cmds_data[8][1] = 0x600027e6;
msg->ddr_cmds_data[8][2] = 0x60000008;
msg->ddr_cmds_data[9][0] = 0x600027c2;
msg->ddr_cmds_data[9][1] = 0x6000342f;
msg->ddr_cmds_data[9][2] = 0x60000008;
msg->ddr_cmds_data[10][0] = 0x60002e71;
msg->ddr_cmds_data[10][1] = 0x60003cf5;
msg->ddr_cmds_data[10][2] = 0x60000008;
msg->ddr_cmds_data[11][0] = 0x600030ae;
msg->ddr_cmds_data[11][1] = 0x60003fe5;
msg->ddr_cmds_data[11][2] = 0x60000008;
msg->cnoc_cmds_num = 1;
msg->cnoc_wait_bitmask = 0x1;
msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0");
msg->cnoc_cmds_data[0][0] = 0x40000000;
msg->cnoc_cmds_data[1][0] = 0x60000001;
}
static void a740_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
{
msg->bw_level_num = 1;
msg->ddr_cmds_num = 3;
msg->ddr_wait_bitmask = 0x7;
msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0");
msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0");
msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV");
msg->ddr_cmds_data[0][0] = 0x40000000;
msg->ddr_cmds_data[0][1] = 0x40000000;
msg->ddr_cmds_data[0][2] = 0x40000000;
/* TODO: add a proper dvfs table */
msg->cnoc_cmds_num = 1;
msg->cnoc_wait_bitmask = 0x1;
msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0");
msg->cnoc_cmds_data[0][0] = 0x40000000;
msg->cnoc_cmds_data[1][0] = 0x60000001;
}
static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
{
/* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
......@@ -564,6 +648,10 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
a660_build_bw_table(&msg);
else if (adreno_is_a690(adreno_gpu))
a690_build_bw_table(&msg);
else if (adreno_is_a730(adreno_gpu))
a730_build_bw_table(&msg);
else if (adreno_is_a740_family(adreno_gpu))
a740_build_bw_table(&msg);
else
a6xx_build_bw_table(&msg);
......
drivers/gpu/drm/msm/adreno/adreno_device.c
View file @ 3f5ba636
......@@ -331,7 +331,7 @@ static const struct adreno_info gpulist[] = {
),
}, {
.machine = "qcom,sm6375",
.chip_ids = ADRENO_CHIP_IDS(0x06010900),
.chip_ids = ADRENO_CHIP_IDS(0x06010901),
.family = ADRENO_6XX_GEN1,
.revn = 619,
.fw = {
......@@ -454,11 +454,13 @@ static const struct adreno_info gpulist[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a660_zap.mbn",
.hwcg = a660_hwcg,
.address_space_size = SZ_16G,
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 117, 0 },
{ 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */
{ 190, 1 },
),
}, {
......@@ -490,6 +492,36 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a690_zap.mdt",
.hwcg = a690_hwcg,
.address_space_size = SZ_16G,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x07030001),
.family = ADRENO_7XX_GEN1,
.fw = {
[ADRENO_FW_SQE] = "a730_sqe.fw",
[ADRENO_FW_GMU] = "gmu_gen70000.bin",
},
.gmem = SZ_2M,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a730_zap.mdt",
.hwcg = a730_hwcg,
.address_space_size = SZ_16G,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
.family = ADRENO_7XX_GEN2,
.fw = {
[ADRENO_FW_SQE] = "a740_sqe.fw",
[ADRENO_FW_GMU] = "gmu_gen70200.bin",
},
.gmem = 3 * SZ_1M,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a740_zap.mdt",
.hwcg = a740_hwcg,
.address_space_size = SZ_16G,
},
};
......
drivers/gpu/drm/msm/adreno/adreno_gpu.c
View file @ 3f5ba636
......@@ -323,7 +323,11 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
*value = adreno_gpu->info->gmem;
return 0;
case MSM_PARAM_GMEM_BASE:
*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
if (adreno_is_a650_family(adreno_gpu) ||
adreno_is_a740_family(adreno_gpu))
*value = 0;
else
*value = 0x100000;
return 0;
case MSM_PARAM_CHIP_ID:
*value = adreno_gpu->chip_id;
......@@ -567,6 +571,7 @@ int adreno_hw_init(struct msm_gpu *gpu)
ring->cur = ring->start;
ring->next = ring->start;
ring->memptrs->rptr = 0;
ring->memptrs->bv_fence = ring->fctx->completed_fence;
/* Detect and clean up an impossible fence, ie. if GPU managed
* to scribble something invalid, we don't want that to confuse
......
drivers/gpu/drm/msm/adreno/adreno_gpu.h
View file @ 3f5ba636
......@@ -46,6 +46,8 @@ enum adreno_family {
ADRENO_6XX_GEN2, /* a640 family */
ADRENO_6XX_GEN3, /* a650 family */
ADRENO_6XX_GEN4, /* a660 family */
ADRENO_7XX_GEN1, /* a730 family */
ADRENO_7XX_GEN2, /* a740 family */
};
#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
......@@ -75,7 +77,7 @@ struct adreno_reglist {
};
extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a730_hwcg[], a740_hwcg[];
struct adreno_speedbin {
uint16_t fuse;
......@@ -391,7 +393,8 @@ static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
{
if (WARN_ON_ONCE(!gpu->info))
return false;
return gpu->info->family >= ADRENO_6XX_GEN3;
return gpu->info->family == ADRENO_6XX_GEN3 ||
gpu->info->family == ADRENO_6XX_GEN4;
}
static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
......@@ -401,6 +404,31 @@ static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
return gpu->info->family == ADRENO_6XX_GEN2;
}
static inline int adreno_is_a730(struct adreno_gpu *gpu)
{
return gpu->info->chip_ids[0] == 0x07030001;
}
static inline int adreno_is_a740(struct adreno_gpu *gpu)
{
return gpu->info->chip_ids[0] == 0x43050a01;
}
/* Placeholder to make future diffs smaller */
static inline int adreno_is_a740_family(struct adreno_gpu *gpu)
{
if (WARN_ON_ONCE(!gpu->info))
return false;
return gpu->info->family == ADRENO_7XX_GEN2;
}
static inline int adreno_is_a7xx(struct adreno_gpu *gpu)
{
/* Update with non-fake (i.e. non-A702) Gen 7 GPUs */
return gpu->info->family == ADRENO_7XX_GEN1 ||
adreno_is_a740_family(gpu);
}
u64 adreno_private_address_space_size(struct msm_gpu *gpu);
int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
uint32_t param, uint64_t *value, uint32_t *len);
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
View file @ 3f5ba636
......@@ -244,7 +244,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = {
.prog_fetch_lines_worst_case = 21,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x280,
......@@ -253,7 +252,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = {
.prog_fetch_lines_worst_case = 21,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x6b000, .len = 0x280,
......@@ -262,7 +260,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = {
.prog_fetch_lines_worst_case = 21,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x6b800, .len = 0x280,
......@@ -270,7 +267,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = {
.prog_fetch_lines_worst_case = 21,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
.intr_tear_rd_ptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
View file @ 3f5ba636
......@@ -260,7 +260,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x280,
......@@ -269,7 +268,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x6b000, .len = 0x280,
......@@ -278,7 +276,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x6b800, .len = 0x280,
......@@ -287,7 +284,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
.intr_tear_rd_ptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
View file @ 3f5ba636
......@@ -220,7 +220,6 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
......@@ -228,7 +227,6 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
......@@ -236,7 +234,6 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = -1,
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
......@@ -244,7 +241,6 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = -1,
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x72000, .len = 0xd4,
......@@ -252,7 +248,6 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
.intr_rdptr = -1,
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x72800, .len = 0xd4,
......@@ -260,7 +255,6 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
.intr_rdptr = -1,
},
};
......@@ -307,7 +301,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2bc,
......@@ -337,7 +330,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
.intr_tear_rd_ptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
View file @ 3f5ba636
......@@ -219,7 +219,6 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
......@@ -227,7 +226,6 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
......@@ -235,7 +233,6 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = -1,
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
......@@ -243,7 +240,6 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = -1,
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x72000, .len = 0xd4,
......@@ -251,7 +247,6 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
.intr_rdptr = -1,
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x72800, .len = 0xd4,
......@@ -259,7 +254,6 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
.intr_rdptr = -1,
},
};
......@@ -314,7 +308,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2bc,
......@@ -346,7 +339,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_4", .id = INTF_4,
.base = 0x6c000, .len = 0x280,
......@@ -356,7 +348,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_5", .id = INTF_5,
.base = 0x6c800, .len = 0x280,
......@@ -366,7 +357,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
.intr_tear_rd_ptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
View file @ 3f5ba636
......@@ -129,7 +129,6 @@ static const struct dpu_pingpong_cfg sm6125_pp[] = {
.merge_3d = 0,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
......@@ -137,7 +136,6 @@ static const struct dpu_pingpong_cfg sm6125_pp[] = {
.merge_3d = 0,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
},
};
......@@ -151,7 +149,6 @@ static const struct dpu_intf_cfg sm6125_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
View file @ 3f5ba636
......@@ -219,7 +219,6 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
......@@ -227,7 +226,6 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
......@@ -235,7 +233,6 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = -1,
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
......@@ -243,7 +240,6 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = -1,
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x72000, .len = 0xd4,
......@@ -251,7 +247,6 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
.intr_rdptr = -1,
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x72800, .len = 0xd4,
......@@ -259,7 +254,6 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
.intr_rdptr = -1,
},
};
......@@ -306,7 +300,6 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
......@@ -336,7 +329,6 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
.intr_tear_rd_ptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
View file @ 3f5ba636
......@@ -120,7 +120,6 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
......@@ -128,7 +127,6 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
},
};
......@@ -142,7 +140,6 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
View file @ 3f5ba636
......@@ -83,7 +83,6 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
View file @ 3f5ba636
......@@ -128,7 +128,6 @@ static struct dpu_pingpong_cfg sm6350_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
......@@ -136,7 +135,6 @@ static struct dpu_pingpong_cfg sm6350_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
},
};
......@@ -158,7 +156,6 @@ static const struct dpu_intf_cfg sm6350_intf[] = {
.prog_fetch_lines_worst_case = 35,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
View file @ 3f5ba636
......@@ -82,7 +82,6 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
View file @ 3f5ba636
......@@ -85,7 +85,6 @@ static const struct dpu_pingpong_cfg sm6375_pp[] = {
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
View file @ 3f5ba636
......@@ -218,7 +218,6 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
......@@ -226,7 +225,6 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
......@@ -234,7 +232,6 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = -1,
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
......@@ -242,7 +239,6 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = -1,
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
......@@ -250,7 +246,6 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
.intr_rdptr = -1,
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
......@@ -258,7 +253,6 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
.intr_rdptr = -1,
},
};
......@@ -314,7 +308,6 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x2c4,
......@@ -344,7 +337,6 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
.intr_tear_rd_ptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
View file @ 3f5ba636
......@@ -131,7 +131,6 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
......@@ -139,7 +138,6 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
......@@ -147,7 +145,6 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = -1,
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
......@@ -155,7 +152,6 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = -1,
},
};
......@@ -194,7 +190,6 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x2c4,
......@@ -214,7 +209,6 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
.intr_tear_rd_ptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
View file @ 3f5ba636
......@@ -221,7 +221,6 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
......@@ -229,7 +228,6 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
......@@ -237,7 +235,6 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = -1,
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
......@@ -245,7 +242,6 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = -1,
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
......@@ -253,7 +249,6 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
.intr_rdptr = -1,
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
......@@ -261,7 +256,6 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
.intr_rdptr = -1,
},
};
......@@ -328,7 +322,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
......@@ -358,7 +351,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_4", .id = INTF_4,
.base = 0x38000, .len = 0x280,
......@@ -368,7 +360,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_5", .id = INTF_5,
.base = 0x39000, .len = 0x280,
......@@ -378,7 +369,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_6", .id = INTF_6,
.base = 0x3a000, .len = 0x280,
......@@ -388,7 +378,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_7", .id = INTF_7,
.base = 0x3b000, .len = 0x280,
......@@ -398,7 +387,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_8", .id = INTF_8,
.base = 0x3c000, .len = 0x280,
......@@ -408,7 +396,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
.intr_tear_rd_ptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
View file @ 3f5ba636
......@@ -221,7 +221,6 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
......@@ -229,7 +228,6 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
......@@ -237,7 +235,6 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = -1,
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
......@@ -245,7 +242,6 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = -1,
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
......@@ -253,7 +249,6 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
.intr_rdptr = -1,
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
......@@ -261,23 +256,18 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
.intr_rdptr = -1,
}, {
.name = "pingpong_6", .id = PINGPONG_6,
.base = 0x65800, .len = 0,
.features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
.intr_done = -1,
.intr_rdptr = -1,
}, {
.name = "pingpong_7", .id = PINGPONG_7,
.base = 0x65c00, .len = 0,
.features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
.intr_done = -1,
.intr_rdptr = -1,
},
};
......@@ -336,7 +326,6 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
......@@ -366,7 +355,6 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
.intr_tear_rd_ptr = -1,
},
};
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
View file @ 3f5ba636
......@@ -24,16 +24,6 @@ static const struct dpu_mdp_cfg sm8550_mdp = {
.base = 0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
[DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 },
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 },
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 },
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 },
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 },
[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 },
[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 },
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
},
};
......@@ -81,7 +71,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.sblk = &sm8550_vig_sblk_0,
.xin_id = 0,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0,
}, {
.name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x344,
......@@ -89,7 +78,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.sblk = &sm8550_vig_sblk_1,
.xin_id = 4,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1,
}, {
.name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x344,
......@@ -97,7 +85,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.sblk = &sm8550_vig_sblk_2,
.xin_id = 8,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2,
}, {
.name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x344,
......@@ -105,7 +92,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.sblk = &sm8550_vig_sblk_3,
.xin_id = 12,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3,
}, {
.name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x344,
......@@ -113,7 +99,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.sblk = &sdm845_dma_sblk_0,
.xin_id = 1,
.type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0,
}, {
.name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x344,
......@@ -121,7 +106,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.sblk = &sdm845_dma_sblk_1,
.xin_id = 5,
.type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1,
}, {
.name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x344,
......@@ -129,7 +113,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.sblk = &sdm845_dma_sblk_2,
.xin_id = 9,
.type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2,
}, {
.name = "sspp_11", .id = SSPP_DMA3,
.base = 0x2a000, .len = 0x344,
......@@ -137,7 +120,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.sblk = &sdm845_dma_sblk_3,
.xin_id = 13,
.type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA3,
}, {
.name = "sspp_12", .id = SSPP_DMA4,
.base = 0x2c000, .len = 0x344,
......@@ -145,7 +127,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.sblk = &sm8550_dma_sblk_4,
.xin_id = 14,
.type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA4,
}, {
.name = "sspp_13", .id = SSPP_DMA5,
.base = 0x2e000, .len = 0x344,
......@@ -153,7 +134,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.sblk = &sm8550_dma_sblk_5,
.xin_id = 15,
.type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA5,
},
};
......@@ -236,7 +216,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = -1,
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
......@@ -244,7 +223,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = -1,
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
......@@ -252,7 +230,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = -1,
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
......@@ -260,7 +237,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = -1,
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
......@@ -268,7 +244,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
.intr_rdptr = -1,
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
......@@ -276,23 +251,18 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = {
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
.intr_rdptr = -1,
}, {
.name = "pingpong_6", .id = PINGPONG_6,
.base = 0x66000, .len = 0,
.features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
.intr_done = -1,
.intr_rdptr = -1,
}, {
.name = "pingpong_7", .id = PINGPONG_7,
.base = 0x66400, .len = 0,
.features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
.intr_done = -1,
.intr_rdptr = -1,
},
};
......@@ -341,6 +311,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = {
},
};
static const struct dpu_wb_cfg sm8550_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
.features = WB_SM8250_MASK,
.format_list = wb2_formats,
.num_formats = ARRAY_SIZE(wb2_formats),
.xin_id = 6,
.vbif_idx = VBIF_RT,
.maxlinewidth = 4096,
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
},
};
static const struct dpu_intf_cfg sm8550_intf[] = {
{
.name = "intf_0", .id = INTF_0,
......@@ -351,7 +335,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
.intr_tear_rd_ptr = -1,
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
......@@ -381,7 +364,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
.prog_fetch_lines_worst_case = 24,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
.intr_tear_rd_ptr = -1,
},
};
......@@ -438,6 +420,8 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
.dsc = sm8550_dsc,
.merge_3d_count = ARRAY_SIZE(sm8550_merge_3d),
.merge_3d = sm8550_merge_3d,
.wb_count = ARRAY_SIZE(sm8550_wb),
.wb = sm8550_wb,
.intf_count = ARRAY_SIZE(sm8550_intf),
.intf = sm8550_intf,
.vbif_count = ARRAY_SIZE(sm8550_vbif),
......
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
View file @ 3f5ba636
......@@ -37,7 +37,7 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms);
*/
u32 dpu_core_irq_read(
struct dpu_kms *dpu_kms,
int irq_idx);
unsigned int irq_idx);
/**
* dpu_core_irq_register_callback - For registering callback function on IRQ
......@@ -52,8 +52,8 @@ u32 dpu_core_irq_read(
*/
int dpu_core_irq_register_callback(
struct dpu_kms *dpu_kms,
int irq_idx,
void (*irq_cb)(void *arg, int irq_idx),
unsigned int irq_idx,
void (*irq_cb)(void *arg),
void *irq_arg);
/**
......@@ -67,7 +67,7 @@ int dpu_core_irq_register_callback(
*/
int dpu_core_irq_unregister_callback(
struct dpu_kms *dpu_kms,
int irq_idx);
unsigned int irq_idx);
/**
* dpu_debugfs_core_irq_init - register core irq debugfs
......
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
View file @ 3f5ba636
......@@ -1466,7 +1466,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
struct msm_drm_private *priv = dev->dev_private;
struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
struct dpu_crtc *dpu_crtc;
int i, ret;
dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
......
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
View file @ 3f5ba636
......@@ -347,8 +347,8 @@ static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
u32 irq_idx, struct dpu_encoder_wait_info *info);
int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
int irq,
void (*func)(void *arg, int irq_idx),
unsigned int irq_idx,
void (*func)(void *arg),
struct dpu_encoder_wait_info *wait_info)
{
u32 irq_status;
......@@ -362,54 +362,54 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
/* return EWOULDBLOCK since we know the wait isn't necessary */
if (phys_enc->enable_state == DPU_ENC_DISABLED) {
DRM_ERROR("encoder is disabled id=%u, callback=%ps, irq=%d\n",
DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n",
DRMID(phys_enc->parent), func,
irq);
DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx));
return -EWOULDBLOCK;
}
if (irq < 0) {
if (irq_idx < 0) {
DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
DRMID(phys_enc->parent), func);
return 0;
}
DRM_DEBUG_KMS("id=%u, callback=%ps, irq=%d, pp=%d, pending_cnt=%d\n",
DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n",
DRMID(phys_enc->parent), func,
irq, phys_enc->hw_pp->idx - PINGPONG_0,
DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0,
atomic_read(wait_info->atomic_cnt));
ret = dpu_encoder_helper_wait_event_timeout(
DRMID(phys_enc->parent),
irq,
irq_idx,
wait_info);
if (ret <= 0) {
irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq);
irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx);
if (irq_status) {
unsigned long flags;
DRM_DEBUG_KMS("irq not triggered id=%u, callback=%ps, irq=%d, pp=%d, atomic_cnt=%d\n",
DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
DRMID(phys_enc->parent), func,
irq,
phys_enc->hw_pp->idx - PINGPONG_0,
atomic_read(wait_info->atomic_cnt));
local_irq_save(flags);
func(phys_enc, irq);
func(phys_enc);
local_irq_restore(flags);
ret = 0;
} else {
ret = -ETIMEDOUT;
DRM_DEBUG_KMS("irq timeout id=%u, callback=%ps, irq=%d, pp=%d, atomic_cnt=%d\n",
DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
DRMID(phys_enc->parent), func,
irq,
phys_enc->hw_pp->idx - PINGPONG_0,
atomic_read(wait_info->atomic_cnt));
}
} else {
ret = 0;
trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
func, irq,
func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
phys_enc->hw_pp->idx - PINGPONG_0,
atomic_read(wait_info->atomic_cnt));
}
......@@ -1194,11 +1194,21 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
struct dpu_encoder_virt *dpu_enc = NULL;
int ret = 0;
struct drm_display_mode *cur_mode = NULL;
struct msm_drm_private *priv = drm_enc->dev->dev_private;
struct msm_display_info *disp_info;
int index;
dpu_enc = to_dpu_encoder_virt(drm_enc);
disp_info = &dpu_enc->disp_info;
index = disp_info->h_tile_instance[0];
dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
if (disp_info->intf_type == INTF_DP)
dpu_enc->wide_bus_en = msm_dp_wide_bus_available(priv->dp[index]);
else if (disp_info->intf_type == INTF_DSI)
dpu_enc->wide_bus_en = msm_dsi_wide_bus_enabled(priv->dsi[index]);
mutex_lock(&dpu_enc->enc_lock);
cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
......@@ -1537,7 +1547,7 @@ void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
static int dpu_encoder_helper_wait_event_timeout(
int32_t drm_id,
u32 irq_idx,
unsigned int irq_idx,
struct dpu_encoder_wait_info *info)
{
int rc = 0;
......@@ -1550,7 +1560,9 @@ static int dpu_encoder_helper_wait_event_timeout(
atomic_read(info->atomic_cnt) == 0, jiffies);
time = ktime_to_ms(ktime_get());
trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
trace_dpu_enc_wait_event_timeout(drm_id,
DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
rc, time,
expected_time,
atomic_read(info->atomic_cnt));
/* If we timed out, counter is valid and time is less, wait again */
......@@ -2383,10 +2395,6 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
timer_setup(&dpu_enc->frame_done_timer,
dpu_encoder_frame_done_timeout, 0);
if (disp_info->intf_type == INTF_DP)
dpu_enc->wide_bus_en = msm_dp_wide_bus_available(
priv->dp[disp_info->h_tile_instance[0]]);
INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
dpu_encoder_off_work);
dpu_enc->idle_timeout = IDLE_TIMEOUT;
......@@ -2480,8 +2488,6 @@ unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc,
struct dpu_enc_phys_init_params *p)
{
int i;
phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
phys_enc->hw_intf = p->hw_intf;
phys_enc->hw_wb = p->hw_wb;
......@@ -2491,9 +2497,6 @@ void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc,
phys_enc->enc_spinlock = p->enc_spinlock;
phys_enc->enable_state = DPU_ENC_DISABLED;
for (i = 0; i < ARRAY_SIZE(phys_enc->irq); i++)
phys_enc->irq[i] = -EINVAL;
atomic_set(&phys_enc->vblank_refcount, 0);
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
......
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
View file @ 3f5ba636
......@@ -193,7 +193,7 @@ struct dpu_encoder_phys {
atomic_t pending_ctlstart_cnt;
atomic_t pending_kickoff_cnt;
wait_queue_head_t pending_kickoff_wq;
int irq[INTR_IDX_MAX];
unsigned int irq[INTR_IDX_MAX];
bool has_intf_te;
};
......@@ -364,8 +364,8 @@ void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
* @Return: 0 or -ERROR
*/
int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
int irq,
void (*func)(void *arg, int irq_idx),
unsigned int irq,
void (*func)(void *arg),
struct dpu_encoder_wait_info *wait_info);
/**
......
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
View file @ 3f5ba636
......@@ -72,11 +72,13 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
if (intf_cfg.dsc != 0)
cmd_mode_cfg.data_compress = true;
cmd_mode_cfg.wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
if (phys_enc->hw_intf->ops.program_intf_cmd_cfg)
phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, &cmd_mode_cfg);
}
static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg)
{
struct dpu_encoder_phys *phys_enc = arg;
unsigned long lock_flags;
......@@ -103,19 +105,11 @@ static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
DPU_ATRACE_END("pp_done_irq");
}
static void dpu_encoder_phys_cmd_te_rd_ptr_irq(void *arg, int irq_idx)
static void dpu_encoder_phys_cmd_te_rd_ptr_irq(void *arg)
{
struct dpu_encoder_phys *phys_enc = arg;
struct dpu_encoder_phys_cmd *cmd_enc;
if (phys_enc->has_intf_te) {
if (!phys_enc->hw_intf)
return;
} else {
if (!phys_enc->hw_pp)
return;
}
DPU_ATRACE_BEGIN("rd_ptr_irq");
cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
......@@ -126,7 +120,7 @@ static void dpu_encoder_phys_cmd_te_rd_ptr_irq(void *arg, int irq_idx)
DPU_ATRACE_END("rd_ptr_irq");
}
static void dpu_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx)
static void dpu_encoder_phys_cmd_ctl_start_irq(void *arg)
{
struct dpu_encoder_phys *phys_enc = arg;
......@@ -139,7 +133,7 @@ static void dpu_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx)
DPU_ATRACE_END("ctl_start_irq");
}
static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx)
static void dpu_encoder_phys_cmd_underrun_irq(void *arg)
{
struct dpu_encoder_phys *phys_enc = arg;
......@@ -333,24 +327,21 @@ static void dpu_encoder_phys_cmd_tearcheck_config(
unsigned long vsync_hz;
struct dpu_kms *dpu_kms;
if (phys_enc->has_intf_te) {
if (!phys_enc->hw_intf ||
!phys_enc->hw_intf->ops.enable_tearcheck) {
DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
return;
}
DPU_DEBUG_CMDENC(cmd_enc, "");
} else {
if (!phys_enc->hw_pp ||
!phys_enc->hw_pp->ops.enable_tearcheck) {
DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
return;
}
DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
/*
* TODO: if/when resource allocation is refactored, move this to a
* place where the driver can actually return an error.
*/
if (!phys_enc->has_intf_te &&
(!phys_enc->hw_pp ||
!phys_enc->hw_pp->ops.enable_tearcheck)) {
DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
return;
}
DPU_DEBUG_CMDENC(cmd_enc, "intf %d pp %d\n",
phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1,
phys_enc->hw_pp ? phys_enc->hw_pp->idx - PINGPONG_0 : -1);
mode = &phys_enc->cached_mode;
dpu_kms = phys_enc->dpu_kms;
......@@ -776,8 +767,19 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
phys_enc->intf_mode = INTF_MODE_CMD;
cmd_enc->stream_sel = 0;
phys_enc->has_intf_te = test_bit(DPU_INTF_TE,
&phys_enc->hw_intf->cap->features);
if (!phys_enc->hw_intf) {
DPU_ERROR_CMDENC(cmd_enc, "no INTF provided\n");
return ERR_PTR(-EINVAL);
}
/* DPU before 5.0 use PINGPONG for TE handling */
if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5)
phys_enc->has_intf_te = true;
if (phys_enc->has_intf_te && !phys_enc->hw_intf->ops.enable_tearcheck) {
DPU_ERROR_CMDENC(cmd_enc, "tearcheck not supported\n");
return ERR_PTR(-EINVAL);
}
atomic_set(&cmd_enc->pending_vblank_cnt, 0);
init_waitqueue_head(&cmd_enc->pending_vblank_wq);
......
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
View file @ 3f5ba636
......@@ -297,7 +297,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
programmable_fetch_config(phys_enc, &timing_params);
}
static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
static void dpu_encoder_phys_vid_vblank_irq(void *arg)
{
struct dpu_encoder_phys *phys_enc = arg;
struct dpu_hw_ctl *hw_ctl;
......@@ -334,7 +334,7 @@ static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
DPU_ATRACE_END("vblank_irq");
}
static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
static void dpu_encoder_phys_vid_underrun_irq(void *arg)
{
struct dpu_encoder_phys *phys_enc = arg;
......
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
View file @ 3f5ba636
......@@ -34,6 +34,23 @@ static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
return true;
}
static bool _dpu_encoder_phys_wb_clk_force_ctrl(struct dpu_hw_wb *wb,
struct dpu_hw_mdp *mdp,
bool enable, bool *forced_on)
{
if (wb->ops.setup_clk_force_ctrl) {
*forced_on = wb->ops.setup_clk_force_ctrl(wb, enable);
return true;
}
if (mdp->ops.setup_clk_force_ctrl) {
*forced_on = mdp->ops.setup_clk_force_ctrl(mdp, wb->caps->clk_ctrl, enable);
return true;
}
return false;
}
/**
* dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
* @phys_enc: Pointer to physical encoder
......@@ -43,6 +60,7 @@ static void dpu_encoder_phys_wb_set_ot_limit(
{
struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
struct dpu_vbif_set_ot_params ot_params;
bool forced_on = false;
memset(&ot_params, 0, sizeof(ot_params));
ot_params.xin_id = hw_wb->caps->xin_id;
......@@ -52,10 +70,17 @@ static void dpu_encoder_phys_wb_set_ot_limit(
ot_params.is_wfd = true;
ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
ot_params.vbif_idx = hw_wb->caps->vbif_idx;
ot_params.clk_ctrl = hw_wb->caps->clk_ctrl;
ot_params.rd = false;
if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
true, &forced_on))
return;
dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);
if (forced_on)
_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
false, &forced_on);
}
/**
......@@ -67,6 +92,7 @@ static void dpu_encoder_phys_wb_set_qos_remap(
{
struct dpu_hw_wb *hw_wb;
struct dpu_vbif_set_qos_params qos_params;
bool forced_on = false;
if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
DPU_ERROR("invalid arguments\n");
......@@ -83,7 +109,6 @@ static void dpu_encoder_phys_wb_set_qos_remap(
memset(&qos_params, 0, sizeof(qos_params));
qos_params.vbif_idx = hw_wb->caps->vbif_idx;
qos_params.xin_id = hw_wb->caps->xin_id;
qos_params.clk_ctrl = hw_wb->caps->clk_ctrl;
qos_params.num = hw_wb->idx - WB_0;
qos_params.is_rt = false;
......@@ -92,7 +117,15 @@ static void dpu_encoder_phys_wb_set_qos_remap(
qos_params.vbif_idx,
qos_params.xin_id, qos_params.is_rt);
if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
true, &forced_on))
return;
dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params);
if (forced_on)
_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
false, &forced_on);
}
/**
......@@ -345,7 +378,11 @@ static void dpu_encoder_phys_wb_setup(
}
static void _dpu_encoder_phys_wb_frame_done_helper(void *arg)
/**
* dpu_encoder_phys_wb_done_irq - writeback interrupt handler
* @arg: Pointer to writeback encoder
*/
static void dpu_encoder_phys_wb_done_irq(void *arg)
{
struct dpu_encoder_phys *phys_enc = arg;
struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
......@@ -371,16 +408,6 @@ static void _dpu_encoder_phys_wb_frame_done_helper(void *arg)
wake_up_all(&phys_enc->pending_kickoff_wq);
}
/**
* dpu_encoder_phys_wb_done_irq - writeback interrupt handler
* @arg: Pointer to writeback encoder
* @irq_idx: interrupt index
*/
static void dpu_encoder_phys_wb_done_irq(void *arg, int irq_idx)
{
_dpu_encoder_phys_wb_frame_done_helper(arg);
}
/**
* dpu_encoder_phys_wb_irq_ctrl - irq control of WB
* @phys: Pointer to physical encoder
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View file @ 3f5ba636
......@@ -79,7 +79,7 @@
(BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
#define PINGPONG_SDM845_MASK \
(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE) | BIT(DPU_PINGPONG_DSC))
(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
#define PINGPONG_SDM845_TE2_MASK \
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
......@@ -100,7 +100,6 @@
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
BIT(DPU_INTF_TE) | \
BIT(DPU_INTF_STATUS_SUPPORTED) | \
BIT(DPU_DATA_HCTL_EN))
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View file @ 3f5ba636
......@@ -119,7 +119,6 @@ enum {
/**
* PINGPONG sub-blocks
* @DPU_PINGPONG_TE Tear check block
* @DPU_PINGPONG_TE2 Additional tear check block for split pipes
* @DPU_PINGPONG_SPLIT PP block supports split fifo
* @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
......@@ -128,8 +127,7 @@ enum {
* @DPU_PINGPONG_MAX
*/
enum {
DPU_PINGPONG_TE = 0x1,
DPU_PINGPONG_TE2,
DPU_PINGPONG_TE2 = 0x1,
DPU_PINGPONG_SPLIT,
DPU_PINGPONG_SLAVE,
DPU_PINGPONG_DITHER,
......@@ -160,7 +158,6 @@ enum {
* INTF sub-blocks
* @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
* pixel data arrives to this INTF
* @DPU_INTF_TE INTF block has TE configuration support
* @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
* than video timing
* @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
......@@ -168,7 +165,6 @@ enum {
*/
enum {
DPU_INTF_INPUT_CTRL = 0x1,
DPU_INTF_TE,
DPU_DATA_HCTL_EN,
DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_MAX
......@@ -494,7 +490,7 @@ struct dpu_mdp_cfg {
*/
struct dpu_ctl_cfg {
DPU_HW_BLK_INFO;
s32 intr_start;
unsigned int intr_start;
};
/**
......@@ -557,8 +553,8 @@ struct dpu_dspp_cfg {
struct dpu_pingpong_cfg {
DPU_HW_BLK_INFO;
u32 merge_3d;
s32 intr_done;
s32 intr_rdptr;
unsigned int intr_done;
unsigned int intr_rdptr;
const struct dpu_pingpong_sub_blks *sblk;
};
......@@ -605,9 +601,9 @@ struct dpu_intf_cfg {
u32 type; /* interface type*/
u32 controller_id;
u32 prog_fetch_lines_worst_case;
s32 intr_underrun;
s32 intr_vsync;
s32 intr_tear_rd_ptr;
unsigned int intr_underrun;
unsigned int intr_vsync;
unsigned int intr_tear_rd_ptr;
};
/**
......@@ -626,7 +622,7 @@ struct dpu_wb_cfg {
u8 vbif_idx;
u32 maxlinewidth;
u32 xin_id;
s32 intr_wb_done;
unsigned int intr_wb_done;
const u32 *format_list;
u32 num_formats;
enum dpu_clk_ctrl_type clk_ctrl;
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
View file @ 3f5ba636
......@@ -36,7 +36,17 @@ enum dpu_hw_intr_reg {
#define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0))
#define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
#define DPU_IRQ_IDX(reg_idx, offset) (1 + reg_idx * 32 + offset)
#define DPU_IRQ_REG(irq_idx) ((irq_idx - 1) / 32)
#define DPU_IRQ_BIT(irq_idx) ((irq_idx - 1) % 32)
#define DPU_NUM_IRQS (MDP_INTR_MAX * 32)
struct dpu_hw_intr_entry {
void (*cb)(void *arg);
void *arg;
atomic_t count;
};
/**
* struct dpu_hw_intr: hw interrupts handling data structure
......@@ -44,7 +54,6 @@ enum dpu_hw_intr_reg {
* @ops: function pointer mapping for IRQ handling
* @cache_irq_mask: array of IRQ enable masks reg storage created during init
* @save_irq_status: array of IRQ status reg storage created during init
* @total_irqs: total number of irq_idx mapped in the hw_interrupts
* @irq_lock: spinlock for accessing IRQ resources
* @irq_cb_tbl: array of IRQ callbacks
*/
......@@ -52,16 +61,11 @@ struct dpu_hw_intr {
struct dpu_hw_blk_reg_map hw;
u32 cache_irq_mask[MDP_INTR_MAX];
u32 *save_irq_status;
u32 total_irqs;
spinlock_t irq_lock;
unsigned long irq_mask;
const struct dpu_intr_reg *intr_set;
struct {
void (*cb)(void *arg, int irq_idx);
void *arg;
atomic_t count;
} irq_tbl[] __counted_by(total_irqs);
struct dpu_hw_intr_entry irq_tbl[DPU_NUM_IRQS];
};
/**
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
View file @ 3f5ba636
......@@ -521,32 +521,10 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
if (cmd_mode_cfg->data_compress)
intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
}
static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
unsigned long cap, const struct dpu_mdss_version *mdss_rev)
{
ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine;
ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch;
ops->get_status = dpu_hw_intf_get_status;
ops->enable_timing = dpu_hw_intf_enable_timing_engine;
ops->get_line_count = dpu_hw_intf_get_line_count;
if (cap & BIT(DPU_INTF_INPUT_CTRL))
ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
ops->setup_misr = dpu_hw_intf_setup_misr;
ops->collect_misr = dpu_hw_intf_collect_misr;
if (cap & BIT(DPU_INTF_TE)) {
ops->enable_tearcheck = dpu_hw_intf_enable_te;
ops->disable_tearcheck = dpu_hw_intf_disable_te;
ops->connect_external_te = dpu_hw_intf_connect_external_te;
ops->vsync_sel = dpu_hw_intf_vsync_sel;
ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh;
}
if (cmd_mode_cfg->wide_bus_en)
intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
if (mdss_rev->core_major_ver >= 7)
ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg;
DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
}
struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
......@@ -571,7 +549,35 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
*/
c->idx = cfg->id;
c->cap = cfg;
_setup_intf_ops(&c->ops, c->cap->features, mdss_rev);
c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine;
c->ops.setup_prg_fetch = dpu_hw_intf_setup_prg_fetch;
c->ops.get_status = dpu_hw_intf_get_status;
c->ops.enable_timing = dpu_hw_intf_enable_timing_engine;
c->ops.get_line_count = dpu_hw_intf_get_line_count;
c->ops.setup_misr = dpu_hw_intf_setup_misr;
c->ops.collect_misr = dpu_hw_intf_collect_misr;
if (cfg->features & BIT(DPU_INTF_INPUT_CTRL))
c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
/* INTF TE is only for DSI interfaces */
if (mdss_rev->core_major_ver >= 5 && cfg->type == INTF_DSI) {
WARN_ON(!cfg->intr_tear_rd_ptr);
c->ops.enable_tearcheck = dpu_hw_intf_enable_te;
c->ops.disable_tearcheck = dpu_hw_intf_disable_te;
c->ops.connect_external_te = dpu_hw_intf_connect_external_te;
c->ops.vsync_sel = dpu_hw_intf_vsync_sel;
c->ops.disable_autorefresh = dpu_hw_intf_disable_autorefresh;
}
/* Technically, INTF_CONFIG2 is present for DPU 5.0+, but
* we can configure it for DPU 7.0+ since the wide bus and DSC flags
* would not be set for DPU < 7.0 anyways
*/
if (mdss_rev->core_major_ver >= 7)
c->ops.program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg;
return c;
}
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
View file @ 3f5ba636
......@@ -50,6 +50,7 @@ struct dpu_hw_intf_status {
struct dpu_hw_intf_cmd_mode_cfg {
u8 data_compress; /* enable data compress between dpu and dsi */
u8 wide_bus_en; /* enable databus widen mode */
};
/**
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
View file @ 3f5ba636
......@@ -281,10 +281,24 @@ static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp)
return 0;
}
static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
unsigned long features)
struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg,
void __iomem *addr, const struct dpu_mdss_version *mdss_rev)
{
if (test_bit(DPU_PINGPONG_TE, &features)) {
struct dpu_hw_pingpong *c;
c = kzalloc(sizeof(*c), GFP_KERNEL);
if (!c)
return ERR_PTR(-ENOMEM);
c->hw.blk_addr = addr + cfg->base;
c->hw.log_mask = DPU_DBG_MASK_PINGPONG;
c->idx = cfg->id;
c->caps = cfg;
if (mdss_rev->core_major_ver < 5) {
WARN_ON(!cfg->intr_rdptr);
c->ops.enable_tearcheck = dpu_hw_pp_enable_te;
c->ops.disable_tearcheck = dpu_hw_pp_disable_te;
c->ops.connect_external_te = dpu_hw_pp_connect_external_te;
......@@ -292,31 +306,14 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh;
}
if (test_bit(DPU_PINGPONG_DSC, &features)) {
if (test_bit(DPU_PINGPONG_DSC, &cfg->features)) {
c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
}
if (test_bit(DPU_PINGPONG_DITHER, &features))
if (test_bit(DPU_PINGPONG_DITHER, &cfg->features))
c->ops.setup_dither = dpu_hw_pp_setup_dither;
};
struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg,
void __iomem *addr)
{
struct dpu_hw_pingpong *c;
c = kzalloc(sizeof(*c), GFP_KERNEL);
if (!c)
return ERR_PTR(-ENOMEM);
c->hw.blk_addr = addr + cfg->base;
c->hw.log_mask = DPU_DBG_MASK_PINGPONG;
c->idx = cfg->id;
c->caps = cfg;
_setup_pingpong_ops(c, c->caps->features);
return c;
}
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
View file @ 3f5ba636
......@@ -123,10 +123,11 @@ static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw)
* pingpong catalog entry.
* @cfg: Pingpong catalog entry for which driver object is required
* @addr: Mapped register io address of MDP
* @mdss_rev: dpu core's major and minor versions
* Return: Error code or allocated dpu_hw_pingpong context
*/
struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg,
void __iomem *addr);
void __iomem *addr, const struct dpu_mdss_version *mdss_rev);
/**
* dpu_hw_pingpong_destroy - destroys pingpong driver context
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
View file @ 3f5ba636
......@@ -69,6 +69,7 @@
#define SSPP_EXCL_REC_XY_REC1 0x188
#define SSPP_EXCL_REC_SIZE 0x1B4
#define SSPP_EXCL_REC_XY 0x1B8
#define SSPP_CLK_CTRL 0x330
/* SSPP_SRC_OP_MODE & OP_MODE_REC1 */
#define MDSS_MDP_OP_DEINTERLACE BIT(22)
......@@ -581,8 +582,18 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
dpu_setup_cdp(&ctx->hw, cdp_cntl_offset, fmt, enable);
}
static bool dpu_hw_sspp_setup_clk_force_ctrl(struct dpu_hw_sspp *ctx, bool enable)
{
static const struct dpu_clk_ctrl_reg sspp_clk_ctrl = {
.reg_off = SSPP_CLK_CTRL,
.bit_off = 0
};
return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable);
}
static void _setup_layer_ops(struct dpu_hw_sspp *c,
unsigned long features)
unsigned long features, const struct dpu_mdss_version *mdss_rev)
{
c->ops.setup_format = dpu_hw_sspp_setup_format;
c->ops.setup_rects = dpu_hw_sspp_setup_rects;
......@@ -612,6 +623,9 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c,
if (test_bit(DPU_SSPP_CDP, &features))
c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
if (mdss_rev->core_major_ver >= 9)
c->ops.setup_clk_force_ctrl = dpu_hw_sspp_setup_clk_force_ctrl;
}
#ifdef CONFIG_DEBUG_FS
......@@ -672,7 +686,8 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
#endif
struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,
void __iomem *addr, const struct msm_mdss_data *mdss_data)
void __iomem *addr, const struct msm_mdss_data *mdss_data,
const struct dpu_mdss_version *mdss_rev)
{
struct dpu_hw_sspp *hw_pipe;
......@@ -690,7 +705,7 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,
hw_pipe->ubwc = mdss_data;
hw_pipe->idx = cfg->id;
hw_pipe->cap = cfg;
_setup_layer_ops(hw_pipe, hw_pipe->cap->features);
_setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
return hw_pipe;
}
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
View file @ 3f5ba636
......@@ -271,6 +271,14 @@ struct dpu_hw_sspp_ops {
void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
bool danger_safe_en);
/**
* setup_clk_force_ctrl - setup clock force control
* @ctx: Pointer to pipe context
* @enable: enable clock force if true
*/
bool (*setup_clk_force_ctrl)(struct dpu_hw_sspp *ctx,
bool enable);
/**
* setup_histogram - setup histograms
* @ctx: Pointer to pipe context
......@@ -334,9 +342,11 @@ struct dpu_kms;
* @cfg: Pipe catalog entry for which driver object is required
* @addr: Mapped register io address of MDP
* @mdss_data: UBWC / MDSS configuration data
* @mdss_rev: dpu core's major and minor versions
*/
struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,
void __iomem *addr, const struct msm_mdss_data *mdss_data);
void __iomem *addr, const struct msm_mdss_data *mdss_data,
const struct dpu_mdss_version *mdss_rev);
/**
* dpu_hw_sspp_destroy(): Destroys SSPP driver context
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
View file @ 3f5ba636
......@@ -66,34 +66,13 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp,
enum dpu_clk_ctrl_type clk_ctrl, bool enable)
{
struct dpu_hw_blk_reg_map *c;
u32 reg_off, bit_off;
u32 reg_val, new_val;
bool clk_forced_on;
if (!mdp)
return false;
c = &mdp->hw;
if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX)
return false;
reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off;
bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off;
reg_val = DPU_REG_READ(c, reg_off);
if (enable)
new_val = reg_val | BIT(bit_off);
else
new_val = reg_val & ~BIT(bit_off);
DPU_REG_WRITE(c, reg_off, new_val);
clk_forced_on = !(reg_val & BIT(bit_off));
return clk_forced_on;
return dpu_hw_clk_force_ctrl(&mdp->hw, &mdp->caps->clk_ctrls[clk_ctrl], enable);
}
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
View file @ 3f5ba636
......@@ -546,3 +546,24 @@ void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
DPU_REG_WRITE(c, offset, cdp_cntl);
}
bool dpu_hw_clk_force_ctrl(struct dpu_hw_blk_reg_map *c,
const struct dpu_clk_ctrl_reg *clk_ctrl_reg,
bool enable)
{
u32 reg_val, new_val;
bool clk_forced_on;
reg_val = DPU_REG_READ(c, clk_ctrl_reg->reg_off);
if (enable)
new_val = reg_val | BIT(clk_ctrl_reg->bit_off);
else
new_val = reg_val & ~BIT(clk_ctrl_reg->bit_off);
DPU_REG_WRITE(c, clk_ctrl_reg->reg_off, new_val);
clk_forced_on = !(reg_val & BIT(clk_ctrl_reg->bit_off));
return clk_forced_on;
}
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
View file @ 3f5ba636
......@@ -367,4 +367,8 @@ int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
u32 misr_signature_offset,
u32 *misr_value);
bool dpu_hw_clk_force_ctrl(struct dpu_hw_blk_reg_map *c,
const struct dpu_clk_ctrl_reg *clk_ctrl_reg,
bool enable);
#endif /* _DPU_HW_UTIL_H */
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
View file @ 3f5ba636
......@@ -43,6 +43,7 @@
#define WB_MUX 0x150
#define WB_CROP_CTRL 0x154
#define WB_CROP_OFFSET 0x158
#define WB_CLK_CTRL 0x178
#define WB_CSC_BASE 0x260
#define WB_DST_ADDR_SW_STATUS 0x2B0
#define WB_CDP_CNTL 0x2B4
......@@ -175,8 +176,18 @@ static void dpu_hw_wb_bind_pingpong_blk(
DPU_REG_WRITE(c, WB_MUX, mux_cfg);
}
static bool dpu_hw_wb_setup_clk_force_ctrl(struct dpu_hw_wb *ctx, bool enable)
{
static const struct dpu_clk_ctrl_reg wb_clk_ctrl = {
.reg_off = WB_CLK_CTRL,
.bit_off = 0
};
return dpu_hw_clk_force_ctrl(&ctx->hw, &wb_clk_ctrl, enable);
}
static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
unsigned long features)
unsigned long features, const struct dpu_mdss_version *mdss_rev)
{
ops->setup_outaddress = dpu_hw_wb_setup_outaddress;
ops->setup_outformat = dpu_hw_wb_setup_format;
......@@ -192,10 +203,13 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
if (test_bit(DPU_WB_INPUT_CTRL, &features))
ops->bind_pingpong_blk = dpu_hw_wb_bind_pingpong_blk;
if (mdss_rev->core_major_ver >= 9)
ops->setup_clk_force_ctrl = dpu_hw_wb_setup_clk_force_ctrl;
}
struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg,
void __iomem *addr)
void __iomem *addr, const struct dpu_mdss_version *mdss_rev)
{
struct dpu_hw_wb *c;
......@@ -212,7 +226,7 @@ struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg,
/* Assign ops */
c->idx = cfg->id;
c->caps = cfg;
_setup_wb_ops(&c->ops, c->caps->features);
_setup_wb_ops(&c->ops, c->caps->features, mdss_rev);
return c;
}
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
View file @ 3f5ba636
......@@ -29,6 +29,7 @@ struct dpu_hw_wb_cfg {
* @setup_outformat: setup output format of writeback block from writeback job
* @setup_qos_lut: setup qos LUT for writeback block based on input
* @setup_cdp: setup chroma down prefetch block for writeback block
* @setup_clk_force_ctrl: setup clock force control
* @bind_pingpong_blk: enable/disable the connection with ping-pong block
*/
struct dpu_hw_wb_ops {
......@@ -48,6 +49,9 @@ struct dpu_hw_wb_ops {
const struct dpu_format *fmt,
bool enable);
bool (*setup_clk_force_ctrl)(struct dpu_hw_wb *ctx,
bool enable);
void (*bind_pingpong_blk)(struct dpu_hw_wb *ctx,
const enum dpu_pingpong pp);
};
......@@ -74,10 +78,11 @@ struct dpu_hw_wb {
* dpu_hw_wb_init() - Initializes the writeback hw driver object.
* @cfg: wb_path catalog entry for which driver object is required
* @addr: mapped register io address of MDP
* @mdss_rev: dpu core's major and minor versions
* Return: Error code or allocated dpu_hw_wb context
*/
struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg,
void __iomem *addr);
void __iomem *addr, const struct dpu_mdss_version *mdss_rev);
/**
* dpu_hw_wb_destroy(): Destroy writeback hw driver object.
......
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
View file @ 3f5ba636
......@@ -389,8 +389,7 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
{
struct icc_path *path0;
struct icc_path *path1;
struct drm_device *dev = dpu_kms->dev;
struct device *dpu_dev = dev->dev;
struct device *dpu_dev = &dpu_kms->pdev->dev;
path0 = msm_icc_get(dpu_dev, "mdp0-mem");
path1 = msm_icc_get(dpu_dev, "mdp1-mem");
......@@ -829,21 +828,9 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
dpu_kms->catalog = NULL;
if (dpu_kms->vbif[VBIF_NRT])
devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]);
dpu_kms->vbif[VBIF_NRT] = NULL;
if (dpu_kms->vbif[VBIF_RT])
devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
dpu_kms->vbif[VBIF_RT] = NULL;
if (dpu_kms->hw_mdp)
dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
dpu_kms->hw_mdp = NULL;
if (dpu_kms->mmio)
devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio);
dpu_kms->mmio = NULL;
}
static void dpu_kms_destroy(struct msm_kms *kms)
......@@ -1079,30 +1066,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
atomic_set(&dpu_kms->bandwidth_ref, 0);
dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp");
if (IS_ERR(dpu_kms->mmio)) {
rc = PTR_ERR(dpu_kms->mmio);
DPU_ERROR("mdp register memory map failed: %d\n", rc);
dpu_kms->mmio = NULL;
goto error;
}
DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif");
if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
DPU_ERROR("vbif register memory map failed: %d\n", rc);
dpu_kms->vbif[VBIF_RT] = NULL;
goto error;
}
dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(dpu_kms->pdev, "vbif_nrt");
if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
dpu_kms->vbif[VBIF_NRT] = NULL;
DPU_DEBUG("VBIF NRT is not defined");
}
dpu_kms_parse_data_bus_icc_path(dpu_kms);
rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev);
if (rc < 0)
goto error;
......@@ -1241,33 +1204,11 @@ static int dpu_kms_init(struct drm_device *ddev)
struct msm_drm_private *priv = ddev->dev_private;
struct device *dev = ddev->dev;
struct platform_device *pdev = to_platform_device(dev);
struct dpu_kms *dpu_kms;
int irq;
struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
struct dev_pm_opp *opp;
int ret = 0;
unsigned long max_freq = ULONG_MAX;
dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL);
if (!dpu_kms)
return -ENOMEM;
ret = devm_pm_opp_set_clkname(dev, "core");
if (ret)
return ret;
/* OPP table is optional */
ret = devm_pm_opp_of_add_table(dev);
if (ret && ret != -ENODEV) {
dev_err(dev, "invalid OPP table in device tree\n");
return ret;
}
ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks);
if (ret < 0) {
DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
return ret;
}
dpu_kms->num_clocks = ret;
opp = dev_pm_opp_find_freq_floor(dev, &max_freq);
if (!IS_ERR(opp))
dev_pm_opp_put(opp);
......@@ -1280,26 +1221,74 @@ static int dpu_kms_init(struct drm_device *ddev)
return ret;
}
dpu_kms->dev = ddev;
dpu_kms->pdev = pdev;
pm_runtime_enable(&pdev->dev);
dpu_kms->rpm_enabled = true;
priv->kms = &dpu_kms->base;
irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0);
if (!irq) {
DPU_ERROR("failed to get irq\n");
return -EINVAL;
}
dpu_kms->base.irq = irq;
return 0;
}
static int dpu_dev_probe(struct platform_device *pdev)
{
return msm_drv_probe(&pdev->dev, dpu_kms_init);
struct device *dev = &pdev->dev;
struct dpu_kms *dpu_kms;
int irq;
int ret = 0;
dpu_kms = devm_kzalloc(dev, sizeof(*dpu_kms), GFP_KERNEL);
if (!dpu_kms)
return -ENOMEM;
dpu_kms->pdev = pdev;
ret = devm_pm_opp_set_clkname(dev, "core");
if (ret)
return ret;
/* OPP table is optional */
ret = devm_pm_opp_of_add_table(dev);
if (ret && ret != -ENODEV)
return dev_err_probe(dev, ret, "invalid OPP table in device tree\n");
ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks);
if (ret < 0)
return dev_err_probe(dev, ret, "failed to parse clocks\n");
dpu_kms->num_clocks = ret;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return dev_err_probe(dev, irq, "failed to get irq\n");
dpu_kms->base.irq = irq;
dpu_kms->mmio = msm_ioremap(pdev, "mdp");
if (IS_ERR(dpu_kms->mmio)) {
ret = PTR_ERR(dpu_kms->mmio);
DPU_ERROR("mdp register memory map failed: %d\n", ret);
dpu_kms->mmio = NULL;
return ret;
}
DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif");
if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
DPU_ERROR("vbif register memory map failed: %d\n", ret);
dpu_kms->vbif[VBIF_RT] = NULL;
return ret;
}
dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt");
if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
dpu_kms->vbif[VBIF_NRT] = NULL;
DPU_DEBUG("VBIF NRT is not defined");
}
ret = dpu_kms_parse_data_bus_icc_path(dpu_kms);
if (ret)
return ret;
return msm_drv_probe(&pdev->dev, dpu_kms_init, &dpu_kms->base);
}
static void dpu_dev_remove(struct platform_device *pdev)
......@@ -1353,8 +1342,8 @@ static const struct dev_pm_ops dpu_pm_ops = {
SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
.prepare = msm_pm_prepare,
.complete = msm_pm_complete,
.prepare = msm_kms_pm_prepare,
.complete = msm_kms_pm_complete,
};
static const struct of_device_id dpu_dt_match[] = {
......@@ -1381,7 +1370,7 @@ MODULE_DEVICE_TABLE(of, dpu_dt_match);
static struct platform_driver dpu_driver = {
.probe = dpu_dev_probe,
.remove_new = dpu_dev_remove,
.shutdown = msm_drv_shutdown,
.shutdown = msm_kms_shutdown,
.driver = {
.name = "msm_dpu",
.of_match_table = dpu_dt_match,
......
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
View file @ 3f5ba636
......@@ -333,6 +333,23 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
enable);
}
static bool _dpu_plane_sspp_clk_force_ctrl(struct dpu_hw_sspp *sspp,
struct dpu_hw_mdp *mdp,
bool enable, bool *forced_on)
{
if (sspp->ops.setup_clk_force_ctrl) {
*forced_on = sspp->ops.setup_clk_force_ctrl(sspp, enable);
return true;
}
if (mdp->ops.setup_clk_force_ctrl) {
*forced_on = mdp->ops.setup_clk_force_ctrl(mdp, sspp->cap->clk_ctrl, enable);
return true;
}
return false;
}
/**
* _dpu_plane_set_ot_limit - set OT limit for the given plane
* @plane: Pointer to drm plane
......@@ -348,6 +365,7 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_vbif_set_ot_params ot_params;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
bool forced_on = false;
memset(&ot_params, 0, sizeof(ot_params));
ot_params.xin_id = pipe->sspp->cap->xin_id;
......@@ -357,10 +375,17 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
ot_params.is_wfd = !pdpu->is_rt_pipe;
ot_params.frame_rate = frame_rate;
ot_params.vbif_idx = VBIF_RT;
ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl;
ot_params.rd = true;
if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
true, &forced_on))
return;
dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
if (forced_on)
_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
false, &forced_on);
}
/**
......@@ -374,21 +399,28 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_vbif_set_qos_params qos_params;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
bool forced_on = false;
memset(&qos_params, 0, sizeof(qos_params));
qos_params.vbif_idx = VBIF_RT;
qos_params.clk_ctrl = pipe->sspp->cap->clk_ctrl;
qos_params.xin_id = pipe->sspp->cap->xin_id;
qos_params.num = pipe->sspp->idx - SSPP_VIG0;
qos_params.is_rt = pdpu->is_rt_pipe;
DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d\n",
qos_params.num,
qos_params.vbif_idx,
qos_params.xin_id, qos_params.is_rt,
qos_params.clk_ctrl);
qos_params.xin_id, qos_params.is_rt);
if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
true, &forced_on))
return;
dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
if (forced_on)
_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
false, &forced_on);
}
static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
......
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
View file @ 3f5ba636
......@@ -146,7 +146,7 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_pingpong *hw;
const struct dpu_pingpong_cfg *pp = &cat->pingpong[i];
hw = dpu_hw_pingpong_init(pp, mmio);
hw = dpu_hw_pingpong_init(pp, mmio, cat->mdss_ver);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
DPU_ERROR("failed pingpong object creation: err %d\n",
......@@ -175,7 +175,7 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_wb *hw;
const struct dpu_wb_cfg *wb = &cat->wb[i];
hw = dpu_hw_wb_init(wb, mmio);
hw = dpu_hw_wb_init(wb, mmio, cat->mdss_ver);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
DPU_ERROR("failed wb object creation: err %d\n", rc);
......@@ -231,7 +231,7 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_sspp *hw;
const struct dpu_sspp_cfg *sspp = &cat->sspp[i];
hw = dpu_hw_sspp_init(sspp, mmio, mdss_data);
hw = dpu_hw_sspp_init(sspp, mmio, mdss_data, cat->mdss_ver);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
DPU_ERROR("failed sspp object creation: err %d\n", rc);
......
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
View file @ 3f5ba636
......@@ -168,46 +168,50 @@ TRACE_EVENT(dpu_perf_crtc_update,
);
DECLARE_EVENT_CLASS(dpu_irq_template,
TP_PROTO(int irq_idx),
TP_ARGS(irq_idx),
TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
TP_ARGS(irq_reg, irq_bit),
TP_STRUCT__entry(
__field( int, irq_idx )
__field( unsigned int, irq_reg )
__field( unsigned int, irq_bit )
),
TP_fast_assign(
__entry->irq_idx = irq_idx;
__entry->irq_reg = irq_reg;
__entry->irq_bit = irq_bit;
),
TP_printk("irq=%d", __entry->irq_idx)
TP_printk("IRQ=[%d, %d]", __entry->irq_reg, __entry->irq_bit)
);
DEFINE_EVENT(dpu_irq_template, dpu_irq_register_success,
TP_PROTO(int irq_idx),
TP_ARGS(irq_idx)
TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
TP_ARGS(irq_reg, irq_bit)
);
DEFINE_EVENT(dpu_irq_template, dpu_irq_unregister_success,
TP_PROTO(int irq_idx),
TP_ARGS(irq_idx)
TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
TP_ARGS(irq_reg, irq_bit)
);
TRACE_EVENT(dpu_enc_irq_wait_success,
TP_PROTO(uint32_t drm_id, void *func,
int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
TP_ARGS(drm_id, func, irq_idx, pp_idx, atomic_cnt),
unsigned int irq_reg, unsigned int irq_bit, enum dpu_pingpong pp_idx, int atomic_cnt),
TP_ARGS(drm_id, func, irq_reg, irq_bit, pp_idx, atomic_cnt),
TP_STRUCT__entry(
__field( uint32_t, drm_id )
__field( void *, func )
__field( int, irq_idx )
__field( unsigned int, irq_reg )
__field( unsigned int, irq_bit )
__field( enum dpu_pingpong, pp_idx )
__field( int, atomic_cnt )
),
TP_fast_assign(
__entry->drm_id = drm_id;
__entry->func = func;
__entry->irq_idx = irq_idx;
__entry->irq_reg = irq_reg;
__entry->irq_bit = irq_bit;
__entry->pp_idx = pp_idx;
__entry->atomic_cnt = atomic_cnt;
),
TP_printk("id=%u, callback=%ps, irq=%d, pp=%d, atomic_cnt=%d",
TP_printk("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, atomic_cnt=%d",
__entry->drm_id, __entry->func,
__entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
__entry->irq_reg, __entry->irq_bit, __entry->pp_idx, __entry->atomic_cnt)
);
DECLARE_EVENT_CLASS(dpu_drm_obj_template,
......@@ -484,12 +488,13 @@ DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending,
);
TRACE_EVENT(dpu_enc_wait_event_timeout,
TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time,
TP_PROTO(uint32_t drm_id, unsigned int irq_reg, unsigned int irq_bit, int rc, s64 time,
s64 expected_time, int atomic_cnt),
TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt),
TP_ARGS(drm_id, irq_reg, irq_bit, rc, time, expected_time, atomic_cnt),
TP_STRUCT__entry(
__field( uint32_t, drm_id )
__field( int, irq_idx )
__field( unsigned int, irq_reg )
__field( unsigned int, irq_bit )
__field( int, rc )
__field( s64, time )
__field( s64, expected_time )
......@@ -497,14 +502,15 @@ TRACE_EVENT(dpu_enc_wait_event_timeout,
),
TP_fast_assign(
__entry->drm_id = drm_id;
__entry->irq_idx = irq_idx;
__entry->irq_reg = irq_reg;
__entry->irq_bit = irq_bit;
__entry->rc = rc;
__entry->time = time;
__entry->expected_time = expected_time;
__entry->atomic_cnt = atomic_cnt;
),
TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
__entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time,
TP_printk("id=%u, IRQ=[%d, %d], rc=%d, time=%lld, expected=%lld cnt=%d",
__entry->drm_id, __entry->irq_reg, __entry->irq_bit, __entry->rc, __entry->time,
__entry->expected_time, __entry->atomic_cnt)
);
......@@ -863,30 +869,34 @@ TRACE_EVENT(dpu_intf_connect_ext_te,
);
TRACE_EVENT(dpu_core_irq_register_callback,
TP_PROTO(int irq_idx, void *callback),
TP_ARGS(irq_idx, callback),
TP_PROTO(unsigned int irq_reg, unsigned int irq_bit, void *callback),
TP_ARGS(irq_reg, irq_bit, callback),
TP_STRUCT__entry(
__field( int, irq_idx )
__field( unsigned int, irq_reg )
__field( unsigned int, irq_bit )
__field( void *, callback)
),
TP_fast_assign(
__entry->irq_idx = irq_idx;
__entry->irq_reg = irq_reg;
__entry->irq_bit = irq_bit;
__entry->callback = callback;
),
TP_printk("irq_idx:%d callback:%ps", __entry->irq_idx,
TP_printk("IRQ=[%d, %d] callback:%ps", __entry->irq_reg, __entry->irq_bit,
__entry->callback)
);
TRACE_EVENT(dpu_core_irq_unregister_callback,
TP_PROTO(int irq_idx),
TP_ARGS(irq_idx),
TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
TP_ARGS(irq_reg, irq_bit),
TP_STRUCT__entry(
__field( int, irq_idx )
__field( unsigned int, irq_reg )
__field( unsigned int, irq_bit )
),
TP_fast_assign(
__entry->irq_idx = irq_idx;
__entry->irq_reg = irq_reg;
__entry->irq_bit = irq_bit;
),
TP_printk("irq_idx:%d", __entry->irq_idx)
TP_printk("IRQ=[%d, %d]", __entry->irq_reg, __entry->irq_bit)
);
TRACE_EVENT(dpu_core_perf_update_clk,
......
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
View file @ 3f5ba636
......@@ -169,23 +169,16 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms,
struct dpu_vbif_set_ot_params *params)
{
struct dpu_hw_vbif *vbif;
struct dpu_hw_mdp *mdp;
bool forced_on = false;
u32 ot_lim;
int ret;
mdp = dpu_kms->hw_mdp;
vbif = dpu_get_vbif(dpu_kms, params->vbif_idx);
if (!vbif || !mdp) {
DRM_DEBUG_ATOMIC("invalid arguments vbif %d mdp %d\n",
vbif != NULL, mdp != NULL);
if (!vbif) {
DRM_DEBUG_ATOMIC("invalid arguments vbif %d\n", vbif != NULL);
return;
}
if (!mdp->ops.setup_clk_force_ctrl ||
!vbif->ops.set_limit_conf ||
!vbif->ops.set_halt_ctrl)
if (!vbif->ops.set_limit_conf || !vbif->ops.set_halt_ctrl)
return;
/* set write_gather_en for all write clients */
......@@ -200,8 +193,6 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms,
trace_dpu_perf_set_ot(params->num, params->xin_id, ot_lim,
params->vbif_idx);
forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true);
vbif->ops.set_limit_conf(vbif, params->xin_id, params->rd, ot_lim);
vbif->ops.set_halt_ctrl(vbif, params->xin_id, true);
......@@ -211,25 +202,19 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms,
trace_dpu_vbif_wait_xin_halt_fail(vbif->idx, params->xin_id);
vbif->ops.set_halt_ctrl(vbif, params->xin_id, false);
if (forced_on)
mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false);
}
void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms,
struct dpu_vbif_set_qos_params *params)
{
struct dpu_hw_vbif *vbif;
struct dpu_hw_mdp *mdp;
bool forced_on = false;
const struct dpu_vbif_qos_tbl *qos_tbl;
int i;
if (!params || !dpu_kms->hw_mdp) {
if (!params) {
DPU_ERROR("invalid arguments\n");
return;
}
mdp = dpu_kms->hw_mdp;
vbif = dpu_get_vbif(dpu_kms, params->vbif_idx);
......@@ -238,7 +223,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms,
return;
}
if (!vbif->ops.set_qos_remap || !mdp->ops.setup_clk_force_ctrl) {
if (!vbif->ops.set_qos_remap) {
DRM_DEBUG_ATOMIC("qos remap not supported\n");
return;
}
......@@ -251,8 +236,6 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms,
return;
}
forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true);
for (i = 0; i < qos_tbl->npriority_lvl; i++) {
DRM_DEBUG_ATOMIC("%s xin:%d lvl:%d/%d\n",
dpu_vbif_name(params->vbif_idx), params->xin_id, i,
......@@ -260,9 +243,6 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms,
vbif->ops.set_qos_remap(vbif, params->xin_id, i,
qos_tbl->priority_lvl[i]);
}
if (forced_on)
mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false);
}
void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms)
......
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h
View file @ 3f5ba636
......@@ -16,13 +16,11 @@ struct dpu_vbif_set_ot_params {
bool rd;
bool is_wfd;
u32 vbif_idx;
u32 clk_ctrl;
};
struct dpu_vbif_set_memtype_params {
u32 xin_id;
u32 vbif_idx;
u32 clk_ctrl;
bool is_cacheable;
};
......@@ -30,14 +28,12 @@ struct dpu_vbif_set_memtype_params {
* struct dpu_vbif_set_qos_params - QoS remapper parameter
* @vbif_idx: vbif identifier
* @xin_id: client interface identifier
* @clk_ctrl: clock control identifier of the xin
* @num: pipe identifier (debug only)
* @is_rt: true if pipe is used in real-time use case
*/
struct dpu_vbif_set_qos_params {
u32 vbif_idx;
u32 xin_id;
u32 clk_ctrl;
u32 num;
bool is_rt;
};
......
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
View file @ 3f5ba636
......@@ -379,7 +379,7 @@ struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms, const struct mdp5_smp_
{
struct mdp5_smp_state *state;
struct mdp5_global_state *global_state;
struct mdp5_smp *smp = NULL;
struct mdp5_smp *smp;
int ret;
smp = kzalloc(sizeof(*smp), GFP_KERNEL);
......
drivers/gpu/drm/msm/dp/dp_display.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/dp/dp_display.h
View file @ 3f5ba636
......@@ -12,6 +12,7 @@
struct msm_dp {
struct drm_device *drm_dev;
struct platform_device *pdev;
struct device *codec_dev;
struct drm_bridge *bridge;
struct drm_connector *connector;
......
drivers/gpu/drm/msm/dp/dp_drm.c
View file @ 3f5ba636
......@@ -272,7 +272,7 @@ static const struct drm_bridge_funcs edp_bridge_ops = {
.atomic_check = edp_bridge_atomic_check,
};
struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
int dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
struct drm_encoder *encoder)
{
int rc;
......@@ -281,7 +281,7 @@ struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *
dp_bridge = devm_kzalloc(dev->dev, sizeof(*dp_bridge), GFP_KERNEL);
if (!dp_bridge)
return ERR_PTR(-ENOMEM);
return -ENOMEM;
dp_bridge->dp_display = dp_display;
......@@ -307,14 +307,18 @@ struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *
DRM_BRIDGE_OP_MODES;
}
drm_bridge_add(bridge);
rc = devm_drm_bridge_add(dev->dev, bridge);
if (rc) {
DRM_ERROR("failed to add bridge, rc=%d\n", rc);
return rc;
}
rc = drm_bridge_attach(encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
if (rc) {
DRM_ERROR("failed to attach bridge, rc=%d\n", rc);
drm_bridge_remove(bridge);
return ERR_PTR(rc);
return rc;
}
if (dp_display->next_bridge) {
......@@ -323,12 +327,13 @@ struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *
DRM_BRIDGE_ATTACH_NO_CONNECTOR);
if (rc < 0) {
DRM_ERROR("failed to attach panel bridge: %d\n", rc);
drm_bridge_remove(bridge);
return ERR_PTR(rc);
return rc;
}
}
return bridge;
dp_display->bridge = bridge;
return 0;
}
/* connector initialization */
......
drivers/gpu/drm/msm/dp/dp_drm.h
View file @ 3f5ba636
......@@ -20,7 +20,7 @@ struct msm_dp_bridge {
#define to_dp_bridge(x) container_of((x), struct msm_dp_bridge, bridge)
struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct drm_encoder *encoder);
struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
int dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
struct drm_encoder *encoder);
void dp_bridge_atomic_enable(struct drm_bridge *drm_bridge,
......
drivers/gpu/drm/msm/dp/dp_link.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/dp/dp_panel.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/dp/dp_panel.h
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/dsi/dsi.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/dsi/dsi.h
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/dsi/dsi.xml.h
View file @ 3f5ba636
......@@ -664,6 +664,7 @@ static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap v
return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
}
#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
#define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x00100000
#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
......
drivers/gpu/drm/msm/dsi/dsi_host.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/dsi/dsi_manager.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/hdmi/hdmi.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/hdmi/hdmi.h
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
View file @ 3f5ba636
......@@ -147,9 +147,8 @@ int msm_hdmi_hpd_enable(struct drm_bridge *bridge)
return ret;
}
void msm_hdmi_hpd_disable(struct hdmi_bridge *hdmi_bridge)
void msm_hdmi_hpd_disable(struct hdmi *hdmi)
{
struct hdmi *hdmi = hdmi_bridge->hdmi;
const struct hdmi_platform_config *config = hdmi->config;
struct device *dev = &hdmi->pdev->dev;
int ret;
......
drivers/gpu/drm/msm/msm_debugfs.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/msm_drv.c
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/msm_drv.h
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/msm_kms.c 0 → 100644
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/msm_kms.h
View file @ 3f5ba636
This diff is collapsed.
drivers/gpu/drm/msm/msm_ringbuffer.h
View file @ 3f5ba636
This diff is collapsed.
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