Commit 3f63345d authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher

drm/amdgpu/mes10.1: add the mes fw api

Add the definitions of mes commands.
Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e25c0dcd
/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __MES_API_DEF_H__
#define __MES_API_DEF_H__
#pragma pack(push, 4)
typedef uint32_t uint32;
typedef uint64_t uint64;
#define MES_API_VERSION 1
//Driver submits one API(cmd) as a single Frame and this command size is same for all API
//to ease the debugging and parsing of ring buffer.
enum {API_FRAME_SIZE_IN_DWORDS = 64};
//To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in,
//this creates another queue
enum {API_NUMBER_OF_COMMAND_MAX = 32};
enum MES_API_TYPE
{
MES_API_TYPE_SCHEDULER = 1,
MES_API_TYPE_MAX
};
enum MES_SCH_API_OPCODE
{
MES_SCH_API_SET_HW_RSRC = 0,
MES_SCH_API_SET_SCHEDULING_CONFIG = 1, //agreegated db, quantums, etc
MES_SCH_API_ADD_QUEUE = 2,
MES_SCH_API_REMOVE_QUEUE = 3,
MES_SCH_API_PERFORM_YIELD = 4,
MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, //For windows GANG = Context
MES_SCH_API_SUSPEND = 6,
MES_SCH_API_RESUME = 7,
MES_SCH_API_RESET = 8,
MES_SCH_API_SET_LOG_BUFFER = 9,
MES_SCH_API_CHANGE_GANG_PRORITY = 10,
MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
MES_SCH_API_PROGRAM_GDS = 12,
MES_SCH_API_MAX = 0xFF
};
union MES_API_HEADER
{
struct
{
uint32 type : 4; // 0 - Invalid; 1 - Scheduling; 2 - TBD
uint32 opcode : 8;
uint32 dwsize : 8; //including header
uint32 reserved : 12;
};
uint32 u32All;
};
enum MES_AMD_PRIORITY_LEVEL
{
AMD_PRIORITY_LEVEL_LOW = 0,
AMD_PRIORITY_LEVEL_NORMAL = 1,
AMD_PRIORITY_LEVEL_MEDIUM = 2,
AMD_PRIORITY_LEVEL_HIGH = 3,
AMD_PRIORITY_LEVEL_REALTIME = 4,
AMD_PRIORITY_NUM_LEVELS
};
enum MES_QUEUE_TYPE
{
MES_QUEUE_TYPE_GFX,
MES_QUEUE_TYPE_COMPUTE,
MES_QUEUE_TYPE_SDMA,
MES_QUEUE_TYPE_MAX,
};
struct MES_API_STATUS
{
uint64 api_completion_fence_addr;
uint64 api_completion_fence_value;
};
enum { MAX_COMPUTE_PIPES = 8 };
enum { MAX_GFX_PIPES = 2 };
enum { MAX_SDMA_PIPES = 2 };
enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
enum { MAX_GFX_HQD_PER_PIPE = 8 };
enum { MAX_SDMA_HQD_PER_PIPE = 10 };
enum { MAX_QUEUES_IN_A_GANG = 8 };
enum VM_HUB_TYPE
{
VM_HUB_TYPE_GC = 0,
VM_HUB_TYPE_MM = 1,
VM_HUB_TYPE_MAX,
};
enum { VMID_INVALID = 0xffff };
enum { MAX_VMID_GCHUB = 16 };
enum { MAX_VMID_MMHUB = 16 };
enum MES_LOG_OPERATION
{
MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0
};
enum MES_LOG_CONTEXT_STATE
{
MES_LOG_CONTEXT_STATE_IDLE = 0,
MES_LOG_CONTEXT_STATE_RUNNING = 1,
MES_LOG_CONTEXT_STATE_READY = 2,
MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
};
struct MES_LOG_CONTEXT_STATE_CHANGE
{
void* h_context;
enum MES_LOG_CONTEXT_STATE new_context_state;
};
struct MES_LOG_ENTRY_HEADER
{
uint32 first_free_entry_index;
uint32 wraparound_count;
uint64 number_of_entries;
uint64 reserved[2];
};
struct MES_LOG_ENTRY_DATA
{
uint64 gpu_time_stamp;
uint32 operation_type; //operation_type is of MES_LOG_OPERATION type
uint32 reserved_operation_type_bits;
union
{
struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
uint64 reserved_operation_data[2];
};
};
struct MES_LOG_BUFFER
{
struct MES_LOG_ENTRY_HEADER header;
struct MES_LOG_ENTRY_DATA entries[1];
};
union MESAPI_SET_HW_RESOURCES
{
struct
{
union MES_API_HEADER header;
uint32 vmid_mask_mmhub;
uint32 vmid_mask_gfxhub;
uint32 gds_size;
uint32 paging_vmid;
uint32 compute_hqd_mask[MAX_COMPUTE_PIPES];
uint32 gfx_hqd_mask[MAX_GFX_PIPES];
uint32 sdma_hqd_mask[MAX_SDMA_PIPES];
uint32 agreegated_doorbells[AMD_PRIORITY_NUM_LEVELS];
uint64 g_sch_ctx_gpu_mc_ptr;
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__ADD_QUEUE
{
struct
{
union MES_API_HEADER header;
uint32 process_id;
uint64 page_table_base_addr;
uint64 process_va_start;
uint64 process_va_end;
uint64 process_quantum;
uint64 process_context_addr;
uint64 gang_quantum;
uint64 gang_context_addr;
uint32 inprocess_gang_priority;
enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
uint32 doorbell_offset;
uint64 mqd_addr;
uint64 wptr_addr;
enum MES_QUEUE_TYPE queue_type;
uint32 gds_base;
uint32 gds_size;
uint32 gws_base;
uint32 gws_size;
uint32 oa_mask;
struct
{
uint32 paging : 1;
uint32 program_gds : 1;
uint32 reserved : 30;
};
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__REMOVE_QUEUE
{
struct
{
union MES_API_HEADER header;
uint32 doorbell_offset;
uint64 gang_context_addr;
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__SET_SCHEDULING_CONFIG
{
struct
{
union MES_API_HEADER header;
// Grace period when preempting another priority band for this priority band.
// The value for idle priority band is ignored, as it never preempts other bands.
uint64 grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
// Default quantum for scheduling across processes within a priority band.
uint64 process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
// Default grace period for processes that preempt each other within a priority band.
uint64 process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
// For normal level this field specifies the target GPU percentage in situations when it's starved by the high level.
// Valid values are between 0 and 50, with the default being 10.
uint32 normal_yield_percent;
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__PERFORM_YIELD
{
struct
{
union MES_API_HEADER header;
uint32 dummy;
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__CHANGE_GANG_PRIORITY_LEVEL
{
struct
{
union MES_API_HEADER header;
uint32 inprocess_gang_priority;
enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
uint64 gang_quantum;
uint64 gang_context_addr;
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__SUSPEND
{
struct
{
union MES_API_HEADER header;
//false - suspend all gangs; true - specific gang
struct
{
uint32 suspend_all_gangs : 1;
uint32 reserved : 31;
};
//gang_context_addr is valid only if suspend_all = false
uint64 gang_context_addr;
uint64 suspend_fence_addr;
uint32 suspend_fence_value;
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__RESUME
{
struct
{
union MES_API_HEADER header;
//false - resume all gangs; true - specified gang
struct
{
uint32 resume_all_gangs : 1;
uint32 reserved : 31;
};
//valid only if resume_all_gangs = false
uint64 gang_context_addr;
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__RESET
{
struct
{
union MES_API_HEADER header;
struct
{
uint32 reset_queue : 1;
uint32 reserved : 31;
};
uint64 gang_context_addr;
uint32 doorbell_offset; //valid only if reset_queue = true
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__SET_LOGGING_BUFFER
{
struct
{
union MES_API_HEADER header;
//There are separate log buffers for each queue type
enum MES_QUEUE_TYPE log_type;
//Log buffer GPU Address
uint64 logging_buffer_addr;
//number of entries in the log buffer
uint32 number_of_entries;
//Entry index at which CPU interrupt needs to be signalled
uint32 interrupt_entry;
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__QUERY_MES_STATUS
{
struct
{
union MES_API_HEADER header;
bool mes_healthy; //0 - not healthy, 1 - healthy
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union MESAPI__PROGRAM_GDS
{
struct
{
union MES_API_HEADER header;
uint64 process_context_addr;
uint32 gds_base;
uint32 gds_size;
uint32 gws_base;
uint32 gws_size;
uint32 oa_mask;
struct MES_API_STATUS api_status;
};
uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
#pragma pack(pop)
#endif
......@@ -29,6 +29,7 @@
#include "gc/gc_10_1_0_offset.h"
#include "gc/gc_10_1_0_sh_mask.h"
#include "v10_structs.h"
#include "mes_api_def.h"
MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
......
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