Commit 3fa2f949 authored by Sanchayan Maity's avatar Sanchayan Maity Committed by Shawn Guo

ARM: dts: vfxxx: Fix erroneous property in esdhc0 node

Something seems to have gone wrong during the merging of the device
tree changes with the following patch

"ARM: dts: add property for maximum ADC clock frequencies"

The property "fsl,adck-max-frequency" instead of being applied for
the ADC1 node got applied to the esdhc0 node. This patch fixes it.
Signed-off-by: default avatarSanchayan Maity <maitysanchayan@gmail.com>
Fixes: def0641e ("ARM: dts: add property for maximum ADC clock frequencies")
Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 8005c49d
...@@ -461,6 +461,8 @@ adc1: adc@400bb000 { ...@@ -461,6 +461,8 @@ adc1: adc@400bb000 {
clock-names = "adc"; clock-names = "adc";
#io-channel-cells = <1>; #io-channel-cells = <1>;
status = "disabled"; status = "disabled";
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
}; };
esdhc0: esdhc@400b1000 { esdhc0: esdhc@400b1000 {
...@@ -472,8 +474,6 @@ esdhc0: esdhc@400b1000 { ...@@ -472,8 +474,6 @@ esdhc0: esdhc@400b1000 {
<&clks VF610_CLK_ESDHC0>; <&clks VF610_CLK_ESDHC0>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
status = "disabled"; status = "disabled";
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
}; };
esdhc1: esdhc@400b2000 { esdhc1: esdhc@400b2000 {
......
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