Commit 3ffcf2cb authored by Bruce Allan's avatar Bruce Allan Committed by Jeff Kirsher

e1000e: cleanup - move defines to appropriate header file

Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent bbf44127
...@@ -44,6 +44,8 @@ ...@@ -44,6 +44,8 @@
#define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */ #define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
#define E1000_EIAC_MASK_82574 0x01F00000 #define E1000_EIAC_MASK_82574 0x01F00000
#define E1000_IVAR_INT_ALLOC_VALID 0x8
/* Manageability Operation Mode mask */ /* Manageability Operation Mode mask */
#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000
......
...@@ -216,6 +216,8 @@ ...@@ -216,6 +216,8 @@
#define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
#define E1000_CTRL_RST 0x04000000 /* Global reset */ #define E1000_CTRL_RST 0x04000000 /* Global reset */
#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
...@@ -310,6 +312,7 @@ ...@@ -310,6 +312,7 @@
/* SerDes Control */ /* SerDes Control */
#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
/* Receive Checksum Control */ /* Receive Checksum Control */
#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
......
...@@ -1432,8 +1432,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter) ...@@ -1432,8 +1432,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
/* special write to serdes control register to enable SerDes analog /* special write to serdes control register to enable SerDes analog
* loopback * loopback
*/ */
#define E1000_SERDES_LB_ON 0x410 ew32(SCTL, E1000_SCTL_ENABLE_SERDES_LOOPBACK);
ew32(SCTL, E1000_SERDES_LB_ON);
e1e_flush(); e1e_flush();
usleep_range(10000, 20000); usleep_range(10000, 20000);
...@@ -1527,8 +1526,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter) ...@@ -1527,8 +1526,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
case e1000_82572: case e1000_82572:
if (hw->phy.media_type == e1000_media_type_fiber || if (hw->phy.media_type == e1000_media_type_fiber ||
hw->phy.media_type == e1000_media_type_internal_serdes) { hw->phy.media_type == e1000_media_type_internal_serdes) {
#define E1000_SERDES_LB_OFF 0x400 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
ew32(SCTL, E1000_SERDES_LB_OFF);
e1e_flush(); e1e_flush();
usleep_range(10000, 20000); usleep_range(10000, 20000);
break; break;
......
...@@ -1957,7 +1957,6 @@ static void e1000_configure_msix(struct e1000_adapter *adapter) ...@@ -1957,7 +1957,6 @@ static void e1000_configure_msix(struct e1000_adapter *adapter)
ew32(RFCTL, rfctl); ew32(RFCTL, rfctl);
} }
#define E1000_IVAR_INT_ALLOC_VALID 0x8
/* Configure Rx vector */ /* Configure Rx vector */
rx_ring->ims_val = E1000_IMS_RXQ0; rx_ring->ims_val = E1000_IMS_RXQ0;
adapter->eiac_mask |= rx_ring->ims_val; adapter->eiac_mask |= rx_ring->ims_val;
...@@ -5911,10 +5910,6 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake, ...@@ -5911,10 +5910,6 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
} }
ctrl = er32(CTRL); ctrl = er32(CTRL);
/* advertise wake from D3Cold */
#define E1000_CTRL_ADVD3WUC 0x00100000
/* phy power management enable */
#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
ctrl |= E1000_CTRL_ADVD3WUC; ctrl |= E1000_CTRL_ADVD3WUC;
if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment