Commit 403e1c5b authored by Ingo Molnar's avatar Ingo Molnar

Merge branch 'x86/mce' into x86/urgent

Merge in these fixlets.
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents fa83523f 80f03361
...@@ -15,6 +15,8 @@ ...@@ -15,6 +15,8 @@
#include <linux/compiler.h> #include <linux/compiler.h>
#include <asm/alternative.h> #include <asm/alternative.h>
#define BIT_64(n) (U64_C(1) << (n))
/* /*
* These have to be done with inline assembly: that way the bit-setting * These have to be done with inline assembly: that way the bit-setting
* is guaranteed to be atomic. All bit operations return 0 if the bit * is guaranteed to be atomic. All bit operations return 0 if the bit
......
...@@ -1458,9 +1458,9 @@ static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) ...@@ -1458,9 +1458,9 @@ static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
rdmsrl(msrs[i], val); rdmsrl(msrs[i], val);
/* CntP bit set? */ /* CntP bit set? */
if (val & BIT(62)) { if (val & BIT_64(62)) {
val &= ~BIT(62); val &= ~BIT_64(62);
wrmsrl(msrs[i], val); wrmsrl(msrs[i], val);
} }
} }
......
...@@ -5,8 +5,6 @@ ...@@ -5,8 +5,6 @@
#include <asm/mce.h> #include <asm/mce.h>
#define BIT_64(n) (U64_C(1) << (n))
#define EC(x) ((x) & 0xffff) #define EC(x) ((x) & 0xffff)
#define XEC(x, mask) (((x) >> 16) & mask) #define XEC(x, mask) (((x) >> 16) & mask)
......
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