clk: sunxi: Add dummy fixed rate clock for Allwinner A1X SoCs
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mike Turquette <mturquette@ti.com>
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drivers/clk/clk-sunxi.c
0 → 100644
include/linux/clk/sunxi.h
0 → 100644
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