Commit 411f5c7a authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (289 commits)
  davinci: DM644x EVM: register MUSB device earlier
  davinci: add spi devices on tnetv107x evm
  davinci: add ssp config for tnetv107x evm board
  davinci: add tnetv107x ssp platform device
  spi: add ti-ssp spi master driver
  mfd: add driver for sequencer serial port
  ARM: EXYNOS4: Implement Clock gating for System MMU
  ARM: EXYNOS4: Enhancement of System MMU driver
  ARM: EXYNOS4: Add support for gpio interrupts
  ARM: S5P: Add function to register gpio interrupt bank data
  ARM: S5P: Cleanup S5P gpio interrupt code
  ARM: EXYNOS4: Add missing GPYx banks
  ARM: S3C64XX: Fix section mismatch from cpufreq init
  ARM: EXYNOS4: Add keypad device to the SMDKV310
  ARM: EXYNOS4: Update clocks for keypad
  ARM: EXYNOS4: Update keypad base address
  ARM: EXYNOS4: Add keypad device helpers
  ARM: EXYNOS4: Add support for SATA on ARMLEX4210
  plat-nomadik: make GPIO interrupts work with cpuidle ApSleep
  mach-u300: define a dummy filter function for coh901318
  ...

Fix up various conflicts in
 - arch/arm/mach-exynos4/cpufreq.c
 - arch/arm/mach-mxs/gpio.c
 - drivers/net/Kconfig
 - drivers/tty/serial/Kconfig
 - drivers/tty/serial/Makefile
 - drivers/usb/gadget/fsl_mxc_udc.c
 - drivers/video/Kconfig
parents 6d7ed21d 9ced9f03
......@@ -5676,7 +5676,8 @@ F: arch/arm/mach-s3c2410/bast-ide.c
F: arch/arm/mach-s3c2410/bast-irq.c
TI DAVINCI MACHINE SUPPORT
M: Kevin Hilman <khilman@deeprootsystems.com>
M: Sekhar Nori <nsekhar@ti.com>
M: Kevin Hilman <khilman@ti.com>
L: davinci-linux-open-source@linux.davincidsp.com (subscribers-only)
Q: http://patchwork.kernel.org/project/linux-davinci/list/
S: Supported
......
......@@ -722,7 +722,8 @@ config ARCH_S5P64X0
select GENERIC_GPIO
select HAVE_CLK
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select ARCH_USES_GETTIMEOFFSET
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
help
......@@ -760,15 +761,16 @@ config ARCH_S5PV210
select HAVE_CLK
select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ
select ARCH_USES_GETTIMEOFFSET
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5PV210/S5PC110 series based systems
config ARCH_S5PV310
bool "Samsung S5PV310/S5PC210"
config ARCH_EXYNOS4
bool "Samsung EXYNOS4"
select CPU_V7
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
......@@ -779,7 +781,7 @@ config ARCH_S5PV310
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5PV310 series based systems
Samsung EXYNOS4 series based systems
config ARCH_SHARK
bool "Shark"
......@@ -993,7 +995,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig"
source "arch/arm/mach-s5pv310/Kconfig"
source "arch/arm/mach-exynos4/Kconfig"
source "arch/arm/mach-shmobile/Kconfig"
......@@ -1315,7 +1317,7 @@ config SMP
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
select USE_GENERIC_SMP_HELPERS
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
......@@ -1403,7 +1405,7 @@ config LOCAL_TIMERS
bool "Use local timer interrupts"
depends on SMP
default y
select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
......@@ -1415,7 +1417,7 @@ source kernel/Kconfig.preempt
config HZ
int
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
......
......@@ -181,7 +181,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5P6442) := s5p6442
machine-$(CONFIG_ARCH_S5PC100) := s5pc100
machine-$(CONFIG_ARCH_S5PV210) := s5pv210
machine-$(CONFIG_ARCH_S5PV310) := s5pv310
machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
machine-$(CONFIG_ARCH_SA1100) := sa1100
machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
......
CONFIG_EXPERIMENTAL=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_EXYNOS4=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDKC210=y
CONFIG_MACH_SMDKV310=y
CONFIG_MACH_UNIVERSAL_C210=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_HOTPLUG_CPU=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_DEBUG_S3C_UART=1
CONFIG_CRC_CCITT=y
......@@ -24,6 +24,7 @@ CONFIG_MACH_OPENRD_ULTIMATE=y
CONFIG_MACH_NETSPACE_V2=y
CONFIG_MACH_INETSPACE_V2=y
CONFIG_MACH_NETSPACE_MAX_V2=y
CONFIG_MACH_D2NET_V2=y
CONFIG_MACH_NET2BIG_V2=y
CONFIG_MACH_NET5BIG_V2=y
CONFIG_MACH_T5325=y
......
......@@ -110,7 +110,7 @@ CONFIG_MMC=y
CONFIG_MMC_BLOCK=m
CONFIG_MMC_SDHCI=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
CONFIG_LEDS_CLASS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_EXT2_FS=y
......
......@@ -10,6 +10,8 @@ CONFIG_S3C_BOOT_ERROR_RESET=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDK6440=y
CONFIG_MACH_SMDK6450=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CPU_32v6K=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
......
......@@ -13,6 +13,8 @@ CONFIG_MACH_AQUILA=y
CONFIG_MACH_GONI=y
CONFIG_MACH_SMDKC110=y
CONFIG_MACH_SMDKV210=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
......
......@@ -50,6 +50,9 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
}
}
/* Function pointer to optional machine-specific reinitialization */
extern void (*kexec_reinit)(void);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_KEXEC */
......
......@@ -12,11 +12,25 @@
#ifndef __ARM_PMU_H__
#define __ARM_PMU_H__
#include <linux/interrupt.h>
enum arm_pmu_type {
ARM_PMU_DEVICE_CPU = 0,
ARM_NUM_PMU_DEVICES,
};
/*
* struct arm_pmu_platdata - ARM PMU platform data
*
* @handle_irq: an optional handler which will be called from the interrupt and
* passed the address of the low level handler, and can be used to implement
* any platform specific handling before or after calling it.
*/
struct arm_pmu_platdata {
irqreturn_t (*handle_irq)(int irq, void *dev,
irq_handler_t pmu_handler);
};
#ifdef CONFIG_CPU_HAS_PMU
/**
......
......@@ -75,6 +75,11 @@ void machine_crash_shutdown(struct pt_regs *regs)
printk(KERN_INFO "Loading crashdump kernel...\n");
}
/*
* Function pointer to optional machine-specific reinitialization
*/
void (*kexec_reinit)(void);
void machine_kexec(struct kimage *image)
{
unsigned long page_list;
......@@ -104,6 +109,8 @@ void machine_kexec(struct kimage *image)
(unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
printk(KERN_INFO "Bye!\n");
if (kexec_reinit)
kexec_reinit();
local_irq_disable();
local_fiq_disable();
setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
......
......@@ -377,9 +377,18 @@ validate_group(struct perf_event *event)
return 0;
}
static irqreturn_t armpmu_platform_irq(int irq, void *dev)
{
struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev);
return plat->handle_irq(irq, dev, armpmu->handle_irq);
}
static int
armpmu_reserve_hardware(void)
{
struct arm_pmu_platdata *plat;
irq_handler_t handle_irq;
int i, err = -ENODEV, irq;
pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
......@@ -390,6 +399,12 @@ armpmu_reserve_hardware(void)
init_pmu(ARM_PMU_DEVICE_CPU);
plat = dev_get_platdata(&pmu_device->dev);
if (plat && plat->handle_irq)
handle_irq = armpmu_platform_irq;
else
handle_irq = armpmu->handle_irq;
if (pmu_device->num_resources < 1) {
pr_err("no irqs for PMUs defined\n");
return -ENODEV;
......@@ -400,7 +415,7 @@ armpmu_reserve_hardware(void)
if (irq < 0)
continue;
err = request_irq(irq, armpmu->handle_irq,
err = request_irq(irq, handle_irq,
IRQF_DISABLED | IRQF_NOBALANCING,
"armpmu", NULL);
if (err) {
......
......@@ -20,6 +20,8 @@
#include <linux/i2c/at24.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -30,6 +32,7 @@
#include <mach/da8xx.h>
#include <mach/usb.h>
#include <mach/aemif.h>
#include <mach/spi.h>
#define DA830_EVM_PHY_ID ""
/*
......@@ -534,6 +537,64 @@ static struct edma_rsv_info da830_edma_rsv[] = {
},
};
static struct mtd_partition da830evm_spiflash_part[] = {
[0] = {
.name = "DSP-UBL",
.offset = 0,
.size = SZ_8K,
.mask_flags = MTD_WRITEABLE,
},
[1] = {
.name = "ARM-UBL",
.offset = MTDPART_OFS_APPEND,
.size = SZ_16K + SZ_8K,
.mask_flags = MTD_WRITEABLE,
},
[2] = {
.name = "U-Boot",
.offset = MTDPART_OFS_APPEND,
.size = SZ_256K - SZ_32K,
.mask_flags = MTD_WRITEABLE,
},
[3] = {
.name = "U-Boot-Environment",
.offset = MTDPART_OFS_APPEND,
.size = SZ_16K,
.mask_flags = 0,
},
[4] = {
.name = "Kernel",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0,
},
};
static struct flash_platform_data da830evm_spiflash_data = {
.name = "m25p80",
.parts = da830evm_spiflash_part,
.nr_parts = ARRAY_SIZE(da830evm_spiflash_part),
.type = "w25x32",
};
static struct davinci_spi_config da830evm_spiflash_cfg = {
.io_type = SPI_IO_TYPE_DMA,
.c2tdelay = 8,
.t2cdelay = 8,
};
static struct spi_board_info da830evm_spi_info[] = {
{
.modalias = "m25p80",
.platform_data = &da830evm_spiflash_data,
.controller_data = &da830evm_spiflash_cfg,
.mode = SPI_MODE_0,
.max_speed_hz = 30000000,
.bus_num = 0,
.chip_select = 0,
},
};
static __init void da830_evm_init(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
......@@ -590,6 +651,12 @@ static __init void da830_evm_init(void)
ret = da8xx_register_rtc();
if (ret)
pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
ret = da8xx_register_spi(0, da830evm_spi_info,
ARRAY_SIZE(da830evm_spi_info));
if (ret)
pr_warning("da830_evm_init: spi 0 registration failed: %d\n",
ret);
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
......
......@@ -29,6 +29,8 @@
#include <linux/regulator/machine.h>
#include <linux/regulator/tps6507x.h>
#include <linux/input/tps6507x-ts.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -38,6 +40,7 @@
#include <mach/nand.h>
#include <mach/mux.h>
#include <mach/aemif.h>
#include <mach/spi.h>
#define DA850_EVM_PHY_ID "0:00"
#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
......@@ -48,6 +51,70 @@
#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
static struct mtd_partition da850evm_spiflash_part[] = {
[0] = {
.name = "UBL",
.offset = 0,
.size = SZ_64K,
.mask_flags = MTD_WRITEABLE,
},
[1] = {
.name = "U-Boot",
.offset = MTDPART_OFS_APPEND,
.size = SZ_512K,
.mask_flags = MTD_WRITEABLE,
},
[2] = {
.name = "U-Boot-Env",
.offset = MTDPART_OFS_APPEND,
.size = SZ_64K,
.mask_flags = MTD_WRITEABLE,
},
[3] = {
.name = "Kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M + SZ_512K,
.mask_flags = 0,
},
[4] = {
.name = "Filesystem",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
.mask_flags = 0,
},
[5] = {
.name = "MAC-Address",
.offset = SZ_8M - SZ_64K,
.size = SZ_64K,
.mask_flags = MTD_WRITEABLE,
},
};
static struct flash_platform_data da850evm_spiflash_data = {
.name = "m25p80",
.parts = da850evm_spiflash_part,
.nr_parts = ARRAY_SIZE(da850evm_spiflash_part),
.type = "m25p64",
};
static struct davinci_spi_config da850evm_spiflash_cfg = {
.io_type = SPI_IO_TYPE_DMA,
.c2tdelay = 8,
.t2cdelay = 8,
};
static struct spi_board_info da850evm_spi_info[] = {
{
.modalias = "m25p80",
.platform_data = &da850evm_spiflash_data,
.controller_data = &da850evm_spiflash_cfg,
.mode = SPI_MODE_0,
.max_speed_hz = 30000000,
.bus_num = 1,
.chip_select = 0,
},
};
static struct mtd_partition da850_evm_norflash_partition[] = {
{
.name = "bootloaders + env",
......@@ -231,8 +298,6 @@ static const short da850_evm_nor_pins[] = {
-1
};
static u32 ui_card_detected;
#if defined(CONFIG_MMC_DAVINCI) || \
defined(CONFIG_MMC_DAVINCI_MODULE)
#define HAS_MMC 1
......@@ -244,7 +309,7 @@ static inline void da850_evm_setup_nor_nand(void)
{
int ret = 0;
if (ui_card_detected & !HAS_MMC) {
if (!HAS_MMC) {
ret = davinci_cfg_reg_list(da850_evm_nand_pins);
if (ret)
pr_warning("da850_evm_init: nand mux setup failed: "
......@@ -394,7 +459,6 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
goto exp_setup_keys_fail;
}
ui_card_detected = 1;
pr_info("DA850/OMAP-L138 EVM UI card detected\n");
da850_evm_setup_nor_nand();
......@@ -664,6 +728,13 @@ static struct snd_platform_data da850_evm_snd_data = {
.rxnumevt = 1,
};
static const short da850_evm_mcasp_pins[] __initconst = {
DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
DA850_AXR_11, DA850_AXR_12,
-1
};
static int da850_evm_mmc_get_ro(int index)
{
return gpio_get_value(DA850_MMCSD_WP_PIN);
......@@ -683,6 +754,13 @@ static struct davinci_mmc_config da850_mmc_config = {
.version = MMC_CTLR_VERSION_2,
};
static const short da850_evm_mmcsd0_pins[] __initconst = {
DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
DA850_GPIO4_0, DA850_GPIO4_1,
-1
};
static void da850_panel_power_ctrl(int val)
{
/* lcd backlight */
......@@ -1070,7 +1148,7 @@ static __init void da850_evm_init(void)
ret);
if (HAS_MMC) {
ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
if (ret)
pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
" %d\n", ret);
......@@ -1106,7 +1184,7 @@ static __init void da850_evm_init(void)
__raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
__raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
ret = davinci_cfg_reg_list(da850_mcasp_pins);
ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
if (ret)
pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
ret);
......@@ -1153,6 +1231,12 @@ static __init void da850_evm_init(void)
if (ret)
pr_warning("da850_evm_init: suspend registration failed: %d\n",
ret);
ret = da8xx_register_spi(1, da850evm_spi_info,
ARRAY_SIZE(da850evm_spi_info));
if (ret)
pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
ret);
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
......
......@@ -440,11 +440,6 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
gpio_request(gpio + 7, "nCF_SEL");
gpio_direction_output(gpio + 7, 1);
/* irlml6401 switches over 1A, in under 8 msec;
* now it can be managed by nDRV_VBUS ...
*/
davinci_setup_usb(1000, 8);
return 0;
}
......@@ -705,6 +700,9 @@ static __init void davinci_evm_init(void)
davinci_serial_init(&uart_config);
dm644x_init_asp(&dm644x_evm_snd_data);
/* irlml6401 switches over 1A, in under 8 msec */
davinci_setup_usb(1000, 8);
soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
/* Register the fixup for PHY on DaVinci */
phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
......
......@@ -17,6 +17,8 @@
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/etherdevice.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -25,6 +27,7 @@
#include <mach/da8xx.h>
#include <mach/nand.h>
#include <mach/mux.h>
#include <mach/spi.h>
#define MITYOMAPL138_PHY_ID "0:03"
......@@ -44,38 +47,109 @@ struct factory_config {
static struct factory_config factory_config;
struct part_no_info {
const char *part_no; /* part number string of interest */
int max_freq; /* khz */
};
static struct part_no_info mityomapl138_pn_info[] = {
{
.part_no = "L138-C",
.max_freq = 300000,
},
{
.part_no = "L138-D",
.max_freq = 375000,
},
{
.part_no = "L138-F",
.max_freq = 456000,
},
{
.part_no = "1808-C",
.max_freq = 300000,
},
{
.part_no = "1808-D",
.max_freq = 375000,
},
{
.part_no = "1808-F",
.max_freq = 456000,
},
{
.part_no = "1810-D",
.max_freq = 375000,
},
};
#ifdef CONFIG_CPU_FREQ
static void mityomapl138_cpufreq_init(const char *partnum)
{
int i, ret;
for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
/*
* the part number has additional characters beyond what is
* stored in the table. This information is not needed for
* determining the speed grade, and would require several
* more table entries. Only check the first N characters
* for a match.
*/
if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
strlen(mityomapl138_pn_info[i].part_no))) {
da850_max_speed = mityomapl138_pn_info[i].max_freq;
break;
}
}
ret = da850_register_cpufreq("pll0_sysclk3");
if (ret)
pr_warning("cpufreq registration failed: %d\n", ret);
}
#else
static void mityomapl138_cpufreq_init(const char *partnum) { }
#endif
static void read_factory_config(struct memory_accessor *a, void *context)
{
int ret;
const char *partnum = NULL;
struct davinci_soc_info *soc_info = &davinci_soc_info;
ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
if (ret != sizeof(struct factory_config)) {
pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
ret);
return;
goto bad_config;
}
if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
factory_config.magic);
return;
goto bad_config;
}
if (factory_config.version != FACTORY_CONFIG_VERSION) {
pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
factory_config.version);
return;
goto bad_config;
}
pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum);
if (is_valid_ether_addr(factory_config.mac))
memcpy(soc_info->emac_pdata->mac_addr,
factory_config.mac, ETH_ALEN);
else
pr_warning("MityOMAPL138: Invalid MAC found "
"in factory config block\n");
partnum = factory_config.partnum;
pr_info("MityOMAPL138: Part Number = %s\n", partnum);
bad_config:
/* default maximum speed is valid for all platforms */
mityomapl138_cpufreq_init(partnum);
}
static struct at24_platform_data mityomapl138_fd_chip = {
......@@ -222,6 +296,82 @@ static int __init pmic_tps65023_init(void)
ARRAY_SIZE(mityomap_tps65023_info));
}
/*
* SPI Devices:
* SPI1_CS0: 8M Flash ST-M25P64-VME6G
*/
static struct mtd_partition spi_flash_partitions[] = {
[0] = {
.name = "ubl",
.offset = 0,
.size = SZ_64K,
.mask_flags = MTD_WRITEABLE,
},
[1] = {
.name = "u-boot",
.offset = MTDPART_OFS_APPEND,
.size = SZ_512K,
.mask_flags = MTD_WRITEABLE,
},
[2] = {
.name = "u-boot-env",
.offset = MTDPART_OFS_APPEND,
.size = SZ_64K,
.mask_flags = MTD_WRITEABLE,
},
[3] = {
.name = "periph-config",
.offset = MTDPART_OFS_APPEND,
.size = SZ_64K,
.mask_flags = MTD_WRITEABLE,
},
[4] = {
.name = "reserved",
.offset = MTDPART_OFS_APPEND,
.size = SZ_256K + SZ_64K,
},
[5] = {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M + SZ_1M,
},
[6] = {
.name = "fpga",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M,
},
[7] = {
.name = "spare",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct flash_platform_data mityomapl138_spi_flash_data = {
.name = "m25p80",
.parts = spi_flash_partitions,
.nr_parts = ARRAY_SIZE(spi_flash_partitions),
.type = "m24p64",
};
static struct davinci_spi_config spi_eprom_config = {
.io_type = SPI_IO_TYPE_DMA,
.c2tdelay = 8,
.t2cdelay = 8,
};
static struct spi_board_info mityomapl138_spi_flash_info[] = {
{
.modalias = "m25p80",
.platform_data = &mityomapl138_spi_flash_data,
.controller_data = &spi_eprom_config,
.mode = SPI_MODE_0,
.max_speed_hz = 30000000,
.bus_num = 1,
.chip_select = 0,
},
};
/*
* MityDSP-L138 includes a 256 MByte large-page NAND flash
* (128K blocks).
......@@ -377,16 +527,17 @@ static void __init mityomapl138_init(void)
mityomapl138_setup_nand();
ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,
ARRAY_SIZE(mityomapl138_spi_flash_info));
if (ret)
pr_warning("spi 1 registration failed: %d\n", ret);
mityomapl138_config_emac();
ret = da8xx_register_rtc();
if (ret)
pr_warning("rtc setup failed: %d\n", ret);
ret = da850_register_cpufreq("pll0_sysclk3");
if (ret)
pr_warning("cpufreq registration failed: %d\n", ret);
ret = da8xx_register_cpuidle();
if (ret)
pr_warning("cpuidle registration failed: %d\n", ret);
......
......@@ -19,6 +19,279 @@
#include <mach/cp_intc.h>
#include <mach/da8xx.h>
#include <mach/mux.h>
#define HAWKBOARD_PHY_ID "0:07"
#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
#define DA850_USB1_VBUS_PIN GPIO_TO_PIN(2, 4)
#define DA850_USB1_OC_PIN GPIO_TO_PIN(6, 13)
static short omapl138_hawk_mii_pins[] __initdata = {
DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
DA850_MDIO_D,
-1
};
static __init void omapl138_hawk_config_emac(void)
{
void __iomem *cfgchip3 = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
int ret;
u32 val;
struct davinci_soc_info *soc_info = &davinci_soc_info;
val = __raw_readl(cfgchip3);
val &= ~BIT(8);
ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins);
if (ret) {
pr_warning("%s: cpgmac/mii mux setup failed: %d\n",
__func__, ret);
return;
}
/* configure the CFGCHIP3 register for MII */
__raw_writel(val, cfgchip3);
pr_info("EMAC: MII PHY configured\n");
soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID;
ret = da8xx_register_emac();
if (ret)
pr_warning("%s: emac registration failed: %d\n",
__func__, ret);
}
/*
* The following EDMA channels/slots are not being used by drivers (for
* example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM/Hawkboard,
* hence they are being reserved for codecs on the DSP side.
*/
static const s16 da850_dma0_rsv_chans[][2] = {
/* (offset, number) */
{ 8, 6},
{24, 4},
{30, 2},
{-1, -1}
};
static const s16 da850_dma0_rsv_slots[][2] = {
/* (offset, number) */
{ 8, 6},
{24, 4},
{30, 50},
{-1, -1}
};
static const s16 da850_dma1_rsv_chans[][2] = {
/* (offset, number) */
{ 0, 28},
{30, 2},
{-1, -1}
};
static const s16 da850_dma1_rsv_slots[][2] = {
/* (offset, number) */
{ 0, 28},
{30, 90},
{-1, -1}
};
static struct edma_rsv_info da850_edma_cc0_rsv = {
.rsv_chans = da850_dma0_rsv_chans,
.rsv_slots = da850_dma0_rsv_slots,
};
static struct edma_rsv_info da850_edma_cc1_rsv = {
.rsv_chans = da850_dma1_rsv_chans,
.rsv_slots = da850_dma1_rsv_slots,
};
static struct edma_rsv_info *da850_edma_rsv[2] = {
&da850_edma_cc0_rsv,
&da850_edma_cc1_rsv,
};
static const short hawk_mmcsd0_pins[] = {
DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
DA850_GPIO3_12, DA850_GPIO3_13,
-1
};
static int da850_hawk_mmc_get_ro(int index)
{
return gpio_get_value(DA850_HAWK_MMCSD_WP_PIN);
}
static int da850_hawk_mmc_get_cd(int index)
{
return !gpio_get_value(DA850_HAWK_MMCSD_CD_PIN);
}
static struct davinci_mmc_config da850_mmc_config = {
.get_ro = da850_hawk_mmc_get_ro,
.get_cd = da850_hawk_mmc_get_cd,
.wires = 4,
.max_freq = 50000000,
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.version = MMC_CTLR_VERSION_2,
};
static __init void omapl138_hawk_mmc_init(void)
{
int ret;
ret = davinci_cfg_reg_list(hawk_mmcsd0_pins);
if (ret) {
pr_warning("%s: MMC/SD0 mux setup failed: %d\n",
__func__, ret);
return;
}
ret = gpio_request_one(DA850_HAWK_MMCSD_CD_PIN,
GPIOF_DIR_IN, "MMC CD");
if (ret < 0) {
pr_warning("%s: can not open GPIO %d\n",
__func__, DA850_HAWK_MMCSD_CD_PIN);
return;
}
ret = gpio_request_one(DA850_HAWK_MMCSD_WP_PIN,
GPIOF_DIR_IN, "MMC WP");
if (ret < 0) {
pr_warning("%s: can not open GPIO %d\n",
__func__, DA850_HAWK_MMCSD_WP_PIN);
goto mmc_setup_wp_fail;
}
ret = da8xx_register_mmcsd0(&da850_mmc_config);
if (ret) {
pr_warning("%s: MMC/SD0 registration failed: %d\n",
__func__, ret);
goto mmc_setup_mmcsd_fail;
}
return;
mmc_setup_mmcsd_fail:
gpio_free(DA850_HAWK_MMCSD_WP_PIN);
mmc_setup_wp_fail:
gpio_free(DA850_HAWK_MMCSD_CD_PIN);
}
static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id);
static da8xx_ocic_handler_t hawk_usb_ocic_handler;
static const short da850_hawk_usb11_pins[] = {
DA850_GPIO2_4, DA850_GPIO6_13,
-1
};
static int hawk_usb_set_power(unsigned port, int on)
{
gpio_set_value(DA850_USB1_VBUS_PIN, on);
return 0;
}
static int hawk_usb_get_power(unsigned port)
{
return gpio_get_value(DA850_USB1_VBUS_PIN);
}
static int hawk_usb_get_oci(unsigned port)
{
return !gpio_get_value(DA850_USB1_OC_PIN);
}
static int hawk_usb_ocic_notify(da8xx_ocic_handler_t handler)
{
int irq = gpio_to_irq(DA850_USB1_OC_PIN);
int error = 0;
if (handler != NULL) {
hawk_usb_ocic_handler = handler;
error = request_irq(irq, omapl138_hawk_usb_ocic_irq,
IRQF_DISABLED | IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING,
"OHCI over-current indicator", NULL);
if (error)
pr_err("%s: could not request IRQ to watch "
"over-current indicator changes\n", __func__);
} else {
free_irq(irq, NULL);
}
return error;
}
static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = {
.set_power = hawk_usb_set_power,
.get_power = hawk_usb_get_power,
.get_oci = hawk_usb_get_oci,
.ocic_notify = hawk_usb_ocic_notify,
/* TPS2087 switch @ 5V */
.potpgt = (3 + 1) / 2, /* 3 ms max */
};
static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id)
{
hawk_usb_ocic_handler(&omapl138_hawk_usb11_pdata, 1);
return IRQ_HANDLED;
}
static __init void omapl138_hawk_usb_init(void)
{
int ret;
u32 cfgchip2;
ret = davinci_cfg_reg_list(da850_hawk_usb11_pins);
if (ret) {
pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
__func__, ret);
return;
}
/* Setup the Ref. clock frequency for the HAWK at 24 MHz. */
cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
cfgchip2 &= ~CFGCHIP2_REFFREQ;
cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ;
__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
ret = gpio_request_one(DA850_USB1_VBUS_PIN,
GPIOF_DIR_OUT, "USB1 VBUS");
if (ret < 0) {
pr_err("%s: failed to request GPIO for USB 1.1 port "
"power control: %d\n", __func__, ret);
return;
}
ret = gpio_request_one(DA850_USB1_OC_PIN,
GPIOF_DIR_IN, "USB1 OC");
if (ret < 0) {
pr_err("%s: failed to request GPIO for USB 1.1 port "
"over-current indicator: %d\n", __func__, ret);
goto usb11_setup_oc_fail;
}
ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata);
if (ret) {
pr_warning("%s: USB 1.1 registration failed: %d\n",
__func__, ret);
goto usb11_setup_fail;
}
return;
usb11_setup_fail:
gpio_free(DA850_USB1_OC_PIN);
usb11_setup_oc_fail:
gpio_free(DA850_USB1_VBUS_PIN);
}
static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
.enabled_uarts = 0x7,
......@@ -30,6 +303,17 @@ static __init void omapl138_hawk_init(void)
davinci_serial_init(&omapl138_hawk_uart_config);
omapl138_hawk_config_emac();
ret = da850_register_edma(da850_edma_rsv);
if (ret)
pr_warning("%s: EDMA registration failed: %d\n",
__func__, ret);
omapl138_hawk_mmc_init();
omapl138_hawk_usb_init();
ret = da8xx_register_watchdog();
if (ret)
pr_warning("omapl138_hawk_init: "
......
......@@ -25,6 +25,7 @@
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
......@@ -37,6 +38,7 @@
#define EVM_MMC_WP_GPIO 21
#define EVM_MMC_CD_GPIO 24
#define EVM_SPI_CS_GPIO 54
static int initialize_gpio(int gpio, char *desc)
{
......@@ -99,6 +101,12 @@ static const short uart1_pins[] __initdata = {
-1
};
static const short ssp_pins[] __initdata = {
TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
TNETV107X_SSP1_3, -1
};
static struct mtd_partition nand_partitions[] = {
/* bootloader (U-Boot, etc) in first 12 sectors */
{
......@@ -196,19 +204,68 @@ static struct matrix_keypad_platform_data keypad_config = {
.no_autorepeat = 0,
};
static void spi_select_device(int cs)
{
static int gpio;
if (!gpio) {
int ret;
ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel");
if (ret < 0) {
pr_err("cannot open spi chipsel gpio\n");
gpio = -ENOSYS;
return;
} else {
gpio = EVM_SPI_CS_GPIO;
gpio_direction_output(gpio, 0);
}
}
if (gpio < 0)
return;
return gpio_set_value(gpio, cs ? 1 : 0);
}
static struct ti_ssp_spi_data spi_master_data = {
.num_cs = 2,
.select = spi_select_device,
.iosel = SSP_PIN_SEL(0, SSP_CLOCK) | SSP_PIN_SEL(1, SSP_DATA) |
SSP_PIN_SEL(2, SSP_CHIPSEL) | SSP_PIN_SEL(3, SSP_IN) |
SSP_INPUT_SEL(3),
};
static struct ti_ssp_data ssp_config = {
.out_clock = 250 * 1000,
.dev_data = {
[1] = {
.dev_name = "ti-ssp-spi",
.pdata = &spi_master_data,
.pdata_size = sizeof(spi_master_data),
},
},
};
static struct tnetv107x_device_info evm_device_info __initconst = {
.serial_config = &serial_config,
.mmc_config[1] = &mmc_config, /* controller 1 */
.nand_config[0] = &nand_config, /* chip select 0 */
.keypad_config = &keypad_config,
.ssp_config = &ssp_config,
};
static struct spi_board_info spi_info[] __initconst = {
};
static __init void tnetv107x_evm_board_init(void)
{
davinci_cfg_reg_list(sdio1_pins);
davinci_cfg_reg_list(uart1_pins);
davinci_cfg_reg_list(ssp_pins);
tnetv107x_devices_init(&evm_device_info);
spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
......
......@@ -148,7 +148,7 @@ static struct clk scr2_ss_clk = {
static struct clk dmax_clk = {
.name = "dmax",
.parent = &pll0_sysclk2,
.lpsc = DA8XX_LPSC0_DMAX,
.lpsc = DA8XX_LPSC0_PRUSS,
.flags = ALWAYS_ENABLED,
};
......@@ -397,8 +397,8 @@ static struct clk_lookup da830_clks[] = {
CLK(NULL, "uart0", &uart0_clk),
CLK(NULL, "uart1", &uart1_clk),
CLK(NULL, "uart2", &uart2_clk),
CLK("dm_spi.0", NULL, &spi0_clk),
CLK("dm_spi.1", NULL, &spi1_clk),
CLK("spi_davinci.0", NULL, &spi0_clk),
CLK("spi_davinci.1", NULL, &spi1_clk),
CLK(NULL, "ecap0", &ecap0_clk),
CLK(NULL, "ecap1", &ecap1_clk),
CLK(NULL, "ecap2", &ecap2_clk),
......
......@@ -345,6 +345,34 @@ static struct clk aemif_clk = {
.flags = ALWAYS_ENABLED,
};
static struct clk usb11_clk = {
.name = "usb11",
.parent = &pll0_sysclk4,
.lpsc = DA8XX_LPSC1_USB11,
.gpsc = 1,
};
static struct clk usb20_clk = {
.name = "usb20",
.parent = &pll0_sysclk2,
.lpsc = DA8XX_LPSC1_USB20,
.gpsc = 1,
};
static struct clk spi0_clk = {
.name = "spi0",
.parent = &pll0_sysclk2,
.lpsc = DA8XX_LPSC0_SPI0,
};
static struct clk spi1_clk = {
.name = "spi1",
.parent = &pll0_sysclk2,
.lpsc = DA8XX_LPSC1_SPI1,
.gpsc = 1,
.flags = DA850_CLK_ASYNC3,
};
static struct clk_lookup da850_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "pll0", &pll0_clk),
......@@ -387,6 +415,10 @@ static struct clk_lookup da850_clks[] = {
CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
CLK(NULL, "aemif", &aemif_clk),
CLK(NULL, "usb11", &usb11_clk),
CLK(NULL, "usb20", &usb20_clk),
CLK("spi_davinci.0", NULL, &spi0_clk),
CLK("spi_davinci.1", NULL, &spi1_clk),
CLK(NULL, NULL, NULL),
};
......@@ -543,30 +575,19 @@ static const struct mux_config da850_pins[] = {
MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
/* GPIO function */
MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
#endif
};
const short da850_uart0_pins[] __initdata = {
DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
-1
};
const short da850_uart1_pins[] __initdata = {
DA850_UART1_RXD, DA850_UART1_TXD,
-1
};
const short da850_uart2_pins[] __initdata = {
DA850_UART2_RXD, DA850_UART2_TXD,
-1
};
const short da850_i2c0_pins[] __initdata = {
DA850_I2C0_SDA, DA850_I2C0_SCL,
-1
......@@ -577,24 +598,6 @@ const short da850_i2c1_pins[] __initdata = {
-1
};
const short da850_cpgmac_pins[] __initdata = {
DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
DA850_MDIO_D, DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, DA850_RMII_RXER,
DA850_RMII_MHZ_50_CLK,
-1
};
const short da850_mcasp_pins[] __initdata = {
DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
DA850_AXR_11, DA850_AXR_12,
-1
};
const short da850_lcdcntl_pins[] __initdata = {
DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
......@@ -604,29 +607,6 @@ const short da850_lcdcntl_pins[] __initdata = {
-1
};
const short da850_mmcsd0_pins[] __initdata = {
DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
DA850_GPIO4_0, DA850_GPIO4_1,
-1
};
const short da850_emif25_pins[] __initdata = {
DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE,
DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11,
DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15,
DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3,
DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7,
DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11,
DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15,
DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19,
DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23,
-1
};
/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
[IRQ_DA8XX_COMMTX] = 7,
......@@ -764,6 +744,13 @@ static struct davinci_id da850_ids[] = {
.cpu_id = DAVINCI_CPU_ID_DA850,
.name = "da850/omap-l138",
},
{
.variant = 0x1,
.part_no = 0xb7d1,
.manufacturer = 0x017, /* 0x02f >> 1 */
.cpu_id = DAVINCI_CPU_ID_DA850,
.name = "da850/omap-l138/am18x",
},
};
static struct davinci_timer_instance da850_timer_instance[4] = {
......
......@@ -38,12 +38,23 @@
#define DA8XX_EMAC_MDIO_BASE 0x01e24000
#define DA8XX_GPIO_BASE 0x01e26000
#define DA8XX_I2C1_BASE 0x01e28000
#define DA8XX_SPI0_BASE 0x01c41000
#define DA8XX_SPI1_BASE 0x01f0e000
#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
#define DA8XX_EMAC_RAM_OFFSET 0x0000
#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
#define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
#define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
#define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
#define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
#define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
#define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
#define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
#define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
void __iomem *da8xx_syscfg0_base;
void __iomem *da8xx_syscfg1_base;
......@@ -573,13 +584,13 @@ static struct resource da8xx_mmcsd0_resources[] = {
.flags = IORESOURCE_IRQ,
},
{ /* DMA RX */
.start = EDMA_CTLR_CHAN(0, 16),
.end = EDMA_CTLR_CHAN(0, 16),
.start = DA8XX_DMA_MMCSD0_RX,
.end = DA8XX_DMA_MMCSD0_RX,
.flags = IORESOURCE_DMA,
},
{ /* DMA TX */
.start = EDMA_CTLR_CHAN(0, 17),
.end = EDMA_CTLR_CHAN(0, 17),
.start = DA8XX_DMA_MMCSD0_TX,
.end = DA8XX_DMA_MMCSD0_TX,
.flags = IORESOURCE_DMA,
},
};
......@@ -610,13 +621,13 @@ static struct resource da850_mmcsd1_resources[] = {
.flags = IORESOURCE_IRQ,
},
{ /* DMA RX */
.start = EDMA_CTLR_CHAN(1, 28),
.end = EDMA_CTLR_CHAN(1, 28),
.start = DA850_DMA_MMCSD1_RX,
.end = DA850_DMA_MMCSD1_RX,
.flags = IORESOURCE_DMA,
},
{ /* DMA TX */
.start = EDMA_CTLR_CHAN(1, 29),
.end = EDMA_CTLR_CHAN(1, 29),
.start = DA850_DMA_MMCSD1_TX,
.end = DA850_DMA_MMCSD1_TX,
.flags = IORESOURCE_DMA,
},
};
......@@ -725,3 +736,101 @@ int __init da8xx_register_cpuidle(void)
return platform_device_register(&da8xx_cpuidle_device);
}
static struct resource da8xx_spi0_resources[] = {
[0] = {
.start = DA8XX_SPI0_BASE,
.end = DA8XX_SPI0_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DA8XX_SPINT0,
.end = IRQ_DA8XX_SPINT0,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DA8XX_DMA_SPI0_RX,
.end = DA8XX_DMA_SPI0_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DA8XX_DMA_SPI0_TX,
.end = DA8XX_DMA_SPI0_TX,
.flags = IORESOURCE_DMA,
},
};
static struct resource da8xx_spi1_resources[] = {
[0] = {
.start = DA8XX_SPI1_BASE,
.end = DA8XX_SPI1_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DA8XX_SPINT1,
.end = IRQ_DA8XX_SPINT1,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DA8XX_DMA_SPI1_RX,
.end = DA8XX_DMA_SPI1_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DA8XX_DMA_SPI1_TX,
.end = DA8XX_DMA_SPI1_TX,
.flags = IORESOURCE_DMA,
},
};
struct davinci_spi_platform_data da8xx_spi_pdata[] = {
[0] = {
.version = SPI_VERSION_2,
.intr_line = 1,
.dma_event_q = EVENTQ_0,
},
[1] = {
.version = SPI_VERSION_2,
.intr_line = 1,
.dma_event_q = EVENTQ_0,
},
};
static struct platform_device da8xx_spi_device[] = {
[0] = {
.name = "spi_davinci",
.id = 0,
.num_resources = ARRAY_SIZE(da8xx_spi0_resources),
.resource = da8xx_spi0_resources,
.dev = {
.platform_data = &da8xx_spi_pdata[0],
},
},
[1] = {
.name = "spi_davinci",
.id = 1,
.num_resources = ARRAY_SIZE(da8xx_spi1_resources),
.resource = da8xx_spi1_resources,
.dev = {
.platform_data = &da8xx_spi_pdata[1],
},
},
};
int __init da8xx_register_spi(int instance, struct spi_board_info *info,
unsigned len)
{
int ret;
if (instance < 0 || instance > 1)
return -EINVAL;
ret = spi_register_board_info(info, len);
if (ret)
pr_warning("%s: failed to register board info for spi %d :"
" %d\n", __func__, instance, ret);
da8xx_spi_pdata[instance].num_chipselect = len;
return platform_device_register(&da8xx_spi_device[instance]);
}
......@@ -35,6 +35,7 @@
#define TNETV107X_SDIO0_BASE 0x08088700
#define TNETV107X_SDIO1_BASE 0x08088800
#define TNETV107X_KEYPAD_BASE 0x08088a00
#define TNETV107X_SSP_BASE 0x08088c00
#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
......@@ -342,6 +343,25 @@ static struct platform_device tsc_device = {
.resource = tsc_resources,
};
static struct resource ssp_resources[] = {
{
.start = TNETV107X_SSP_BASE,
.end = TNETV107X_SSP_BASE + 0x1ff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_TNETV107X_SSP,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device ssp_device = {
.name = "ti-ssp",
.id = -1,
.num_resources = ARRAY_SIZE(ssp_resources),
.resource = ssp_resources,
};
void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
{
int i, error;
......@@ -380,4 +400,9 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
keypad_device.dev.platform_data = info->keypad_config;
platform_device_register(&keypad_device);
}
if (info->ssp_config) {
ssp_device.dev.platform_data = info->ssp_config;
platform_device_register(&ssp_device);
}
}
......@@ -403,16 +403,13 @@ static struct resource dm355_spi0_resources[] = {
.start = 16,
.flags = IORESOURCE_DMA,
},
{
.start = EVENTQ_1,
.flags = IORESOURCE_DMA,
},
};
static struct davinci_spi_platform_data dm355_spi0_pdata = {
.version = SPI_VERSION_1,
.num_chipselect = 2,
.cshold_bug = true,
.dma_event_q = EVENTQ_1,
};
static struct platform_device dm355_spi0_device = {
.name = "spi_davinci",
......
......@@ -625,6 +625,7 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
static struct davinci_spi_platform_data dm365_spi0_pdata = {
.version = SPI_VERSION_1,
.num_chipselect = 2,
.dma_event_q = EVENTQ_3,
};
static struct resource dm365_spi0_resources[] = {
......@@ -645,10 +646,6 @@ static struct resource dm365_spi0_resources[] = {
.start = 16,
.flags = IORESOURCE_DMA,
},
{
.start = EVENTQ_3,
.flags = IORESOURCE_DMA,
},
};
static struct platform_device dm365_spi0_device = {
......
......@@ -15,6 +15,7 @@
#include <linux/platform_device.h>
#include <linux/davinci_emac.h>
#include <linux/spi/spi.h>
#include <mach/serial.h>
#include <mach/edma.h>
......@@ -23,6 +24,7 @@
#include <mach/mmc.h>
#include <mach/usb.h>
#include <mach/pm.h>
#include <mach/spi.h>
extern void __iomem *da8xx_syscfg0_base;
extern void __iomem *da8xx_syscfg1_base;
......@@ -77,6 +79,7 @@ void __init da850_init(void);
int da830_register_edma(struct edma_rsv_info *rsv);
int da850_register_edma(struct edma_rsv_info *rsv[2]);
int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
int da8xx_register_spi(int instance, struct spi_board_info *info, unsigned len);
int da8xx_register_watchdog(void);
int da8xx_register_usb20(unsigned mA, unsigned potpgt);
int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
......@@ -95,6 +98,7 @@ extern struct platform_device da8xx_serial_device;
extern struct emac_platform_data da8xx_emac_pdata;
extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
extern struct davinci_spi_platform_data da8xx_spi_pdata[];
extern struct platform_device da8xx_wdt_device;
......@@ -123,15 +127,8 @@ extern const short da830_ecap2_pins[];
extern const short da830_eqep0_pins[];
extern const short da830_eqep1_pins[];
extern const short da850_uart0_pins[];
extern const short da850_uart1_pins[];
extern const short da850_uart2_pins[];
extern const short da850_i2c0_pins[];
extern const short da850_i2c1_pins[];
extern const short da850_cpgmac_pins[];
extern const short da850_mcasp_pins[];
extern const short da850_lcdcntl_pins[];
extern const short da850_mmcsd0_pins[];
extern const short da850_emif25_pins[];
#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
......@@ -151,42 +151,6 @@ struct edmacc_param {
#define DA830_DMACH2EVENT_MAP1 0x00000000u
#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
/* DA830 specific EDMA3 Events Information */
enum DA830_edma_ch {
DA830_DMACH_MCASP0_RX,
DA830_DMACH_MCASP0_TX,
DA830_DMACH_MCASP1_RX,
DA830_DMACH_MCASP1_TX,
DA830_DMACH_MCASP2_RX,
DA830_DMACH_MCASP2_TX,
DA830_DMACH_GPIO_BNK0INT,
DA830_DMACH_GPIO_BNK1INT,
DA830_DMACH_UART0_RX,
DA830_DMACH_UART0_TX,
DA830_DMACH_TMR64P0_EVTOUT12,
DA830_DMACH_TMR64P0_EVTOUT34,
DA830_DMACH_UART1_RX,
DA830_DMACH_UART1_TX,
DA830_DMACH_SPI0_RX,
DA830_DMACH_SPI0_TX,
DA830_DMACH_MMCSD_RX,
DA830_DMACH_MMCSD_TX,
DA830_DMACH_SPI1_RX,
DA830_DMACH_SPI1_TX,
DA830_DMACH_DMAX_EVTOUT6,
DA830_DMACH_DMAX_EVTOUT7,
DA830_DMACH_GPIO_BNK2INT,
DA830_DMACH_GPIO_BNK3INT,
DA830_DMACH_I2C0_RX,
DA830_DMACH_I2C0_TX,
DA830_DMACH_I2C1_RX,
DA830_DMACH_I2C1_TX,
DA830_DMACH_GPIO_BNK4INT,
DA830_DMACH_GPIO_BNK5INT,
DA830_DMACH_UART2_RX,
DA830_DMACH_UART2_TX
};
/*ch_status paramater of callback function possible values*/
#define DMA_COMPLETE 1
#define DMA_CC_ERROR 2
......
......@@ -908,11 +908,15 @@ enum davinci_da850_index {
DA850_NEMA_CS_2,
/* GPIO function */
DA850_GPIO2_4,
DA850_GPIO2_6,
DA850_GPIO2_8,
DA850_GPIO2_15,
DA850_GPIO3_12,
DA850_GPIO3_13,
DA850_GPIO4_0,
DA850_GPIO4_1,
DA850_GPIO6_13,
DA850_RTC_ALARM,
};
......
......@@ -150,7 +150,7 @@
#define DA8XX_LPSC0_SCR0_SS 10
#define DA8XX_LPSC0_SCR1_SS 11
#define DA8XX_LPSC0_SCR2_SS 12
#define DA8XX_LPSC0_DMAX 13
#define DA8XX_LPSC0_PRUSS 13
#define DA8XX_LPSC0_ARM 14
#define DA8XX_LPSC0_GEM 15
......
......@@ -19,6 +19,8 @@
#ifndef __ARCH_ARM_DAVINCI_SPI_H
#define __ARCH_ARM_DAVINCI_SPI_H
#include <mach/edma.h>
#define SPI_INTERN_CS 0xFF
enum {
......@@ -39,6 +41,8 @@ enum {
* to populate if all chip-selects are internal.
* @cshold_bug: set this to true if the SPI controller on your chip requires
* a write to CSHOLD bit in between transfers (like in DM355).
* @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any
* device on the bus.
*/
struct davinci_spi_platform_data {
u8 version;
......@@ -46,6 +50,7 @@ struct davinci_spi_platform_data {
u8 intr_line;
u8 *chip_sel;
bool cshold_bug;
enum dma_event_q dma_event_q;
};
/**
......
......@@ -34,6 +34,7 @@
#include <linux/serial_8250.h>
#include <linux/input/matrix_keypad.h>
#include <linux/mfd/ti_ssp.h>
#include <mach/mmc.h>
#include <mach/nand.h>
......@@ -44,6 +45,7 @@ struct tnetv107x_device_info {
struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */
struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */
struct matrix_keypad_platform_data *keypad_config;
struct ti_ssp_data *ssp_config;
};
extern struct platform_device tnetv107x_wdt_device;
......
......@@ -278,7 +278,7 @@ static struct clk_lookup clks[] = {
CLK(NULL, "timer1", &clk_timer1),
CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm),
CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp),
CLK("ti-ssp.0", NULL, &clk_ssp),
CLK("ti-ssp", NULL, &clk_ssp),
CLK(NULL, "clk_tdm0", &clk_tdm0),
CLK(NULL, "clk_vlynq", &clk_vlynq),
CLK(NULL, "clk_mcdma", &clk_mcdma),
......
......@@ -90,6 +90,7 @@ MACHINE_START(CM_A510, "Compulab CM-A510 Board")
.boot_params = 0x00000100,
.init_machine = cm_a510_init,
.map_io = dove_map_io,
.init_early = dove_init_early,
.init_irq = dove_init_irq,
.timer = &dove_timer,
MACHINE_END
......@@ -532,6 +532,11 @@ void __init dove_i2c_init(void)
/*****************************************************************************
* Time handling
****************************************************************************/
void __init dove_init_early(void)
{
orion_time_set_base(TIMER_VIRT_BASE);
}
static int get_tclk(void)
{
/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
......@@ -540,7 +545,8 @@ static int get_tclk(void)
static void dove_timer_init(void)
{
orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_DOVE_BRIDGE, get_tclk());
}
struct sys_timer dove_timer = {
......
......@@ -22,6 +22,7 @@ extern struct mbus_dram_target_info dove_mbus_dram_info;
*/
void dove_map_io(void);
void dove_init(void);
void dove_init_early(void);
void dove_init_irq(void);
void dove_setup_cpu_mbus(void);
void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
......
......@@ -97,6 +97,7 @@ MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
.boot_params = 0x00000100,
.init_machine = dove_db_init,
.map_io = dove_map_io,
.init_early = dove_init_early,
.init_irq = dove_init_irq,
.timer = &dove_timer,
MACHINE_END
......@@ -26,10 +26,6 @@
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
......
......@@ -130,7 +130,8 @@
#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
......
......@@ -6,46 +6,4 @@
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#include <asm/errno.h>
#include <mach/irqs.h>
#include <plat/gpio.h>
#include <asm-generic/gpio.h> /* cansleep wrappers */
#define GPIO_MAX 72
#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00)
#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20)
#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : \
((pin < 64) ? GPIO_BASE_HI : \
DOVE_GPIO2_VIRT_BASE))
#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00)
#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04)
#define GPIO_BLINK_EN(pin) (GPIO_BASE(pin) + 0x08)
#define GPIO_IN_POL(pin) (GPIO_BASE(pin) + 0x0c)
#define GPIO_DATA_IN(pin) (GPIO_BASE(pin) + 0x10)
#define GPIO_EDGE_CAUSE(pin) (GPIO_BASE(pin) + 0x14)
#define GPIO_EDGE_MASK(pin) (GPIO_BASE(pin) + 0x18)
#define GPIO_LEVEL_MASK(pin) (GPIO_BASE(pin) + 0x1c)
static inline int gpio_to_irq(int pin)
{
if (pin < NR_GPIO_IRQS)
return pin + IRQ_DOVE_GPIO_START;
return -EINVAL;
}
static inline int irq_to_gpio(int irq)
{
if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
return irq - IRQ_DOVE_GPIO_START;
return -EINVAL;
}
#endif
......@@ -92,10 +92,5 @@
#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
/* Required for compatability with PXA AC97 driver. */
#define IRQ_AC97 IRQ_DOVE_AC97
/* Required for compatability with PXA DMA driver. */
#define IRQ_DMA IRQ_DOVE_PDMA
/* Required for compatability with PXA NAND driver */
#define IRQ_NAND IRQ_DOVE_NAND
#endif
......@@ -99,11 +99,21 @@ void __init dove_init_irq(void)
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
/*
* Mask and clear GPIO IRQ interrupts.
* Initialize gpiolib for GPIOs 0-71.
*/
writel(0, GPIO_LEVEL_MASK(0));
writel(0, GPIO_EDGE_MASK(0));
writel(0, GPIO_EDGE_CAUSE(0));
orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START);
set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 32);
set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 64);
/*
* Mask and clear PMU interrupts
......@@ -111,18 +121,6 @@ void __init dove_init_irq(void)
writel(0, PMU_INTERRUPT_MASK);
writel(0, PMU_INTERRUPT_CAUSE);
for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_desc[i].status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
set_irq_chip(i, &pmu_irq_chip);
set_irq_handler(i, handle_level_irq);
......
# arch/arm/mach-s5pv310/Kconfig
# arch/arm/mach-exynos4/Kconfig
#
# Copyright (c) 2010 Samsung Electronics Co., Ltd.
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
# Configuration options for the S5PV310
# Configuration options for the EXYNOS4
if ARCH_S5PV310
if ARCH_EXYNOS4
config CPU_S5PV310
config CPU_EXYNOS4210
bool
select S3C_PL330_DMA
help
Enable S5PV310 CPU support
Enable EXYNOS4210 CPU support
config S5PV310_DEV_PD
config EXYNOS4_MCT
bool "Kernel timer support by MCT"
help
Use MCT (Multi Core Timer) as kernel timers
config EXYNOS4_DEV_PD
bool
help
Compile in platform device definitions for Power Domain
config S5PV310_SETUP_I2C1
config EXYNOS4_DEV_SYSMMU
bool
help
Common setup code for SYSTEM MMU in EXYNOS4
config EXYNOS4_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config S5PV310_SETUP_I2C2
config EXYNOS4_SETUP_I2C2
bool
help
Common setup code for i2c bus 2.
config S5PV310_SETUP_I2C3
config EXYNOS4_SETUP_I2C3
bool
help
Common setup code for i2c bus 3.
config S5PV310_SETUP_I2C4
config EXYNOS4_SETUP_I2C4
bool
help
Common setup code for i2c bus 4.
config S5PV310_SETUP_I2C5
config EXYNOS4_SETUP_I2C5
bool
help
Common setup code for i2c bus 5.
config S5PV310_SETUP_I2C6
config EXYNOS4_SETUP_I2C6
bool
help
Common setup code for i2c bus 6.
config S5PV310_SETUP_I2C7
config EXYNOS4_SETUP_I2C7
bool
help
Common setup code for i2c bus 7.
config S5PV310_SETUP_SDHCI
config EXYNOS4_SETUP_KEYPAD
bool
select S5PV310_SETUP_SDHCI_GPIO
help
Internal helper functions for S5PV310 based SDHCI systems.
Common setup code for keypad.
config S5PV310_SETUP_SDHCI_GPIO
config EXYNOS4_SETUP_SDHCI
bool
select EXYNOS4_SETUP_SDHCI_GPIO
help
Internal helper functions for EXYNOS4 based SDHCI systems.
config EXYNOS4_SETUP_SDHCI_GPIO
bool
help
Common setup code for SDHCI gpio.
config S5PV310_DEV_SYSMMU
config EXYNOS4_SETUP_FIMC
bool
help
Common setup code for SYSTEM MMU in S5PV310
Common setup code for the camera interfaces.
# machine support
menu "S5PC210 Machines"
menu "EXYNOS4 Machines"
config MACH_SMDKC210
bool "SMDKC210"
select CPU_S5PV310
select CPU_EXYNOS4210
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
......@@ -85,48 +100,77 @@ config MACH_SMDKC210
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S5PV310_DEV_PD
select S5PV310_SETUP_I2C1
select S5PV310_SETUP_SDHCI
select S5PV310_DEV_SYSMMU
select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung SMDKC210
S5PC210(MCP) is one of package option of S5PV310
config MACH_SMDKV310
bool "SMDKV310"
select CPU_EXYNOS4210
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select SAMSUNG_DEV_KEYPAD
select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_KEYPAD
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung SMDKV310
config MACH_ARMLEX4210
bool "ARMLEX4210"
select CPU_EXYNOS4210
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_SDHCI
select SATA_AHCI_PLATFORM
help
Machine support for Samsung ARMLEX4210 based on EXYNOS4210
config MACH_UNIVERSAL_C210
bool "Mobile UNIVERSAL_C210 Board"
select CPU_S5PV310
select S5P_DEV_ONENAND
select CPU_EXYNOS4210
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S5PV310_SETUP_SDHCI
select S3C_DEV_I2C1
select S5PV310_SETUP_I2C1
select S3C_DEV_I2C5
select S5P_DEV_ONENAND
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung Mobile Universal S5PC210 Reference
Board. S5PC210(MCP) is one of package option of S5PV310
Board.
endmenu
menu "S5PV310 Machines"
config MACH_SMDKV310
bool "SMDKV310"
select CPU_S5PV310
select S3C_DEV_RTC
config MACH_NURI
bool "Mobile NURI Board"
select CPU_EXYNOS4210
select S3C_DEV_WDT
select S3C_DEV_I2C1
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S5PV310_DEV_PD
select S5PV310_DEV_SYSMMU
select S5PV310_SETUP_I2C1
select S5PV310_SETUP_SDHCI
select S3C_DEV_I2C1
select S3C_DEV_I2C5
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
select SAMSUNG_DEV_PWM
help
Machine support for Samsung SMDKV310
Machine support for Samsung Mobile NURI Board.
endmenu
......@@ -134,13 +178,13 @@ comment "Configuration for HSMMC bus width"
menu "Use 8-bit bus width"
config S5PV310_SDHCI_CH0_8BIT
config EXYNOS4_SDHCI_CH0_8BIT
bool "Channel 0 with 8-bit bus"
help
Support HSMMC Channel 0 8-bit bus.
If selected, Channel 1 is disabled.
config S5PV310_SDHCI_CH2_8BIT
config EXYNOS4_SDHCI_CH2_8BIT
bool "Channel 2 with 8-bit bus"
help
Support HSMMC Channel 2 8-bit bus.
......
# arch/arm/mach-exynos4/Makefile
#
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for EXYNOS4 system
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
ifeq ($(CONFIG_EXYNOS4_MCT),y)
obj-y += mct.o
else
obj-y += time.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
endif
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
# machine support
obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
obj-$(CONFIG_MACH_NURI) += mach-nuri.o
# device support
obj-y += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_SATA_AHCI_PLATFORM) += dev-ahci.o
/* linux/arch/arm/mach-s5pv310/cpu.c
/* linux/arch/arm/mach-exynos4/cpu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -19,8 +19,10 @@
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/s5pv310.h>
#include <plat/exynos4.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/fimc-core.h>
#include <mach/regs-irq.h>
......@@ -29,55 +31,60 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
/* Initial IO mappings */
static struct map_desc s5pv310_iodesc[] __initdata = {
static struct map_desc exynos4_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(S5PV310_PA_CMU),
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
.length = SZ_128K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_PMU,
.pfn = __phys_to_pfn(S5PV310_PA_PMU),
.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(S5PV310_PA_COMBINER),
.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
.pfn = __phys_to_pfn(S5PV310_PA_COREPERI),
.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_L2CC,
.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO1,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO2,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO2),
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO3,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO3),
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
.length = SZ_256,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_DMC0,
.pfn = __phys_to_pfn(S5PV310_PA_DMC0),
.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
......@@ -87,13 +94,13 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SROMC,
.pfn = __phys_to_pfn(S5PV310_PA_SROMC),
.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static void s5pv310_idle(void)
static void exynos4_idle(void)
{
if (!need_resched())
cpu_do_idle();
......@@ -101,32 +108,38 @@ static void s5pv310_idle(void)
local_irq_enable();
}
/* s5pv310_map_io
/*
* exynos4_map_io
*
* register the standard cpu IO areas
*/
void __init s5pv310_map_io(void)
*/
void __init exynos4_map_io(void)
{
iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
/* initialize device information early */
s5pv310_default_sdhci0();
s5pv310_default_sdhci1();
s5pv310_default_sdhci2();
s5pv310_default_sdhci3();
exynos4_default_sdhci0();
exynos4_default_sdhci1();
exynos4_default_sdhci2();
exynos4_default_sdhci3();
s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
}
void __init s5pv310_init_clocks(int xtal)
void __init exynos4_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5pv310_register_clocks();
s5pv310_setup_clocks();
exynos4_register_clocks();
exynos4_setup_clocks();
}
void __init s5pv310_init_irq(void)
void __init exynos4_init_irq(void)
{
int irq;
......@@ -148,29 +161,29 @@ void __init s5pv310_init_irq(void)
}
/* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because S5PV310
* Theses parameters should be NULL and 0 because EXYNOS4
* uses GIC instead of VIC.
*/
s5p_init_irq(NULL, 0);
}
struct sysdev_class s5pv310_sysclass = {
.name = "s5pv310-core",
struct sysdev_class exynos4_sysclass = {
.name = "exynos4-core",
};
static struct sys_device s5pv310_sysdev = {
.cls = &s5pv310_sysclass,
static struct sys_device exynos4_sysdev = {
.cls = &exynos4_sysclass,
};
static int __init s5pv310_core_init(void)
static int __init exynos4_core_init(void)
{
return sysdev_class_register(&s5pv310_sysclass);
return sysdev_class_register(&exynos4_sysclass);
}
core_initcall(s5pv310_core_init);
core_initcall(exynos4_core_init);
#ifdef CONFIG_CACHE_L2X0
static int __init s5pv310_l2x0_cache_init(void)
static int __init exynos4_l2x0_cache_init(void)
{
/* TAG, Data Latency Control: 2cycle */
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
......@@ -188,15 +201,15 @@ static int __init s5pv310_l2x0_cache_init(void)
return 0;
}
early_initcall(s5pv310_l2x0_cache_init);
early_initcall(exynos4_l2x0_cache_init);
#endif
int __init s5pv310_init(void)
int __init exynos4_init(void)
{
printk(KERN_INFO "S5PV310: Initializing architecture\n");
printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
/* set idle function */
pm_idle = s5pv310_idle;
pm_idle = exynos4_idle;
return sysdev_register(&s5pv310_sysdev);
return sysdev_register(&exynos4_sysdev);
}
/* linux/arch/arm/mach-s5pv310/cpufreq.c
/* linux/arch/arm/mach-exynos4/cpufreq.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - CPU frequency scaling support
* EXYNOS4 - CPU frequency scaling support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -31,15 +31,13 @@ static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;
#ifdef CONFIG_REGULATOR
static struct regulator *arm_regulator;
static struct regulator *int_regulator;
#endif
static struct cpufreq_freqs freqs;
static unsigned int memtype;
enum s5pv310_memory_type {
enum exynos4_memory_type {
DDR2 = 4,
LPDDR2,
DDR3,
......@@ -49,7 +47,7 @@ enum cpufreq_level_index {
L0, L1, L2, L3, CPUFREQ_LEVEL_END,
};
static struct cpufreq_frequency_table s5pv310_freq_table[] = {
static struct cpufreq_frequency_table exynos4_freq_table[] = {
{L0, 1000*1000},
{L1, 800*1000},
{L2, 400*1000},
......@@ -160,7 +158,7 @@ struct cpufreq_voltage_table {
unsigned int int_volt;
};
static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
{
.index = L0,
.arm_volt = 1200000,
......@@ -180,7 +178,7 @@ static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
},
};
static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
/* APLL FOUT L0: 1000MHz */
((250 << 16) | (6 << 8) | 1),
......@@ -194,17 +192,17 @@ static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
((200 << 16) | (6 << 8) | 4),
};
int s5pv310_verify_speed(struct cpufreq_policy *policy)
int exynos4_verify_speed(struct cpufreq_policy *policy)
{
return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
}
unsigned int s5pv310_getspeed(unsigned int cpu)
unsigned int exynos4_getspeed(unsigned int cpu)
{
return clk_get_rate(cpu_clk) / 1000;
}
void s5pv310_set_clkdiv(unsigned int div_index)
void exynos4_set_clkdiv(unsigned int div_index)
{
unsigned int tmp;
......@@ -321,7 +319,7 @@ void s5pv310_set_clkdiv(unsigned int div_index)
} while (tmp & 0x11);
}
static void s5pv310_set_apll(unsigned int index)
static void exynos4_set_apll(unsigned int index)
{
unsigned int tmp;
......@@ -340,7 +338,7 @@ static void s5pv310_set_apll(unsigned int index)
/* 3. Change PLL PMS values */
tmp = __raw_readl(S5P_APLL_CON0);
tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
tmp |= s5pv310_apll_pms_table[index];
tmp |= exynos4_apll_pms_table[index];
__raw_writel(tmp, S5P_APLL_CON0);
/* 4. wait_lock_time */
......@@ -357,99 +355,95 @@ static void s5pv310_set_apll(unsigned int index)
} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
}
static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
{
unsigned int tmp;
if (old_index > new_index) {
/* The frequency changing to L0 needs to change apll */
if (freqs.new == s5pv310_freq_table[L0].frequency) {
if (freqs.new == exynos4_freq_table[L0].frequency) {
/* 1. Change the system clock divider values */
s5pv310_set_clkdiv(new_index);
exynos4_set_clkdiv(new_index);
/* 2. Change the apll m,p,s value */
s5pv310_set_apll(new_index);
exynos4_set_apll(new_index);
} else {
/* 1. Change the system clock divider values */
s5pv310_set_clkdiv(new_index);
exynos4_set_clkdiv(new_index);
/* 2. Change just s value in apll m,p,s value */
tmp = __raw_readl(S5P_APLL_CON0);
tmp &= ~(0x7 << 0);
tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
__raw_writel(tmp, S5P_APLL_CON0);
}
}
else if (old_index < new_index) {
/* The frequency changing from L0 needs to change apll */
if (freqs.old == s5pv310_freq_table[L0].frequency) {
if (freqs.old == exynos4_freq_table[L0].frequency) {
/* 1. Change the apll m,p,s value */
s5pv310_set_apll(new_index);
exynos4_set_apll(new_index);
/* 2. Change the system clock divider values */
s5pv310_set_clkdiv(new_index);
exynos4_set_clkdiv(new_index);
} else {
/* 1. Change just s value in apll m,p,s value */
tmp = __raw_readl(S5P_APLL_CON0);
tmp &= ~(0x7 << 0);
tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
__raw_writel(tmp, S5P_APLL_CON0);
/* 2. Change the system clock divider values */
s5pv310_set_clkdiv(new_index);
exynos4_set_clkdiv(new_index);
}
}
}
static int s5pv310_target(struct cpufreq_policy *policy,
static int exynos4_target(struct cpufreq_policy *policy,
unsigned int target_freq,
unsigned int relation)
{
unsigned int index, old_index;
unsigned int arm_volt, int_volt;
freqs.old = s5pv310_getspeed(policy->cpu);
freqs.old = exynos4_getspeed(policy->cpu);
if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
freqs.old, relation, &old_index))
return -EINVAL;
if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
target_freq, relation, &index))
return -EINVAL;
freqs.new = s5pv310_freq_table[index].frequency;
freqs.new = exynos4_freq_table[index].frequency;
freqs.cpu = policy->cpu;
if (freqs.new == freqs.old)
return 0;
/* get the voltage value */
arm_volt = s5pv310_volt_table[index].arm_volt;
int_volt = s5pv310_volt_table[index].int_volt;
arm_volt = exynos4_volt_table[index].arm_volt;
int_volt = exynos4_volt_table[index].int_volt;
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
/* control regulator */
if (freqs.new > freqs.old) {
/* Voltage up */
#ifdef CONFIG_REGULATOR
regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
regulator_set_voltage(int_regulator, int_volt, int_volt);
#endif
}
/* Clock Configuration Procedure */
s5pv310_set_frequency(old_index, index);
exynos4_set_frequency(old_index, index);
/* control regulator */
if (freqs.new < freqs.old) {
/* Voltage down */
#ifdef CONFIG_REGULATOR
regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
regulator_set_voltage(int_regulator, int_volt, int_volt);
#endif
}
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
......@@ -458,51 +452,51 @@ static int s5pv310_target(struct cpufreq_policy *policy,
}
#ifdef CONFIG_PM
static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy)
static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
{
return 0;
}
static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
{
return 0;
}
#endif
static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
/* set the transition latency value */
policy->cpuinfo.transition_latency = 100000;
/*
* S5PV310 multi-core processors has 2 cores
* EXYNOS4 multi-core processors has 2 cores
* that the frequency cannot be set independently.
* Each cpu is bound to the same speed.
* So the affected cpu is all of the cpus.
*/
cpumask_setall(policy->cpus);
return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
}
static struct cpufreq_driver s5pv310_driver = {
static struct cpufreq_driver exynos4_driver = {
.flags = CPUFREQ_STICKY,
.verify = s5pv310_verify_speed,
.target = s5pv310_target,
.get = s5pv310_getspeed,
.init = s5pv310_cpufreq_cpu_init,
.name = "s5pv310_cpufreq",
.verify = exynos4_verify_speed,
.target = exynos4_target,
.get = exynos4_getspeed,
.init = exynos4_cpufreq_cpu_init,
.name = "exynos4_cpufreq",
#ifdef CONFIG_PM
.suspend = s5pv310_cpufreq_suspend,
.resume = s5pv310_cpufreq_resume,
.suspend = exynos4_cpufreq_suspend,
.resume = exynos4_cpufreq_resume,
#endif
};
static int __init s5pv310_cpufreq_init(void)
static int __init exynos4_cpufreq_init(void)
{
cpu_clk = clk_get(NULL, "armclk");
if (IS_ERR(cpu_clk))
......@@ -520,7 +514,6 @@ static int __init s5pv310_cpufreq_init(void)
if (IS_ERR(mout_apll))
goto out;
#ifdef CONFIG_REGULATOR
arm_regulator = regulator_get(NULL, "vdd_arm");
if (IS_ERR(arm_regulator)) {
printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
......@@ -532,7 +525,6 @@ static int __init s5pv310_cpufreq_init(void)
printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
goto out;
}
#endif
/*
* Check DRAM type.
......@@ -549,7 +541,7 @@ static int __init s5pv310_cpufreq_init(void)
printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
}
return cpufreq_register_driver(&s5pv310_driver);
return cpufreq_register_driver(&exynos4_driver);
out:
if (!IS_ERR(cpu_clk))
......@@ -564,16 +556,14 @@ static int __init s5pv310_cpufreq_init(void)
if (!IS_ERR(mout_apll))
clk_put(mout_apll);
#ifdef CONFIG_REGULATOR
if (!IS_ERR(arm_regulator))
regulator_put(arm_regulator);
if (!IS_ERR(int_regulator))
regulator_put(int_regulator);
#endif
printk(KERN_ERR "%s: failed initialization\n", __func__);
return -EINVAL;
}
late_initcall(s5pv310_cpufreq_init);
late_initcall(exynos4_cpufreq_init);
/* linux/arch/arm/mach-exynos4/dev-ahci.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - AHCI support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/ahci_platform.h>
#include <plat/cpu.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include <mach/regs-pmu.h>
/* PHY Control Register */
#define SATA_CTRL0 0x0
/* PHY Link Control Register */
#define SATA_CTRL1 0x4
/* PHY Status Register */
#define SATA_PHY_STATUS 0x8
#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27)
#define SATA_CTRL0_SPEED_MODE (1 << 26)
#define SATA_CTRL0_M_PHY_CAL (1 << 19)
#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10)
#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9)
#define SATA_CTRL0_PHY_POR_N (1 << 8)
#define SATA_CTRL1_RST_PMALIVE_N (1 << 8)
#define SATA_CTRL1_RST_RXOOB_N (1 << 7)
#define SATA_CTRL1_RST_RX_N (1 << 6)
#define SATA_CTRL1_RST_TX_N (1 << 5)
#define SATA_PHY_STATUS_CMU_OK (1 << 18)
#define SATA_PHY_STATUS_LANE_OK (1 << 16)
#define LANE0 0x200
#define COM_LANE 0xA00
#define HOST_PORTS_IMPL 0xC
#define SCLK_SATA_FREQ (67 * MHZ)
static void __iomem *phy_base, *phy_ctrl;
struct phy_reg {
u8 reg;
u8 val;
};
/* SATA PHY setup */
static const struct phy_reg exynos4_sataphy_cmu[] = {
{ 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
{ 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
{ 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
{ 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
{ 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
{ 0x6b, 0xc8 }, { 0x6c, 0x06 },
};
static const struct phy_reg exynos4_sataphy_lane[] = {
{ 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
{ 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
{ 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
{ 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
{ 0x51, 0x0f },
};
static const struct phy_reg exynos4_sataphy_comlane[] = {
{ 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
{ 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
{ 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
{ 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
{ 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
{ 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
{ 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
{ 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
{ 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
{ 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
{ 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
{ 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
{ 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
{ 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
};
static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
{
unsigned long timeout;
/* wait for maximum of 3 sec */
timeout = jiffies + msecs_to_jiffies(3000);
while (!(__raw_readl(reg) & bit)) {
if (time_after(jiffies, timeout))
return -1;
cpu_relax();
}
return 0;
}
static int ahci_phy_init(void __iomem *mmio)
{
int i, ctrl0;
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
__raw_writeb(exynos4_sataphy_cmu[i].val,
phy_base + (exynos4_sataphy_cmu[i].reg * 4));
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
__raw_writeb(exynos4_sataphy_lane[i].val,
phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
__raw_writeb(exynos4_sataphy_comlane[i].val,
phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
__raw_writeb(0x07, phy_base);
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
SATA_PHY_STATUS_CMU_OK) < 0) {
printk(KERN_ERR "PHY CMU not ready\n");
return -EBUSY;
}
__raw_writeb(0x03, phy_base + (COM_LANE * 4));
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
SATA_PHY_STATUS_LANE_OK) < 0) {
printk(KERN_ERR "PHY LANE not ready\n");
return -EBUSY;
}
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
ctrl0 |= SATA_CTRL0_M_PHY_CAL;
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
return 0;
}
static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
{
struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
int val, ret;
phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
if (!phy_base) {
dev_err(dev, "failed to allocate memory for SATA PHY\n");
return -ENOMEM;
}
phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
if (!phy_ctrl) {
dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
ret = -ENOMEM;
goto err1;
}
clk_sata = clk_get(dev, "sata");
if (IS_ERR(clk_sata)) {
dev_err(dev, "failed to get sata clock\n");
ret = PTR_ERR(clk_sata);
clk_sata = NULL;
goto err2;
}
clk_enable(clk_sata);
clk_sataphy = clk_get(dev, "sataphy");
if (IS_ERR(clk_sataphy)) {
dev_err(dev, "failed to get sataphy clock\n");
ret = PTR_ERR(clk_sataphy);
clk_sataphy = NULL;
goto err3;
}
clk_enable(clk_sataphy);
clk_sclk_sata = clk_get(dev, "sclk_sata");
if (IS_ERR(clk_sclk_sata)) {
dev_err(dev, "failed to get sclk_sata\n");
ret = PTR_ERR(clk_sclk_sata);
clk_sclk_sata = NULL;
goto err4;
}
clk_enable(clk_sclk_sata);
clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
__raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
/* Enable PHY link control */
val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
__raw_writel(val, phy_ctrl + SATA_CTRL1);
/* Set communication speed as 3Gbps and enable PHY power */
val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
SATA_CTRL0_PHY_POR_N;
__raw_writel(val, phy_ctrl + SATA_CTRL0);
/* Port0 is available */
__raw_writel(0x1, mmio + HOST_PORTS_IMPL);
return ahci_phy_init(mmio);
err4:
clk_disable(clk_sataphy);
clk_put(clk_sataphy);
err3:
clk_disable(clk_sata);
clk_put(clk_sata);
err2:
iounmap(phy_ctrl);
err1:
iounmap(phy_base);
return ret;
}
static struct ahci_platform_data exynos4_ahci_pdata = {
.init = exynos4_ahci_init,
};
static struct resource exynos4_ahci_resource[] = {
[0] = {
.start = EXYNOS4_PA_SATA,
.end = EXYNOS4_PA_SATA + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SATA,
.end = IRQ_SATA,
.flags = IORESOURCE_IRQ,
},
};
static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
struct platform_device exynos4_device_ahci = {
.name = "ahci",
.id = -1,
.resource = exynos4_ahci_resource,
.num_resources = ARRAY_SIZE(exynos4_ahci_resource),
.dev = {
.platform_data = &exynos4_ahci_pdata,
.dma_mask = &exynos4_ahci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
/* linux/arch/arm/mach-s5pv310/dev-audio.c
/* linux/arch/arm/mach-exynos4/dev-audio.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
......@@ -24,18 +27,18 @@ static const char *rclksrc[] = {
[1] = "i2sclk",
};
static int s5pv310_cfg_i2s(struct platform_device *pdev)
static int exynos4_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
break;
case 1:
s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
break;
case 2:
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4));
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
......@@ -46,7 +49,7 @@ static int s5pv310_cfg_i2s(struct platform_device *pdev)
}
static struct s3c_audio_pdata i2sv5_pdata = {
.cfg_gpio = s5pv310_cfg_i2s,
.cfg_gpio = exynos4_cfg_i2s,
.type = {
.i2s = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
......@@ -56,10 +59,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
},
};
static struct resource s5pv310_i2s0_resource[] = {
static struct resource exynos4_i2s0_resource[] = {
[0] = {
.start = S5PV310_PA_I2S0,
.end = S5PV310_PA_I2S0 + 0x100 - 1,
.start = EXYNOS4_PA_I2S0,
.end = EXYNOS4_PA_I2S0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -79,11 +82,11 @@ static struct resource s5pv310_i2s0_resource[] = {
},
};
struct platform_device s5pv310_device_i2s0 = {
struct platform_device exynos4_device_i2s0 = {
.name = "samsung-i2s",
.id = 0,
.num_resources = ARRAY_SIZE(s5pv310_i2s0_resource),
.resource = s5pv310_i2s0_resource,
.num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
.resource = exynos4_i2s0_resource,
.dev = {
.platform_data = &i2sv5_pdata,
},
......@@ -95,7 +98,7 @@ static const char *rclksrc_v3[] = {
};
static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = s5pv310_cfg_i2s,
.cfg_gpio = exynos4_cfg_i2s,
.type = {
.i2s = {
.quirks = QUIRK_NO_MUXPSR,
......@@ -104,10 +107,10 @@ static struct s3c_audio_pdata i2sv3_pdata = {
},
};
static struct resource s5pv310_i2s1_resource[] = {
static struct resource exynos4_i2s1_resource[] = {
[0] = {
.start = S5PV310_PA_I2S1,
.end = S5PV310_PA_I2S1 + 0x100 - 1,
.start = EXYNOS4_PA_I2S1,
.end = EXYNOS4_PA_I2S1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -122,20 +125,20 @@ static struct resource s5pv310_i2s1_resource[] = {
},
};
struct platform_device s5pv310_device_i2s1 = {
struct platform_device exynos4_device_i2s1 = {
.name = "samsung-i2s",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv310_i2s1_resource),
.resource = s5pv310_i2s1_resource,
.num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
.resource = exynos4_i2s1_resource,
.dev = {
.platform_data = &i2sv3_pdata,
},
};
static struct resource s5pv310_i2s2_resource[] = {
static struct resource exynos4_i2s2_resource[] = {
[0] = {
.start = S5PV310_PA_I2S2,
.end = S5PV310_PA_I2S2 + 0x100 - 1,
.start = EXYNOS4_PA_I2S2,
.end = EXYNOS4_PA_I2S2 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -150,11 +153,11 @@ static struct resource s5pv310_i2s2_resource[] = {
},
};
struct platform_device s5pv310_device_i2s2 = {
struct platform_device exynos4_device_i2s2 = {
.name = "samsung-i2s",
.id = 2,
.num_resources = ARRAY_SIZE(s5pv310_i2s2_resource),
.resource = s5pv310_i2s2_resource,
.num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
.resource = exynos4_i2s2_resource,
.dev = {
.platform_data = &i2sv3_pdata,
},
......@@ -162,17 +165,17 @@ struct platform_device s5pv310_device_i2s2 = {
/* PCM Controller platform_devices */
static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3));
s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
break;
case 1:
s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3));
s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
break;
case 2:
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3));
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
......@@ -183,13 +186,13 @@ static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5pv310_pcm_cfg_gpio,
.cfg_gpio = exynos4_pcm_cfg_gpio,
};
static struct resource s5pv310_pcm0_resource[] = {
static struct resource exynos4_pcm0_resource[] = {
[0] = {
.start = S5PV310_PA_PCM0,
.end = S5PV310_PA_PCM0 + 0x100 - 1,
.start = EXYNOS4_PA_PCM0,
.end = EXYNOS4_PA_PCM0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -204,20 +207,20 @@ static struct resource s5pv310_pcm0_resource[] = {
},
};
struct platform_device s5pv310_device_pcm0 = {
struct platform_device exynos4_device_pcm0 = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5pv310_pcm0_resource),
.resource = s5pv310_pcm0_resource,
.num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
.resource = exynos4_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5pv310_pcm1_resource[] = {
static struct resource exynos4_pcm1_resource[] = {
[0] = {
.start = S5PV310_PA_PCM1,
.end = S5PV310_PA_PCM1 + 0x100 - 1,
.start = EXYNOS4_PA_PCM1,
.end = EXYNOS4_PA_PCM1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -232,20 +235,20 @@ static struct resource s5pv310_pcm1_resource[] = {
},
};
struct platform_device s5pv310_device_pcm1 = {
struct platform_device exynos4_device_pcm1 = {
.name = "samsung-pcm",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv310_pcm1_resource),
.resource = s5pv310_pcm1_resource,
.num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
.resource = exynos4_pcm1_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5pv310_pcm2_resource[] = {
static struct resource exynos4_pcm2_resource[] = {
[0] = {
.start = S5PV310_PA_PCM2,
.end = S5PV310_PA_PCM2 + 0x100 - 1,
.start = EXYNOS4_PA_PCM2,
.end = EXYNOS4_PA_PCM2 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -260,11 +263,11 @@ static struct resource s5pv310_pcm2_resource[] = {
},
};
struct platform_device s5pv310_device_pcm2 = {
struct platform_device exynos4_device_pcm2 = {
.name = "samsung-pcm",
.id = 2,
.num_resources = ARRAY_SIZE(s5pv310_pcm2_resource),
.resource = s5pv310_pcm2_resource,
.num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
.resource = exynos4_pcm2_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
......@@ -272,15 +275,15 @@ struct platform_device s5pv310_device_pcm2 = {
/* AC97 Controller platform devices */
static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev)
static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
{
return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4));
return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
}
static struct resource s5pv310_ac97_resource[] = {
static struct resource exynos4_ac97_resource[] = {
[0] = {
.start = S5PV310_PA_AC97,
.end = S5PV310_PA_AC97 + 0x100 - 1,
.start = EXYNOS4_PA_AC97,
.end = EXYNOS4_PA_AC97 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -306,36 +309,36 @@ static struct resource s5pv310_ac97_resource[] = {
};
static struct s3c_audio_pdata s3c_ac97_pdata = {
.cfg_gpio = s5pv310_ac97_cfg_gpio,
.cfg_gpio = exynos4_ac97_cfg_gpio,
};
static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32);
static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
struct platform_device s5pv310_device_ac97 = {
struct platform_device exynos4_device_ac97 = {
.name = "samsung-ac97",
.id = -1,
.num_resources = ARRAY_SIZE(s5pv310_ac97_resource),
.resource = s5pv310_ac97_resource,
.num_resources = ARRAY_SIZE(exynos4_ac97_resource),
.resource = exynos4_ac97_resource,
.dev = {
.platform_data = &s3c_ac97_pdata,
.dma_mask = &s5pv310_ac97_dmamask,
.dma_mask = &exynos4_ac97_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
/* S/PDIF Controller platform_device */
static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev)
static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
{
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3));
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
return 0;
}
static struct resource s5pv310_spdif_resource[] = {
static struct resource exynos4_spdif_resource[] = {
[0] = {
.start = S5PV310_PA_SPDIF,
.end = S5PV310_PA_SPDIF + 0x100 - 1,
.start = EXYNOS4_PA_SPDIF,
.end = EXYNOS4_PA_SPDIF + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -346,19 +349,19 @@ static struct resource s5pv310_spdif_resource[] = {
};
static struct s3c_audio_pdata samsung_spdif_pdata = {
.cfg_gpio = s5pv310_spdif_cfg_gpio,
.cfg_gpio = exynos4_spdif_cfg_gpio,
};
static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32);
static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
struct platform_device s5pv310_device_spdif = {
struct platform_device exynos4_device_spdif = {
.name = "samsung-spdif",
.id = -1,
.num_resources = ARRAY_SIZE(s5pv310_spdif_resource),
.resource = s5pv310_spdif_resource,
.num_resources = ARRAY_SIZE(exynos4_spdif_resource),
.resource = exynos4_spdif_resource,
.dev = {
.platform_data = &samsung_spdif_pdata,
.dma_mask = &s5pv310_spdif_dmamask,
.dma_mask = &exynos4_spdif_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
/* linux/arch/arm/mach-s5pv310/dev-pd.c
/* linux/arch/arm/mach-exynos4/dev-pd.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Power Domain support
* EXYNOS4 - Power Domain support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -19,7 +19,7 @@
#include <plat/pd.h>
static int s5pv310_pd_enable(struct device *dev)
static int exynos4_pd_enable(struct device *dev)
{
struct samsung_pd_info *pdata = dev->platform_data;
u32 timeout;
......@@ -42,7 +42,7 @@ static int s5pv310_pd_enable(struct device *dev)
return 0;
}
static int s5pv310_pd_disable(struct device *dev)
static int exynos4_pd_disable(struct device *dev)
{
struct samsung_pd_info *pdata = dev->platform_data;
u32 timeout;
......@@ -64,14 +64,14 @@ static int s5pv310_pd_disable(struct device *dev)
return 0;
}
struct platform_device s5pv310_device_pd[] = {
struct platform_device exynos4_device_pd[] = {
{
.name = "samsung-pd",
.id = 0,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_MFC_CONF,
},
},
......@@ -80,8 +80,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 1,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_G3D_CONF,
},
},
......@@ -90,8 +90,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 2,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_LCD0_CONF,
},
},
......@@ -100,8 +100,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 3,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_LCD1_CONF,
},
},
......@@ -110,8 +110,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 4,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_TV_CONF,
},
},
......@@ -120,8 +120,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 5,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_CAM_CONF,
},
},
......@@ -130,8 +130,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 6,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_GPS_CONF,
},
},
......
/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c
/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - System MMU support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
......@@ -13,11 +15,33 @@
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/sysmmu.h>
#include <plat/s5p-clock.h>
/* These names must be equal to the clock names in mach-exynos4/clock.c */
const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
"SYSMMU_MDMA" ,
"SYSMMU_SSS" ,
"SYSMMU_FIMC0" ,
"SYSMMU_FIMC1" ,
"SYSMMU_FIMC2" ,
"SYSMMU_FIMC3" ,
"SYSMMU_JPEG" ,
"SYSMMU_FIMD0" ,
"SYSMMU_FIMD1" ,
"SYSMMU_PCIe" ,
"SYSMMU_G2D" ,
"SYSMMU_ROTATOR",
"SYSMMU_MDMA2" ,
"SYSMMU_TV" ,
"SYSMMU_MFC_L" ,
"SYSMMU_MFC_R" ,
};
static struct resource s5pv310_sysmmu_resource[] = {
static struct resource exynos4_sysmmu_resource[] = {
[0] = {
.start = S5PV310_PA_SYSMMU_MDMA,
.end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_MDMA,
.end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -26,8 +50,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = S5PV310_PA_SYSMMU_SSS,
.end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_SSS,
.end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[3] = {
......@@ -36,8 +60,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[4] = {
.start = S5PV310_PA_SYSMMU_FIMC0,
.end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMC0,
.end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[5] = {
......@@ -46,8 +70,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[6] = {
.start = S5PV310_PA_SYSMMU_FIMC1,
.end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMC1,
.end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[7] = {
......@@ -56,8 +80,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[8] = {
.start = S5PV310_PA_SYSMMU_FIMC2,
.end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMC2,
.end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[9] = {
......@@ -66,8 +90,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[10] = {
.start = S5PV310_PA_SYSMMU_FIMC3,
.end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMC3,
.end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[11] = {
......@@ -76,8 +100,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[12] = {
.start = S5PV310_PA_SYSMMU_JPEG,
.end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_JPEG,
.end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[13] = {
......@@ -86,8 +110,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[14] = {
.start = S5PV310_PA_SYSMMU_FIMD0,
.end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMD0,
.end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[15] = {
......@@ -96,8 +120,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[16] = {
.start = S5PV310_PA_SYSMMU_FIMD1,
.end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMD1,
.end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[17] = {
......@@ -106,8 +130,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[18] = {
.start = S5PV310_PA_SYSMMU_PCIe,
.end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_PCIe,
.end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[19] = {
......@@ -116,8 +140,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[20] = {
.start = S5PV310_PA_SYSMMU_G2D,
.end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_G2D,
.end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[21] = {
......@@ -126,8 +150,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[22] = {
.start = S5PV310_PA_SYSMMU_ROTATOR,
.end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_ROTATOR,
.end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[23] = {
......@@ -136,8 +160,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[24] = {
.start = S5PV310_PA_SYSMMU_MDMA2,
.end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_MDMA2,
.end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[25] = {
......@@ -146,8 +170,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[26] = {
.start = S5PV310_PA_SYSMMU_TV,
.end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_TV,
.end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[27] = {
......@@ -156,8 +180,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[28] = {
.start = S5PV310_PA_SYSMMU_MFC_L,
.end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_MFC_L,
.end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[29] = {
......@@ -166,8 +190,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[30] = {
.start = S5PV310_PA_SYSMMU_MFC_R,
.end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_MFC_R,
.end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[31] = {
......@@ -177,11 +201,32 @@ static struct resource s5pv310_sysmmu_resource[] = {
},
};
struct platform_device s5pv310_device_sysmmu = {
struct platform_device exynos4_device_sysmmu = {
.name = "s5p-sysmmu",
.id = 32,
.num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource),
.resource = s5pv310_sysmmu_resource,
.num_resources = ARRAY_SIZE(exynos4_sysmmu_resource),
.resource = exynos4_sysmmu_resource,
};
EXPORT_SYMBOL(exynos4_device_sysmmu);
static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
{
sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
if (IS_ERR(sysmmu_clk[ips]))
sysmmu_clk[ips] = NULL;
else
clk_put(sysmmu_clk[ips]);
}
void sysmmu_clk_enable(sysmmu_ips ips)
{
if (sysmmu_clk[ips])
clk_enable(sysmmu_clk[ips]);
}
EXPORT_SYMBOL(s5pv310_device_sysmmu);
void sysmmu_clk_disable(sysmmu_ips ips)
{
if (sysmmu_clk[ips])
clk_disable(sysmmu_clk[ips]);
}
/*
/* linux/arch/arm/mach-exynos4/dma.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
......@@ -30,10 +34,10 @@
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5pv310_pdma0_resource[] = {
static struct resource exynos4_pdma0_resource[] = {
[0] = {
.start = S5PV310_PA_PDMA0,
.end = S5PV310_PA_PDMA0 + SZ_4K,
.start = EXYNOS4_PA_PDMA0,
.end = EXYNOS4_PA_PDMA0 + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -43,7 +47,7 @@ static struct resource s5pv310_pdma0_resource[] = {
},
};
static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
.peri = {
[0] = DMACH_PCM0_RX,
[1] = DMACH_PCM0_TX,
......@@ -80,22 +84,22 @@ static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
},
};
static struct platform_device s5pv310_device_pdma0 = {
static struct platform_device exynos4_device_pdma0 = {
.name = "s3c-pl330",
.id = 0,
.num_resources = ARRAY_SIZE(s5pv310_pdma0_resource),
.resource = s5pv310_pdma0_resource,
.num_resources = ARRAY_SIZE(exynos4_pdma0_resource),
.resource = exynos4_pdma0_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv310_pdma0_pdata,
.platform_data = &exynos4_pdma0_pdata,
},
};
static struct resource s5pv310_pdma1_resource[] = {
static struct resource exynos4_pdma1_resource[] = {
[0] = {
.start = S5PV310_PA_PDMA1,
.end = S5PV310_PA_PDMA1 + SZ_4K,
.start = EXYNOS4_PA_PDMA1,
.end = EXYNOS4_PA_PDMA1 + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -105,7 +109,7 @@ static struct resource s5pv310_pdma1_resource[] = {
},
};
static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
.peri = {
[0] = DMACH_PCM0_RX,
[1] = DMACH_PCM0_TX,
......@@ -142,27 +146,27 @@ static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
},
};
static struct platform_device s5pv310_device_pdma1 = {
static struct platform_device exynos4_device_pdma1 = {
.name = "s3c-pl330",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv310_pdma1_resource),
.resource = s5pv310_pdma1_resource,
.num_resources = ARRAY_SIZE(exynos4_pdma1_resource),
.resource = exynos4_pdma1_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv310_pdma1_pdata,
.platform_data = &exynos4_pdma1_pdata,
},
};
static struct platform_device *s5pv310_dmacs[] __initdata = {
&s5pv310_device_pdma0,
&s5pv310_device_pdma1,
static struct platform_device *exynos4_dmacs[] __initdata = {
&exynos4_device_pdma0,
&exynos4_device_pdma1,
};
static int __init s5pv310_dma_init(void)
static int __init exynos4_dma_init(void)
{
platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs));
platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
return 0;
}
arch_initcall(s5pv310_dma_init);
arch_initcall(exynos4_dma_init);
/* linux/arch/arm/mach-s5pv310/gpiolib.c
/* linux/arch/arm/mach-exynos4/gpiolib.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - GPIOlib support
* EXYNOS4 - GPIOlib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -43,168 +43,217 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
* Note: The initialization of 'base' member of s3c_gpio_chip structure
* uses the above macro and depends on the banks being listed in order here.
*/
static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
{
.chip = {
.base = S5PV310_GPA0(0),
.ngpio = S5PV310_GPIO_A0_NR,
.base = EXYNOS4_GPA0(0),
.ngpio = EXYNOS4_GPIO_A0_NR,
.label = "GPA0",
},
}, {
.chip = {
.base = S5PV310_GPA1(0),
.ngpio = S5PV310_GPIO_A1_NR,
.base = EXYNOS4_GPA1(0),
.ngpio = EXYNOS4_GPIO_A1_NR,
.label = "GPA1",
},
}, {
.chip = {
.base = S5PV310_GPB(0),
.ngpio = S5PV310_GPIO_B_NR,
.base = EXYNOS4_GPB(0),
.ngpio = EXYNOS4_GPIO_B_NR,
.label = "GPB",
},
}, {
.chip = {
.base = S5PV310_GPC0(0),
.ngpio = S5PV310_GPIO_C0_NR,
.base = EXYNOS4_GPC0(0),
.ngpio = EXYNOS4_GPIO_C0_NR,
.label = "GPC0",
},
}, {
.chip = {
.base = S5PV310_GPC1(0),
.ngpio = S5PV310_GPIO_C1_NR,
.base = EXYNOS4_GPC1(0),
.ngpio = EXYNOS4_GPIO_C1_NR,
.label = "GPC1",
},
}, {
.chip = {
.base = S5PV310_GPD0(0),
.ngpio = S5PV310_GPIO_D0_NR,
.base = EXYNOS4_GPD0(0),
.ngpio = EXYNOS4_GPIO_D0_NR,
.label = "GPD0",
},
}, {
.chip = {
.base = S5PV310_GPD1(0),
.ngpio = S5PV310_GPIO_D1_NR,
.base = EXYNOS4_GPD1(0),
.ngpio = EXYNOS4_GPIO_D1_NR,
.label = "GPD1",
},
}, {
.chip = {
.base = S5PV310_GPE0(0),
.ngpio = S5PV310_GPIO_E0_NR,
.base = EXYNOS4_GPE0(0),
.ngpio = EXYNOS4_GPIO_E0_NR,
.label = "GPE0",
},
}, {
.chip = {
.base = S5PV310_GPE1(0),
.ngpio = S5PV310_GPIO_E1_NR,
.base = EXYNOS4_GPE1(0),
.ngpio = EXYNOS4_GPIO_E1_NR,
.label = "GPE1",
},
}, {
.chip = {
.base = S5PV310_GPE2(0),
.ngpio = S5PV310_GPIO_E2_NR,
.base = EXYNOS4_GPE2(0),
.ngpio = EXYNOS4_GPIO_E2_NR,
.label = "GPE2",
},
}, {
.chip = {
.base = S5PV310_GPE3(0),
.ngpio = S5PV310_GPIO_E3_NR,
.base = EXYNOS4_GPE3(0),
.ngpio = EXYNOS4_GPIO_E3_NR,
.label = "GPE3",
},
}, {
.chip = {
.base = S5PV310_GPE4(0),
.ngpio = S5PV310_GPIO_E4_NR,
.base = EXYNOS4_GPE4(0),
.ngpio = EXYNOS4_GPIO_E4_NR,
.label = "GPE4",
},
}, {
.chip = {
.base = S5PV310_GPF0(0),
.ngpio = S5PV310_GPIO_F0_NR,
.base = EXYNOS4_GPF0(0),
.ngpio = EXYNOS4_GPIO_F0_NR,
.label = "GPF0",
},
}, {
.chip = {
.base = S5PV310_GPF1(0),
.ngpio = S5PV310_GPIO_F1_NR,
.base = EXYNOS4_GPF1(0),
.ngpio = EXYNOS4_GPIO_F1_NR,
.label = "GPF1",
},
}, {
.chip = {
.base = S5PV310_GPF2(0),
.ngpio = S5PV310_GPIO_F2_NR,
.base = EXYNOS4_GPF2(0),
.ngpio = EXYNOS4_GPIO_F2_NR,
.label = "GPF2",
},
}, {
.chip = {
.base = S5PV310_GPF3(0),
.ngpio = S5PV310_GPIO_F3_NR,
.base = EXYNOS4_GPF3(0),
.ngpio = EXYNOS4_GPIO_F3_NR,
.label = "GPF3",
},
},
};
static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
{
.chip = {
.base = S5PV310_GPJ0(0),
.ngpio = S5PV310_GPIO_J0_NR,
.base = EXYNOS4_GPJ0(0),
.ngpio = EXYNOS4_GPIO_J0_NR,
.label = "GPJ0",
},
}, {
.chip = {
.base = S5PV310_GPJ1(0),
.ngpio = S5PV310_GPIO_J1_NR,
.base = EXYNOS4_GPJ1(0),
.ngpio = EXYNOS4_GPIO_J1_NR,
.label = "GPJ1",
},
}, {
.chip = {
.base = S5PV310_GPK0(0),
.ngpio = S5PV310_GPIO_K0_NR,
.base = EXYNOS4_GPK0(0),
.ngpio = EXYNOS4_GPIO_K0_NR,
.label = "GPK0",
},
}, {
.chip = {
.base = S5PV310_GPK1(0),
.ngpio = S5PV310_GPIO_K1_NR,
.base = EXYNOS4_GPK1(0),
.ngpio = EXYNOS4_GPIO_K1_NR,
.label = "GPK1",
},
}, {
.chip = {
.base = S5PV310_GPK2(0),
.ngpio = S5PV310_GPIO_K2_NR,
.base = EXYNOS4_GPK2(0),
.ngpio = EXYNOS4_GPIO_K2_NR,
.label = "GPK2",
},
}, {
.chip = {
.base = S5PV310_GPK3(0),
.ngpio = S5PV310_GPIO_K3_NR,
.base = EXYNOS4_GPK3(0),
.ngpio = EXYNOS4_GPIO_K3_NR,
.label = "GPK3",
},
}, {
.chip = {
.base = S5PV310_GPL0(0),
.ngpio = S5PV310_GPIO_L0_NR,
.base = EXYNOS4_GPL0(0),
.ngpio = EXYNOS4_GPIO_L0_NR,
.label = "GPL0",
},
}, {
.chip = {
.base = S5PV310_GPL1(0),
.ngpio = S5PV310_GPIO_L1_NR,
.base = EXYNOS4_GPL1(0),
.ngpio = EXYNOS4_GPIO_L1_NR,
.label = "GPL1",
},
}, {
.chip = {
.base = S5PV310_GPL2(0),
.ngpio = S5PV310_GPIO_L2_NR,
.base = EXYNOS4_GPL2(0),
.ngpio = EXYNOS4_GPIO_L2_NR,
.label = "GPL2",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY0(0),
.ngpio = EXYNOS4_GPIO_Y0_NR,
.label = "GPY0",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY1(0),
.ngpio = EXYNOS4_GPIO_Y1_NR,
.label = "GPY1",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY2(0),
.ngpio = EXYNOS4_GPIO_Y2_NR,
.label = "GPY2",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY3(0),
.ngpio = EXYNOS4_GPIO_Y3_NR,
.label = "GPY3",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY4(0),
.ngpio = EXYNOS4_GPIO_Y4_NR,
.label = "GPY4",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY5(0),
.ngpio = EXYNOS4_GPIO_Y5_NR,
.label = "GPY5",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = EXYNOS4_GPY6(0),
.ngpio = EXYNOS4_GPIO_Y6_NR,
.label = "GPY6",
},
}, {
.base = (S5P_VA_GPIO2 + 0xC00),
.config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(0),
.chip = {
.base = S5PV310_GPX0(0),
.ngpio = S5PV310_GPIO_X0_NR,
.base = EXYNOS4_GPX0(0),
.ngpio = EXYNOS4_GPIO_X0_NR,
.label = "GPX0",
.to_irq = samsung_gpiolib_to_irq,
},
......@@ -213,8 +262,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
.config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(8),
.chip = {
.base = S5PV310_GPX1(0),
.ngpio = S5PV310_GPIO_X1_NR,
.base = EXYNOS4_GPX1(0),
.ngpio = EXYNOS4_GPIO_X1_NR,
.label = "GPX1",
.to_irq = samsung_gpiolib_to_irq,
},
......@@ -223,8 +272,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
.config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(16),
.chip = {
.base = S5PV310_GPX2(0),
.ngpio = S5PV310_GPIO_X2_NR,
.base = EXYNOS4_GPX2(0),
.ngpio = EXYNOS4_GPIO_X2_NR,
.label = "GPX2",
.to_irq = samsung_gpiolib_to_irq,
},
......@@ -233,72 +282,84 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
.config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(24),
.chip = {
.base = S5PV310_GPX3(0),
.ngpio = S5PV310_GPIO_X3_NR,
.base = EXYNOS4_GPX3(0),
.ngpio = EXYNOS4_GPIO_X3_NR,
.label = "GPX3",
.to_irq = samsung_gpiolib_to_irq,
},
},
};
static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {
static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
{
.chip = {
.base = S5PV310_GPZ(0),
.ngpio = S5PV310_GPIO_Z_NR,
.base = EXYNOS4_GPZ(0),
.ngpio = EXYNOS4_GPIO_Z_NR,
.label = "GPZ",
},
},
};
static __init int s5pv310_gpiolib_init(void)
static __init int exynos4_gpiolib_init(void)
{
struct s3c_gpio_chip *chip;
int i;
int group = 0;
int nr_chips;
/* GPIO part 1 */
chip = s5pv310_gpio_part1_4bit;
nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);
chip = exynos4_gpio_part1_4bit;
nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
for (i = 0; i < nr_chips; i++, chip++) {
if (chip->config == NULL)
if (chip->config == NULL) {
chip->config = &gpio_cfg;
/* Assign the GPIO interrupt group */
chip->group = group++;
}
if (chip->base == NULL)
chip->base = S5P_VA_GPIO1 + (i) * 0x20;
}
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);
samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
/* GPIO part 2 */
chip = s5pv310_gpio_part2_4bit;
nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);
chip = exynos4_gpio_part2_4bit;
nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
for (i = 0; i < nr_chips; i++, chip++) {
if (chip->config == NULL)
if (chip->config == NULL) {
chip->config = &gpio_cfg;
/* Assign the GPIO interrupt group */
chip->group = group++;
}
if (chip->base == NULL)
chip->base = S5P_VA_GPIO2 + (i) * 0x20;
}
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);
samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
/* GPIO part 3 */
chip = s5pv310_gpio_part3_4bit;
nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);
chip = exynos4_gpio_part3_4bit;
nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
for (i = 0; i < nr_chips; i++, chip++) {
if (chip->config == NULL)
if (chip->config == NULL) {
chip->config = &gpio_cfg;
/* Assign the GPIO interrupt group */
chip->group = group++;
}
if (chip->base == NULL)
chip->base = S5P_VA_GPIO3 + (i) * 0x20;
}
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);
samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
return 0;
}
core_initcall(s5pv310_gpiolib_init);
core_initcall(exynos4_gpiolib_init);
/*
* linux/arch/arm/mach-s5pv310/headsmp.S
* linux/arch/arm/mach-exynos4/headsmp.S
*
* Cloned from linux/arch/arm/mach-realview/headsmp.S
*
......@@ -16,11 +16,11 @@
__INIT
/*
* s5pv310 specific entry point for secondary CPUs. This provides
* exynos4 specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
* ready for them to initialise.
*/
ENTRY(s5pv310_secondary_startup)
ENTRY(exynos4_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f
......
/* linux arch/arm/mach-s5pv310/hotplug.c
/* linux arch/arm/mach-exynos4/hotplug.c
*
* Cloned from linux/arch/arm/mach-realview/hotplug.c
*
......@@ -30,13 +30,13 @@ static inline void cpu_enter_lowpower(void)
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, #0x20\n"
" bic %0, %0, %3\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0), "Ir" (CR_C)
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
: "cc");
}
......@@ -49,10 +49,10 @@ static inline void cpu_leave_lowpower(void)
" orr %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 0\n"
" mrc p15, 0, %0, c1, c0, 1\n"
" orr %0, %0, #0x20\n"
" orr %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 1\n"
: "=&r" (v)
: "Ir" (CR_C)
: "Ir" (CR_C), "Ir" (0x40)
: "cc");
}
......
/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S
/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
*
......
/* arch/arm/mach-s5pv310/include/mach/entry-macro.S
/* arch/arm/mach-exynos4/include/mach/entry-macro.S
*
* Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for S5PV310 platforms
* Low-level IRQ helper macros for EXYNOS4 platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
......
This diff is collapsed.
/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h
/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Hardware support
* EXYNOS4 - Hardware support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......
/* linux/arch/arm/mach-s5pv310/include/mach/io.h
/* linux/arch/arm/mach-exynos4/include/mach/io.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
*
* Based on arch/arm/mach-s5p6442/include/mach/io.h
*
* Default IO routines for S5PV310
* Default IO routines for EXYNOS4
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......
This diff is collapsed.
/* linux/arch/arm/mach-s5pv310/include/mach/memory.h
/* linux/arch/arm/mach-exynos4/include/mach/memory.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Memory definitions
* EXYNOS4 - Memory definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......
This diff is collapsed.
/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......@@ -10,7 +10,7 @@
*
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
*
* S5PV310 - pwm clock and timer support
* EXYNOS4 - pwm clock and timer support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment