Commit 41218847 authored by Allen-KH Cheng's avatar Allen-KH Cheng Committed by Matthias Brugger

arm64: dts: mediatek: mt8186: Add GCE node

Add the Global Command Engine (GCE) node for MT8186 SoC
Signed-off-by: default avatarAllen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230324021258.15863-6-allen-kh.cheng@mediatek.comSigned-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 4dad4f32
...@@ -5,6 +5,7 @@ ...@@ -5,6 +5,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include <dt-bindings/clock/mt8186-clk.h> #include <dt-bindings/clock/mt8186-clk.h>
#include <dt-bindings/gce/mt8186-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8186-memory-port.h> #include <dt-bindings/memory/mt8186-memory-port.h>
...@@ -626,6 +627,15 @@ systimer: timer@10017000 { ...@@ -626,6 +627,15 @@ systimer: timer@10017000 {
clocks = <&clk13m>; clocks = <&clk13m>;
}; };
gce: mailbox@1022c000 {
compatible = "mediatek,mt8186-gce";
reg = <0 0X1022c000 0 0x4000>;
clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
clock-names = "gce";
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <2>;
};
scp: scp@10500000 { scp: scp@10500000 {
compatible = "mediatek,mt8186-scp"; compatible = "mediatek,mt8186-scp";
reg = <0 0x10500000 0 0x40000>, reg = <0 0x10500000 0 0x40000>,
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment