Commit 41f0e4d0 authored by David Daney's avatar David Daney Committed by Ralf Baechle

MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.

Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.
Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 95affdda
...@@ -147,6 +147,10 @@ ...@@ -147,6 +147,10 @@
#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips64r1 | cpu_has_mips64r2) cpu_has_mips64r1 | cpu_has_mips64r2)
#ifndef cpu_has_mips_r2_exec_hazard
#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
#endif
/* /*
* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
* pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
......
...@@ -259,6 +259,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, ...@@ -259,6 +259,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
} }
if (cpu_has_mips_r2) { if (cpu_has_mips_r2) {
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(p); uasm_i_ehb(p);
tlbw(p); tlbw(p);
return; return;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment