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Commit 41f91315 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
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drm/amd/display: Query DMCUB for dp alt status 

[Why]
To avoid hanging RDPCSPIPE when INTERCEPTB isn't set.

DMCUB owns control of that bit so DMCUB should manage returning the
information driver needs for link encoder control.

[How]
Add a new DMCUB command to return dp alt disable and dp4 information.
Reviewed-by: default avatarHansen Dsouza <hansen.dsouza@amd.com>
Acked-by: default avatarPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 32b119c8
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Inline Side-by-side
Showing with 88 additions and 38 deletions
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
View file @ 41f91315
...@@ -67,6 +67,39 @@ ...@@ -67,6 +67,39 @@
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
#endif #endif
static uint8_t phy_id_from_transmitter(enum transmitter t)
{
uint8_t phy_id;
switch (t) {
case TRANSMITTER_UNIPHY_A:
phy_id = 0;
break;
case TRANSMITTER_UNIPHY_B:
phy_id = 1;
break;
case TRANSMITTER_UNIPHY_C:
phy_id = 2;
break;
case TRANSMITTER_UNIPHY_D:
phy_id = 3;
break;
case TRANSMITTER_UNIPHY_E:
phy_id = 4;
break;
case TRANSMITTER_UNIPHY_F:
phy_id = 5;
break;
case TRANSMITTER_UNIPHY_G:
phy_id = 6;
break;
default:
phy_id = 0;
break;
}
return phy_id;
}
void dcn31_link_encoder_set_dio_phy_mux( void dcn31_link_encoder_set_dio_phy_mux(
struct link_encoder *enc, struct link_encoder *enc,
enum encoder_type_select sel, enum encoder_type_select sel,
...@@ -536,57 +569,45 @@ void dcn31_link_encoder_disable_output( ...@@ -536,57 +569,45 @@ void dcn31_link_encoder_disable_output(
bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc) bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
{ {
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
uint32_t dp_alt_mode_disable; struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;
union dmub_rb_cmd cmd;
bool is_usb_c_alt_mode = false; bool is_usb_c_alt_mode = false;
if (enc->features.flags.bits.DP_IS_USB_C) { if (enc->features.flags.bits.DP_IS_USB_C && dc_dmub_srv) {
if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) { memset(&cmd, 0, sizeof(cmd));
// [Note] no need to check hw_internal_rev once phy mux selection is ready cmd.query_dp_alt.header.type = DMUB_CMD__VBIOS;
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); cmd.query_dp_alt.header.sub_type = DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT;
} else { cmd.query_dp_alt.header.payload_bytes = sizeof(cmd.panel_cntl.data);
/* cmd.query_dp_alt.data.phy_id = phy_id_from_transmitter(enc10->base.transmitter);
* B0 phys use a new set of registers to check whether alt mode is disabled.
* if value == 1 alt mode is disabled, otherwise it is enabled.
*/
if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
} else {
// [Note] need to change TRANSMITTER_UNIPHY_C/D to F/G once phy mux selection is ready
REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
}
}
is_usb_c_alt_mode = (dp_alt_mode_disable == 0); if (!dc_dmub_srv_cmd_with_reply_data(dc_dmub_srv, &cmd))
return false;
is_usb_c_alt_mode = (cmd.query_dp_alt.data.is_dp_alt_disable == 0);
} }
return is_usb_c_alt_mode; return is_usb_c_alt_mode;
} }
void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc, void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc, struct dc_link_settings *link_settings)
struct dc_link_settings *link_settings)
{ {
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
uint32_t is_in_usb_c_dp4_mode = 0; struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;
union dmub_rb_cmd cmd;
dcn10_link_encoder_get_max_link_cap(enc, link_settings); dcn10_link_encoder_get_max_link_cap(enc, link_settings);
/* in usb c dp2 mode, max lane count is 2 */ if (enc->features.flags.bits.DP_IS_USB_C && dc_dmub_srv) {
if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) { memset(&cmd, 0, sizeof(cmd));
if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) { cmd.query_dp_alt.header.type = DMUB_CMD__VBIOS;
// [Note] no need to check hw_internal_rev once phy mux selection is ready cmd.query_dp_alt.header.sub_type = DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT;
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); cmd.query_dp_alt.header.payload_bytes = sizeof(cmd.panel_cntl.data);
} else { cmd.query_dp_alt.data.phy_id = phy_id_from_transmitter(enc10->base.transmitter);
if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_B) if (!dc_dmub_srv_cmd_with_reply_data(dc_dmub_srv, &cmd))
|| (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) { return;
REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
} else { if (cmd.query_dp_alt.data.is_usb && cmd.query_dp_alt.data.is_dp4 == 0)
REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
}
}
if (!is_in_usb_c_dp4_mode)
link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
} }
} }
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
View file @ 41f91315
...@@ -408,7 +408,14 @@ enum dmub_cmd_vbios_type { ...@@ -408,7 +408,14 @@ enum dmub_cmd_vbios_type {
* Enables or disables power gating. * Enables or disables power gating.
*/ */
DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
/**
* Controls embedded panels.
*/
DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
/**
* Query DP alt status on a transmitter.
*/
DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
}; };
//============================================================================== //==============================================================================
...@@ -2393,6 +2400,24 @@ struct dmub_rb_cmd_lvtma_control { ...@@ -2393,6 +2400,24 @@ struct dmub_rb_cmd_lvtma_control {
struct dmub_cmd_lvtma_control_data data; struct dmub_cmd_lvtma_control_data data;
}; };
/**
* Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
*/
struct dmub_rb_cmd_transmitter_query_dp_alt_data {
uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
uint8_t is_usb; /**< is phy is usb */
uint8_t is_dp_alt_disable; /**< is dp alt disable */
uint8_t is_dp4; /**< is dp in 4 lane */
};
/**
* Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
*/
struct dmub_rb_cmd_transmitter_query_dp_alt {
struct dmub_cmd_header header; /**< header */
struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
};
/** /**
* Maximum number of bytes a chunk sent to DMUB for parsing * Maximum number of bytes a chunk sent to DMUB for parsing
*/ */
...@@ -2600,6 +2625,10 @@ union dmub_rb_cmd { ...@@ -2600,6 +2625,10 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
*/ */
struct dmub_rb_cmd_lvtma_control lvtma_control; struct dmub_rb_cmd_lvtma_control lvtma_control;
/**
* Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
*/
struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
/** /**
* Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
*/ */
......
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