Commit 42a6e20e authored by Seungwhan Youn's avatar Seungwhan Youn Committed by Kukjin Kim

ARM: S5PV210: Fix wrong EPLL rate getting on setup clocks

This patch fix wrong EPLL getting on setup clocks on S5PV210.
Signed-off-by: default avatarSeungwhan Youn <sw.youn@samsung.com>
Acked-by: default avatarJassi Brar <jassi.brar@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent d4b34c6c
...@@ -1082,7 +1082,8 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) ...@@ -1082,7 +1082,8 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
__raw_readl(S5P_EPLL_CON1), pll_4600);
vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#define S5P_APLL_CON S5P_CLKREG(0x100) #define S5P_APLL_CON S5P_CLKREG(0x100)
#define S5P_MPLL_CON S5P_CLKREG(0x108) #define S5P_MPLL_CON S5P_CLKREG(0x108)
#define S5P_EPLL_CON S5P_CLKREG(0x110) #define S5P_EPLL_CON S5P_CLKREG(0x110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x114)
#define S5P_VPLL_CON S5P_CLKREG(0x120) #define S5P_VPLL_CON S5P_CLKREG(0x120)
#define S5P_CLK_SRC0 S5P_CLKREG(0x200) #define S5P_CLK_SRC0 S5P_CLKREG(0x200)
......
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