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Commit 42accadb authored by Olof Johansson's avatar Olof Johansson
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Merge branch 'arm/fixes' into arm/soc 

Merging in the last batch of fixes that didn't go in before previous
release, just a few smaller DT fixups and a MAINTAINERS update

* arm/fixes: (29 commits)
  MAINTAINERS: Add myself as TEE subsystem reviewer
  ARM: dts: ux500: Fix LED probing
  arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory
  arm64: dts: allwinner: a64-sopine-baseboard: change RGMII mode to TXID
  arm64: meson: select COMMON_CLK
  soc: amlogic: meson-clk-measure: remove redundant dev_err call in meson_msr_probe()
  ARM: dts: qcom: sdx55-telit: Represent secure-regions as 64-bit elements
  ARM: dts: qcom: sdx55-t55: Represent secure-regions as 64-bit elements
  ARM: dts: sun8i: h3: orangepi-plus: Fix ethernet phy-mode
  ARM: dts: imx: emcon-avari: Fix nxp,pca8574 #gpio-cells
  ARM: dts: imx7d-pico: Fix the 'tuning-step' property
  ARM: dts: imx7d-meerkat96: Fix the 'tuning-step' property
  arm64: dts: freescale: sl28: var1: fix RGMII clock and voltage
  arm64: dts: freescale: sl28: var4: fix RGMII clock and voltage
  ARM: imx: pm-imx27: Include "common.h"
  arm64: dts: zii-ultra: fix 12V_MAIN voltage
  arm64: dts: zii-ultra: remove second GEN_3V3 regulator instance
  arm64: dts: ls1028a: fix memory node
  optee: use export_uuid() to copy client UUID
  arm64: dts: ti: k3*: Introduce reg definition for interrupt routers
  ...
parents 95ef7152 048c958f
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MAINTAINERS
View file @ 42accadb
......@@ -17921,6 +17921,7 @@ F: include/media/i2c/tw9910.h
TEE SUBSYSTEM
M: Jens Wiklander <jens.wiklander@linaro.org>
R: Sumit Garg <sumit.garg@linaro.org>
L: op-tee@lists.trustedfirmware.org
S: Maintained
F: Documentation/staging/tee.rst
......
arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
View file @ 42accadb
......@@ -105,9 +105,13 @@ &fec {
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-reset-duration = <20>;
phy-supply = <&sw2_reg>;
phy-handle = <&ethphy0>;
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm/boot/dts/imx6q-dhcom-som.dtsi
View file @ 42accadb
......@@ -406,6 +406,18 @@ &reg_soc {
vin-supply = <&sw1_reg>;
};
&reg_pu {
vin-supply = <&sw1_reg>;
};
&reg_vdd1p1 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 {
vin-supply = <&sw2_reg>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
......
arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi
View file @ 42accadb
......@@ -126,7 +126,7 @@ boardid: gpio@3a {
compatible = "nxp,pca8574";
reg = <0x3a>;
gpio-controller;
#gpio-cells = <1>;
#gpio-cells = <2>;
};
};
......
arch/arm/boot/dts/imx7d-meerkat96.dts
View file @ 42accadb
......@@ -193,7 +193,7 @@ &usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
keep-power-in-suspend;
tuning-step = <2>;
fsl,tuning-step = <2>;
vmmc-supply = <&reg_3p3v>;
no-1-8-v;
broken-cd;
......
arch/arm/boot/dts/imx7d-pico.dtsi
View file @ 42accadb
......@@ -351,7 +351,7 @@ &usdhc1 {
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
bus-width = <4>;
tuning-step = <2>;
fsl,tuning-step = <2>;
vmmc-supply = <&reg_3p3v>;
wakeup-source;
no-1-8-v;
......
arch/arm/boot/dts/qcom-sdx55-t55.dts
View file @ 42accadb
......@@ -250,7 +250,7 @@ nand@0 {
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
/* efs2 partition is secured */
secure-regions = <0x500000 0xb00000>;
secure-regions = /bits/ 64 <0x500000 0xb00000>;
};
};
......
arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
View file @ 42accadb
......@@ -250,7 +250,7 @@ nand@0 {
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
/* ico and efs2 partitions are secured */
secure-regions = <0x500000 0x500000
secure-regions = /bits/ 64 <0x500000 0x500000
0xa00000 0xb00000>;
};
};
......
arch/arm/boot/dts/ste-href.dtsi
View file @ 42accadb
......@@ -4,6 +4,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include "ste-href-family-pinctrl.dtsi"
/ {
......@@ -64,17 +65,20 @@ chan@0 {
reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
linux,default-trigger = "heartbeat";
};
chan@1 {
reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
chan@2 {
reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
};
lp5521@34 {
......@@ -88,16 +92,19 @@ chan@0 {
reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
chan@1 {
reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
chan@2 {
reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
};
bh1780@29 {
......
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
View file @ 42accadb
......@@ -85,7 +85,7 @@ &emac {
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
status = "okay";
};
......
arch/arm/mach-imx/pm-imx27.c
View file @ 42accadb
......@@ -12,6 +12,7 @@
#include <linux/suspend.h>
#include <linux/io.h>
#include "common.h"
#include "hardware.h"
static int mx27_suspend_enter(suspend_state_t state)
......
arch/arm64/Kconfig.platforms
View file @ 42accadb
......@@ -166,6 +166,7 @@ config ARCH_MEDIATEK
config ARCH_MESON
bool "Amlogic Platforms"
select COMMON_CLK
select MESON_IRQ_GPIO
help
This enables support for the arm64 based Amlogic SoCs
......
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
View file @ 42accadb
......@@ -79,7 +79,7 @@ &ehci1 {
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii-id";
phy-mode = "rgmii-txid";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_dc1sw>;
status = "okay";
......
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
View file @ 42accadb
......@@ -46,7 +46,8 @@ phy0: ethernet-phy@4 {
eee-broken-100tx;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
vddio-supply = <&vddh>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
......
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
View file @ 42accadb
......@@ -31,11 +31,10 @@ phy1: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
vddio-supply = <&vddh>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
......
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View file @ 42accadb
......@@ -197,8 +197,8 @@ soc: soc {
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
};
dcfg: syscon@1e00000 {
......
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts
View file @ 42accadb
......@@ -88,11 +88,11 @@ codec2: codec@18 {
pinctrl-0 = <&pinctrl_codec2>;
reg = <0x18>;
#sound-dai-cells = <0>;
HPVDD-supply = <&reg_3p3v>;
SPRVDD-supply = <&reg_3p3v>;
SPLVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>;
HPVDD-supply = <&reg_gen_3p3>;
SPRVDD-supply = <&reg_gen_3p3>;
SPLVDD-supply = <&reg_gen_3p3>;
AVDD-supply = <&reg_gen_3p3>;
IOVDD-supply = <&reg_gen_3p3>;
DVDD-supply = <&vgen4_reg>;
reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
};
......
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View file @ 42accadb
......@@ -45,8 +45,8 @@ pcie1_refclk: clock-pcie1-refclk {
reg_12p0_main: regulator-12p0-main {
compatible = "regulator-fixed";
regulator-name = "12V_MAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
......@@ -77,15 +77,6 @@ reg_gen_3p3: regulator-gen-3p3 {
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
vin-supply = <&reg_3p3_main>;
regulator-name = "GEN_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
......@@ -415,11 +406,11 @@ codec1: codec@18 {
pinctrl-0 = <&pinctrl_codec1>;
reg = <0x18>;
#sound-dai-cells = <0>;
HPVDD-supply = <&reg_3p3v>;
SPRVDD-supply = <&reg_3p3v>;
SPLVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>;
HPVDD-supply = <&reg_gen_3p3>;
SPRVDD-supply = <&reg_gen_3p3>;
SPLVDD-supply = <&reg_gen_3p3>;
AVDD-supply = <&reg_gen_3p3>;
IOVDD-supply = <&reg_gen_3p3>;
DVDD-supply = <&vgen4_reg>;
reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
};
......
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View file @ 42accadb
......@@ -227,7 +227,7 @@ pcie0: pcie@f8000000 {
<&pcie_phy 2>, <&pcie_phy 3>;
phy-names = "pcie-phy-0", "pcie-phy-1",
"pcie-phy-2", "pcie-phy-3";
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
<0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
......
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
View file @ 42accadb
......@@ -42,12 +42,12 @@ gic_its: msi-controller@1820000 {
};
};
dmss: dmss {
dmss: bus@48000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ranges;
ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
ti,sci-dev-id = <25>;
......@@ -134,7 +134,7 @@ main_pktdma: dma-controller@485c0000 {
};
};
dmsc: dmsc@44043000 {
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
......@@ -148,7 +148,7 @@ k3_pds: power-controller {
#power-domain-cells = <2>;
};
k3_clks: clocks {
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
......@@ -373,8 +373,9 @@ main_spi4: spi@20140000 {
clocks = <&k3_clks 145 0>;
};
main_gpio_intr: interrupt-controller0 {
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
......
arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
View file @ 42accadb
......@@ -74,8 +74,9 @@ mcu_spi1: spi@4b10000 {
clocks = <&k3_clks 148 0>;
};
mcu_gpio_intr: interrupt-controller1 {
mcu_gpio_intr: interrupt-controller@4210000 {
compatible = "ti,sci-intr";
reg = <0x00 0x04210000 0x00 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
......
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
View file @ 42accadb
......@@ -433,8 +433,9 @@ usb1_phy: phy@4110000 {
#phy-cells = <0>;
};
intr_main_gpio: interrupt-controller0 {
intr_main_gpio: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x0 0x00a00000 0x0 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
......@@ -444,18 +445,19 @@ intr_main_gpio: interrupt-controller0 {
ti,interrupt-ranges = <0 392 32>;
};
main-navss {
main_navss: bus@30800000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <118>;
intr_main_navss: interrupt-controller1 {
intr_main_navss: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x0 0x310e0000 0x0 0x2000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
......
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
View file @ 42accadb
......@@ -116,11 +116,11 @@ adc {
};
};
mcu-navss {
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;
......
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
View file @ 42accadb
......@@ -6,24 +6,24 @@
*/
&cbass_wakeup {
dmsc: dmsc {
dmsc: system-controller@44083000 {
compatible = "ti,am654-sci";
ti,host-id = <12>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x44083000 0x1000>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clocks {
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
......@@ -69,8 +69,9 @@ wkup_i2c0: i2c@42120000 {
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
};
intr_wkup_gpio: interrupt-controller2 {
intr_wkup_gpio: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x42200000 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
......
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
View file @ 42accadb
......@@ -85,12 +85,6 @@ sw6 {
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
};
};
clk_ov5640_fixed: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&wkup_pmx0 {
......@@ -287,23 +281,6 @@ &main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
ov5640: camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2_phy0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&main_i2c2 {
......@@ -496,14 +473,6 @@ flash@0{
};
};
&csi2_0 {
csi2_phy0: endpoint {
remote-endpoint = <&csi2_cam0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
......
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
View file @ 42accadb
......@@ -68,8 +68,9 @@ gic_its: msi-controller@1820000 {
};
};
main_gpio_intr: interrupt-controller0 {
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
......@@ -85,9 +86,12 @@ main_navss: bus@30000000 {
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <199>;
dma-coherent;
dma-ranges;
main_navss_intr: interrupt-controller1 {
main_navss_intr: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x00 0x310e0000 0x00 0x4000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
......
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
View file @ 42accadb
......@@ -6,7 +6,7 @@
*/
&cbass_mcu_wakeup {
dmsc: dmsc@44083000 {
dmsc: system-controller@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
......@@ -23,7 +23,7 @@ k3_pds: power-controller {
#power-domain-cells = <2>;
};
k3_clks: clocks {
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
......@@ -96,8 +96,9 @@ mcu_uart0: serial@40a00000 {
clock-names = "fclk";
};
wkup_gpio_intr: interrupt-controller2 {
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
......
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
View file @ 42accadb
......@@ -76,8 +76,9 @@ gic_its: msi-controller@1820000 {
};
};
main_gpio_intr: interrupt-controller0 {
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
......@@ -87,18 +88,19 @@ main_gpio_intr: interrupt-controller0 {
ti,interrupt-ranges = <8 392 56>;
};
main-navss {
main_navss: bus@30000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <199>;
main_navss_intr: interrupt-controller1 {
main_navss_intr: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x0 0x310e0000 0x0 0x4000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
......
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
View file @ 42accadb
......@@ -6,7 +6,7 @@
*/
&cbass_mcu_wakeup {
dmsc: dmsc@44083000 {
dmsc: system-controller@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
......@@ -23,7 +23,7 @@ k3_pds: power-controller {
#power-domain-cells = <2>;
};
k3_clks: clocks {
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
......@@ -96,8 +96,9 @@ mcu_uart0: serial@40a00000 {
clock-names = "fclk";
};
wkup_gpio_intr: interrupt-controller2 {
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
......@@ -249,11 +250,11 @@ adc {
};
};
mcu-navss {
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;
......
drivers/soc/amlogic/meson-clk-measure.c
View file @ 42accadb
......@@ -626,10 +626,8 @@ static int meson_msr_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base)) {
dev_err(&pdev->dev, "io resource mapping failed\n");
if (IS_ERR(base))
return PTR_ERR(base);
}
priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
&meson_clk_msr_regmap_config);
......
drivers/tee/optee/call.c
View file @ 42accadb
......@@ -220,6 +220,7 @@ int optee_open_session(struct tee_context *ctx,
struct optee_msg_arg *msg_arg;
phys_addr_t msg_parg;
struct optee_session *sess = NULL;
uuid_t client_uuid;
/* +2 for the meta parameters added below */
shm = get_msg_arg(ctx, arg->num_params + 2, &msg_arg, &msg_parg);
......@@ -240,10 +241,11 @@ int optee_open_session(struct tee_context *ctx,
memcpy(&msg_arg->params[0].u.value, arg->uuid, sizeof(arg->uuid));
msg_arg->params[1].u.value.c = arg->clnt_login;
rc = tee_session_calc_client_uuid((uuid_t *)&msg_arg->params[1].u.value,
arg->clnt_login, arg->clnt_uuid);
rc = tee_session_calc_client_uuid(&client_uuid, arg->clnt_login,
arg->clnt_uuid);
if (rc)
goto out;
export_uuid(msg_arg->params[1].u.octets, &client_uuid);
rc = optee_to_msg_param(msg_arg->params + 2, arg->num_params, param);
if (rc)
......
drivers/tee/optee/optee_msg.h
View file @ 42accadb
......@@ -9,7 +9,7 @@
#include <linux/types.h>
/*
* This file defines the OP-TEE message protocol used to communicate
* This file defines the OP-TEE message protocol (ABI) used to communicate
* with an instance of OP-TEE running in secure world.
*
* This file is divided into two sections.
......@@ -144,9 +144,10 @@ struct optee_msg_param_value {
* @tmem: parameter by temporary memory reference
* @rmem: parameter by registered memory reference
* @value: parameter by opaque value
* @octets: parameter by octet string
*
* @attr & OPTEE_MSG_ATTR_TYPE_MASK indicates if tmem, rmem or value is used in
* the union. OPTEE_MSG_ATTR_TYPE_VALUE_* indicates value,
* the union. OPTEE_MSG_ATTR_TYPE_VALUE_* indicates value or octets,
* OPTEE_MSG_ATTR_TYPE_TMEM_* indicates @tmem and
* OPTEE_MSG_ATTR_TYPE_RMEM_* indicates @rmem,
* OPTEE_MSG_ATTR_TYPE_NONE indicates that none of the members are used.
......@@ -157,6 +158,7 @@ struct optee_msg_param {
struct optee_msg_param_tmem tmem;
struct optee_msg_param_rmem rmem;
struct optee_msg_param_value value;
u8 octets[24];
} u;
};
......
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