Commit 42d0c3ad authored by Hans Verkuil's avatar Hans Verkuil Committed by Mauro Carvalho Chehab

[media] cx18: support big-endian systems

base_addr has type resource_size_t, which may be 64 bits.

Also fix a few endian issues related to mailboxes and firmware loading.
Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 1c36dfc5
...@@ -838,10 +838,10 @@ static int cx18_setup_pci(struct cx18 *cx, struct pci_dev *pci_dev, ...@@ -838,10 +838,10 @@ static int cx18_setup_pci(struct cx18 *cx, struct pci_dev *pci_dev,
} }
CX18_DEBUG_INFO("cx%d (rev %d) at %02x:%02x.%x, " CX18_DEBUG_INFO("cx%d (rev %d) at %02x:%02x.%x, "
"irq: %d, latency: %d, memory: 0x%lx\n", "irq: %d, latency: %d, memory: 0x%llx\n",
cx->pci_dev->device, cx->card_rev, pci_dev->bus->number, cx->pci_dev->device, cx->card_rev, pci_dev->bus->number,
PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn), PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn),
cx->pci_dev->irq, pci_latency, (unsigned long)cx->base_addr); cx->pci_dev->irq, pci_latency, (u64)cx->base_addr);
return 0; return 0;
} }
...@@ -938,7 +938,7 @@ static int __devinit cx18_probe(struct pci_dev *pci_dev, ...@@ -938,7 +938,7 @@ static int __devinit cx18_probe(struct pci_dev *pci_dev,
if (retval) if (retval)
goto err; goto err;
CX18_DEBUG_INFO("base addr: 0x%08x\n", cx->base_addr); CX18_DEBUG_INFO("base addr: 0x%llx\n", (u64)cx->base_addr);
/* PCI Device Setup */ /* PCI Device Setup */
retval = cx18_setup_pci(cx, pci_dev, pci_id); retval = cx18_setup_pci(cx, pci_dev, pci_id);
...@@ -946,8 +946,8 @@ static int __devinit cx18_probe(struct pci_dev *pci_dev, ...@@ -946,8 +946,8 @@ static int __devinit cx18_probe(struct pci_dev *pci_dev,
goto free_workqueues; goto free_workqueues;
/* map io memory */ /* map io memory */
CX18_DEBUG_INFO("attempting ioremap at 0x%08x len 0x%08x\n", CX18_DEBUG_INFO("attempting ioremap at 0x%llx len 0x%08x\n",
cx->base_addr + CX18_MEM_OFFSET, CX18_MEM_SIZE); (u64)cx->base_addr + CX18_MEM_OFFSET, CX18_MEM_SIZE);
cx->enc_mem = ioremap_nocache(cx->base_addr + CX18_MEM_OFFSET, cx->enc_mem = ioremap_nocache(cx->base_addr + CX18_MEM_OFFSET,
CX18_MEM_SIZE); CX18_MEM_SIZE);
if (!cx->enc_mem) { if (!cx->enc_mem) {
......
...@@ -622,7 +622,7 @@ struct cx18 { ...@@ -622,7 +622,7 @@ struct cx18 {
unique ID. Starts at 1, so 0 can be used as unique ID. Starts at 1, so 0 can be used as
uninitialized value in the stream->id. */ uninitialized value in the stream->id. */
u32 base_addr; resource_size_t base_addr;
u8 card_rev; u8 card_rev;
void __iomem *enc_mem, *reg_mem; void __iomem *enc_mem, *reg_mem;
......
...@@ -164,8 +164,13 @@ static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx, ...@@ -164,8 +164,13 @@ static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx,
apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32]; apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
while (offset + sizeof(seghdr) < fw->size) { while (offset + sizeof(seghdr) < fw->size) {
/* TODO: byteswapping */ const u32 *shptr = src + offset / 4;
memcpy(&seghdr, src + offset / 4, sizeof(seghdr));
seghdr.sync1 = le32_to_cpu(shptr[0]);
seghdr.sync2 = le32_to_cpu(shptr[1]);
seghdr.addr = le32_to_cpu(shptr[2]);
seghdr.size = le32_to_cpu(shptr[3]);
offset += sizeof(seghdr); offset += sizeof(seghdr);
if (seghdr.sync1 != APU_ROM_SYNC1 || if (seghdr.sync1 != APU_ROM_SYNC1 ||
seghdr.sync2 != APU_ROM_SYNC2) { seghdr.sync2 != APU_ROM_SYNC2) {
......
...@@ -434,6 +434,7 @@ static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order) ...@@ -434,6 +434,7 @@ static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
{ {
u32 handle, mdl_ack_offset, mdl_ack_count; u32 handle, mdl_ack_offset, mdl_ack_count;
struct cx18_mailbox *mb; struct cx18_mailbox *mb;
int i;
mb = &order->mb; mb = &order->mb;
handle = mb->args[0]; handle = mb->args[0];
...@@ -447,8 +448,9 @@ static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order) ...@@ -447,8 +448,9 @@ static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
return -1; return -1;
} }
cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset, for (i = 0; i < sizeof(struct cx18_mdl_ack) * mdl_ack_count; i += sizeof(u32))
sizeof(struct cx18_mdl_ack) * mdl_ack_count); ((u32 *)order->mdl_ack)[i / sizeof(u32)] =
cx18_readl(cx, cx->enc_mem + mdl_ack_offset + i);
if ((order->flags & CX18_F_EWO_MB_STALE) == 0) if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
mb_ack_irq(cx, order); mb_ack_irq(cx, order);
...@@ -538,6 +540,7 @@ void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu) ...@@ -538,6 +540,7 @@ void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
struct cx18_mailbox *order_mb; struct cx18_mailbox *order_mb;
struct cx18_in_work_order *order; struct cx18_in_work_order *order;
int submit; int submit;
int i;
switch (rpu) { switch (rpu) {
case CPU: case CPU:
...@@ -562,10 +565,12 @@ void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu) ...@@ -562,10 +565,12 @@ void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
order_mb = &order->mb; order_mb = &order->mb;
/* mb->cmd and mb->args[0] through mb->args[2] */ /* mb->cmd and mb->args[0] through mb->args[2] */
cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32)); for (i = 0; i < 4; i++)
(&order_mb->cmd)[i] = cx18_readl(cx, &mb->cmd + i);
/* mb->request and mb->ack. N.B. we want to read mb->ack last */ /* mb->request and mb->ack. N.B. we want to read mb->ack last */
cx18_memcpy_fromio(cx, &order_mb->request, &mb->request, for (i = 0; i < 2; i++)
2 * sizeof(u32)); (&order_mb->request)[i] = cx18_readl(cx, &mb->request + i);
if (order_mb->request == order_mb->ack) { if (order_mb->request == order_mb->ack) {
CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our " CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment