Commit 42efa5e3 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'x86_cpu_for_v6.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 cpu updates from Borislav Petkov:

 - Remove the vendor check when selecting MWAIT as the default idle
   state

 - Respect idle=nomwait when supplied on the kernel cmdline

 - Two small cleanups

* tag 'x86_cpu_for_v6.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Use MSR_IA32_MISC_ENABLE constants
  x86: Fix comment for X86_FEATURE_ZEN
  x86: Remove vendor checks from prefer_mwait_c1_over_halt
  x86: Handle idle=nomwait cmdline properly for x86_idle
parents 650ea1f6 3f2adf00
...@@ -612,8 +612,8 @@ the ``menu`` governor to be used on the systems that use the ``ladder`` governor ...@@ -612,8 +612,8 @@ the ``menu`` governor to be used on the systems that use the ``ladder`` governor
by default this way, for example. by default this way, for example.
The other kernel command line parameters controlling CPU idle time management The other kernel command line parameters controlling CPU idle time management
described below are only relevant for the *x86* architecture and some of described below are only relevant for the *x86* architecture and references
them affect Intel processors only. to ``intel_idle`` affect Intel processors only.
The *x86* architecture support code recognizes three kernel command line The *x86* architecture support code recognizes three kernel command line
options related to CPU idle time management: ``idle=poll``, ``idle=halt``, options related to CPU idle time management: ``idle=poll``, ``idle=halt``,
...@@ -635,10 +635,13 @@ idle, so it very well may hurt single-thread computations performance as well as ...@@ -635,10 +635,13 @@ idle, so it very well may hurt single-thread computations performance as well as
energy-efficiency. Thus using it for performance reasons may not be a good idea energy-efficiency. Thus using it for performance reasons may not be a good idea
at all.] at all.]
The ``idle=nomwait`` option disables the ``intel_idle`` driver and causes The ``idle=nomwait`` option prevents the use of ``MWAIT`` instruction of
``acpi_idle`` to be used (as long as all of the information needed by it is the CPU to enter idle states. When this option is used, the ``acpi_idle``
there in the system's ACPI tables), but it is not allowed to use the driver will use the ``HLT`` instruction instead of ``MWAIT``. On systems
``MWAIT`` instruction of the CPUs to ask the hardware to enter idle states. running Intel processors, this option disables the ``intel_idle`` driver
and forces the use of the ``acpi_idle`` driver instead. Note that in either
case, ``acpi_idle`` driver will function only if all the information needed
by it is in the system's ACPI tables.
In addition to the architecture-level kernel command line options affecting CPU In addition to the architecture-level kernel command line options affecting CPU
idle time management, there are parameters affecting individual ``CPUIdle`` idle time management, there are parameters affecting individual ``CPUIdle``
......
...@@ -219,7 +219,7 @@ ...@@ -219,7 +219,7 @@
#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */ #define X86_FEATURE_ZEN (7*32+28) /* "" CPU based on Zen microarchitecture */
#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
#define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */ #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
......
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#define MWAIT_SUBSTATE_SIZE 4 #define MWAIT_SUBSTATE_SIZE 4
#define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) #define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
#define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK) #define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK)
#define MWAIT_C1_SUBSTATE_MASK 0xf0
#define CPUID_MWAIT_LEAF 5 #define CPUID_MWAIT_LEAF 5
#define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
......
...@@ -682,9 +682,9 @@ static void init_intel(struct cpuinfo_x86 *c) ...@@ -682,9 +682,9 @@ static void init_intel(struct cpuinfo_x86 *c)
unsigned int l1, l2; unsigned int l1, l2;
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
if (!(l1 & (1<<11))) if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
set_cpu_cap(c, X86_FEATURE_BTS); set_cpu_cap(c, X86_FEATURE_BTS);
if (!(l1 & (1<<12))) if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
set_cpu_cap(c, X86_FEATURE_PEBS); set_cpu_cap(c, X86_FEATURE_PEBS);
} }
......
...@@ -810,24 +810,43 @@ static void amd_e400_idle(void) ...@@ -810,24 +810,43 @@ static void amd_e400_idle(void)
} }
/* /*
* Intel Core2 and older machines prefer MWAIT over HALT for C1. * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf
* We can't rely on cpuidle installing MWAIT, because it will not load * exists and whenever MONITOR/MWAIT extensions are present there is at
* on systems that support only C1 -- so the boot default must be MWAIT. * least one C1 substate.
* *
* Some AMD machines are the opposite, they depend on using HALT. * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait
* * is passed to kernel commandline parameter.
* So for default C1, which is used during boot until cpuidle loads,
* use MWAIT-C1 on Intel HW that has it, else use HALT.
*/ */
static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
{ {
if (c->x86_vendor != X86_VENDOR_INTEL) u32 eax, ebx, ecx, edx;
/* User has disallowed the use of MWAIT. Fallback to HALT */
if (boot_option_idle_override == IDLE_NOMWAIT)
return 0; return 0;
if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR)) /* MWAIT is not supported on this platform. Fallback to HALT */
if (!cpu_has(c, X86_FEATURE_MWAIT))
return 0; return 0;
/* Monitor has a bug. Fallback to HALT */
if (boot_cpu_has_bug(X86_BUG_MONITOR))
return 0;
cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
/*
* If MWAIT extensions are not available, it is safe to use MWAIT
* with EAX=0, ECX=0.
*/
if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED))
return 1; return 1;
/*
* If MWAIT extensions are available, there should be at least one
* MWAIT C1 substate present.
*/
return (edx & MWAIT_C1_SUBSTATE_MASK);
} }
/* /*
...@@ -932,9 +951,8 @@ static int __init idle_setup(char *str) ...@@ -932,9 +951,8 @@ static int __init idle_setup(char *str)
} else if (!strcmp(str, "nomwait")) { } else if (!strcmp(str, "nomwait")) {
/* /*
* If the boot option of "idle=nomwait" is added, * If the boot option of "idle=nomwait" is added,
* it means that mwait will be disabled for CPU C2/C3 * it means that mwait will be disabled for CPU C1/C2/C3
* states. In such case it won't touch the variable * states.
* of boot_option_idle_override.
*/ */
boot_option_idle_override = IDLE_NOMWAIT; boot_option_idle_override = IDLE_NOMWAIT;
} else } else
......
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