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Commit 4369c5f3 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge branch 'clps711x/cleanup' into next/cleanup2 

Various cleanups for the clps711x platform from
Alexander Shiyan <shc_work@mail.ru> via email:

* clps711x/cleanup:
  ARM: clps711x: Remove board support for CEIVA
  ARM: clps711x: Fix register definitions
  ARM: clps711x: Fix lowlevel debug-macro
  ARM: clps711x: Added simple clock framework
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9c0cc578 1c3a918f
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arch/arm/Kconfig
View file @ 4369c5f3
......@@ -384,6 +384,8 @@ config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select CPU_ARM720T
select ARCH_USES_GETTIMEOFFSET
select COMMON_CLK
select CLKDEV_LOOKUP
select NEED_MACH_MEMORY_H
help
Support for Cirrus Logic 711x/721x/731x based boards.
......
arch/arm/mach-clps711x/Kconfig
View file @ 4369c5f3
......@@ -16,12 +16,6 @@ config ARCH_CDB89712
The board includes 2 serial ports, Ethernet, IRDA, and expansion
headers. It comes with 16 MB SDRAM and 8 MB flash ROM.
config ARCH_CEIVA
bool "CEIVA"
help
Say Y here if you intend to run this kernel on the Ceiva/Polaroid
PhotoMax Digital Picture Frame.
config ARCH_CLEP7312
bool "CLEP7312"
help
......
arch/arm/mach-clps711x/Makefile
View file @ 4369c5f3
......@@ -9,7 +9,6 @@ obj-m :=
obj-n :=
obj- :=
obj-$(CONFIG_ARCH_CEIVA) += ceiva.o
obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
......
arch/arm/mach-clps711x/ceiva.c deleted 100644 → 0
View file @ 9c0cc578
/*
* linux/arch/arm/mach-clps711x/arch-ceiva.c
*
* Copyright (C) 2002, Rob Scott <rscott@mtrob.fdns.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/string.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/sizes.h>
#include <asm/mach/map.h>
#include "common.h"
static struct map_desc ceiva_io_desc[] __initdata = {
/* SED1355 controlled video RAM & registers */
{
.virtual = CEIVA_VIRT_SED1355,
.pfn = __phys_to_pfn(CEIVA_PHYS_SED1355),
.length = SZ_2M,
.type = MT_DEVICE
}
};
static void __init ceiva_map_io(void)
{
clps711x_map_io();
iotable_init(ceiva_io_desc, ARRAY_SIZE(ceiva_io_desc));
}
MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame")
/* Maintainer: Rob Scott */
.atag_offset = 0x100,
.map_io = ceiva_map_io,
.init_irq = clps711x_init_irq,
.timer = &clps711x_timer,
.restart = clps711x_restart,
MACHINE_END
arch/arm/mach-clps711x/common.c
View file @ 4369c5f3
......@@ -19,24 +19,25 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <asm/sizes.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>
#include <mach/hardware.h>
static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
*clk_tint, *clk_spi;
static unsigned long latch;
/*
* This maps the generic CLPS711x registers
*/
......@@ -166,8 +167,8 @@ void __init clps711x_init_irq(void)
static unsigned long clps711x_gettimeoffset(void)
{
unsigned long hwticks;
hwticks = LATCH - (clps_readl(TC2D) & 0xffff); /* since last underflow */
return (hwticks * (tick_nsec / 1000)) / LATCH;
hwticks = latch - (clps_readl(TC2D) & 0xffff);
return (hwticks * (tick_nsec / 1000)) / latch;
}
/*
......@@ -185,15 +186,71 @@ static struct irqaction clps711x_timer_irq = {
.handler = p720t_timer_interrupt,
};
static void add_fixed_clk(struct clk *clk, const char *name, int rate)
{
clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
clk_register_clkdev(clk, name, NULL);
}
static void __init clps711x_timer_init(void)
{
unsigned int syscon;
int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
u32 tmp;
osc = 3686400;
ext = 13000000;
tmp = clps_readl(PLLR) >> 24;
if (tmp)
pll = (osc * tmp) / 2;
else
pll = 73728000; /* Default value */
tmp = clps_readl(SYSFLG2);
if (tmp & SYSFLG2_CKMODE) {
cpu = ext;
bus = cpu;
spi = 135400;
} else {
cpu = pll;
if (cpu >= 36864000)
bus = cpu / 2;
else
bus = 36864000 / 2;
spi = cpu / 576;
}
uart = bus / 10;
if (tmp & SYSFLG2_CKMODE) {
tmp = clps_readl(SYSCON2);
if (tmp & SYSCON2_OSTB)
timh = ext / 26;
else
timh = 541440;
} else
timh = cpu / 144;
timl = timh / 256;
/* All clocks are fixed */
add_fixed_clk(clk_pll, "pll", pll);
add_fixed_clk(clk_bus, "bus", bus);
add_fixed_clk(clk_uart, "uart", uart);
add_fixed_clk(clk_timerl, "timer_lf", timl);
add_fixed_clk(clk_timerh, "timer_hf", timh);
add_fixed_clk(clk_tint, "tint", 64);
add_fixed_clk(clk_spi, "spi", spi);
pr_info("CPU frequency set at %i Hz.\n", cpu);
latch = (timh + HZ / 2) / HZ;
syscon = clps_readl(SYSCON1);
syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
clps_writel(syscon, SYSCON1);
tmp = clps_readl(SYSCON1);
tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
clps_writel(tmp, SYSCON1);
clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
clps_writel(latch - 1, TC2D);
setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
}
......
arch/arm/mach-clps711x/include/mach/clps711x.h
View file @ 4369c5f3
......@@ -31,8 +31,8 @@
#define PBDDR (0x0041)
#define PCDDR (0x0042)
#define PDDDR (0x0043)
#define PEDR (0x0080)
#define PEDDR (0x00c0)
#define PEDR (0x0083)
#define PEDDR (0x00c3)
#define SYSCON1 (0x0100)
#define SYSFLG1 (0x0140)
#define MEMCFG1 (0x0180)
......@@ -77,7 +77,7 @@
#define KBDEOI (0x1700)
#define DAIR (0x2000)
#define DAIR0 (0x2040)
#define DAIDR0 (0x2040)
#define DAIDR1 (0x2080)
#define DAIDR2 (0x20c0)
#define DAISR (0x2100)
......@@ -191,8 +191,7 @@
#define UBRLCR_WRDLEN8 (3 << 17)
#define UBRLCR_WRDLEN_MASK (3 << 17)
#define SYNCIO_FRMLEN(x) (((x) & 0x3f) << 7)
#define SYNCIO_CFGLEN(x) ((x) & 0x7f)
#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8)
#define SYNCIO_SMCKEN (1 << 13)
#define SYNCIO_TXFRMEN (1 << 14)
......
arch/arm/mach-clps711x/include/mach/debug-macro.S
View file @ 4369c5f3
......@@ -28,17 +28,11 @@
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
tst \rd, #1 << 11 @ UBUSYx
bne 1001b
.endm
.macro busyuart,rd,rx
tst \rx, #0x1000 @ UART2 does not have CTS here
bne 1002f
1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
tst \rd, #1 << 8 @ CTS
tst \rd, #1 << 11 @ UBUSYx
bne 1001b
1002:
.endm
arch/arm/mach-clps711x/include/mach/hardware.h
View file @ 4369c5f3
......@@ -116,7 +116,6 @@
#endif /* CONFIG_ARCH_EDB7211 */
/*
* Relevant bits in port D, which controls power to the various parts of
* the LCD on the EDB7211.
......@@ -125,51 +124,4 @@
#define EDB_PD2_LCDEN (1<<2)
#define EDB_PD3_LCDBL (1<<3)
#if defined (CONFIG_ARCH_CEIVA)
/*
* The two flash banks are wired to chip selects 0 and 1. This is the mapping
* for them.
*
* nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
* in jumpered boot mode.
*/
#define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
#define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
#define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */
#define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */
#define CEIVA_FLASH_SIZE 0x100000
#define CEIVA_FLASH_WIDTH 2
/*
* SED1355 LCD controller
*/
#define CEIVA_PHYS_SED1355 CS2_PHYS_BASE
#define CEIVA_VIRT_SED1355 (0xfc000000)
/*
* Relevant bits in port D, which controls power to the various parts of
* the LCD on the Ceiva Photo Max, and reset to the LCD controller.
*/
// Reset line to SED1355 (must be high to operate)
#define CEIVA_PD1_LCDRST (1<<1)
// LCD panel enable (set to one, to enable LCD)
#define CEIVA_PD4_LCDEN (1<<4)
// Backlight (set to one, to turn on backlight
#define CEIVA_PD5_LCDBL (1<<5)
/*
* Relevant bits in port B, which report the status of the buttons.
*/
// White button
#define CEIVA_PB4_WHT_BTN (1<<4)
// Black button
#define CEIVA_PB0_BLK_BTN (1<<0)
#endif // #if defined (CONFIG_ARCH_CEIVA)
#endif
arch/arm/mach-clps711x/include/mach/timex.h
View file @ 4369c5f3
/*
* arch/arm/mach-clps711x/include/mach/timex.h
*
* Prospector 720T architecture timex specifications
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* Bogus value */
#define CLOCK_TICK_RATE 512000
arch/arm/tools/mach-types
View file @ 4369c5f3
......@@ -66,7 +66,6 @@ iq80321 ARCH_IQ80321 IQ80321 169
ks8695 ARCH_KS8695 KS8695 180
karo ARCH_KARO KARO 190
smdk2410 ARCH_SMDK2410 SMDK2410 193
ceiva ARCH_CEIVA CEIVA 200
voiceblue MACH_VOICEBLUE VOICEBLUE 218
h5400 ARCH_H5400 H5400 220
omap_innovator MACH_OMAP_INNOVATOR OMAP_INNOVATOR 234
......
drivers/video/Kconfig
View file @ 4369c5f3
......@@ -979,18 +979,6 @@ config FB_PVR2
(<file:drivers/video/pvr2fb.c>). Please see the file
<file:Documentation/fb/pvr2fb.txt>.
config FB_EPSON1355
bool "Epson 1355 framebuffer support"
depends on (FB = y) && ARCH_CEIVA
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
help
Build in support for the SED1355 Epson Research Embedded RAMDAC
LCD/CRT Controller (since redesignated as the S1D13505) as a
framebuffer. Product specs at
<http://vdc.epson.com/>.
config FB_S1D13XXX
tristate "Epson S1D13XXX framebuffer support"
depends on FB
......
drivers/video/Makefile
View file @ 4369c5f3
......@@ -94,7 +94,6 @@ obj-$(CONFIG_FB_G364) += g364fb.o
obj-$(CONFIG_FB_EP93XX) += ep93xx-fb.o
obj-$(CONFIG_FB_SA1100) += sa1100fb.o
obj-$(CONFIG_FB_HIT) += hitfb.o
obj-$(CONFIG_FB_EPSON1355) += epson1355fb.o
obj-$(CONFIG_FB_ATMEL) += atmel_lcdfb.o
obj-$(CONFIG_FB_PVR2) += pvr2fb.o
obj-$(CONFIG_FB_VOODOO1) += sstfb.o
......
drivers/video/epson1355fb.c deleted 100644 → 0
View file @ 9c0cc578
This diff is collapsed.
include/video/epson1355.h deleted 100644 → 0
View file @ 9c0cc578
/*
* include/video/epson13xx.h -- Epson 13xx frame buffer
*
* Copyright (C) Hewlett-Packard Company. All rights reserved.
*
* Written by Christopher Hoover <ch@hpl.hp.com>
*
*/
#ifndef _EPSON13XX_H_
#define _EPSON13XX_H_
#define REG_REVISION_CODE 0x00
#define REG_MEMORY_CONFIG 0x01
#define REG_PANEL_TYPE 0x02
#define REG_MOD_RATE 0x03
#define REG_HORZ_DISP_WIDTH 0x04
#define REG_HORZ_NONDISP_PERIOD 0x05
#define REG_HRTC_START_POSITION 0x06
#define REG_HRTC_PULSE_WIDTH 0x07
#define REG_VERT_DISP_HEIGHT0 0x08
#define REG_VERT_DISP_HEIGHT1 0x09
#define REG_VERT_NONDISP_PERIOD 0x0A
#define REG_VRTC_START_POSITION 0x0B
#define REG_VRTC_PULSE_WIDTH 0x0C
#define REG_DISPLAY_MODE 0x0D
#define REG_SCRN1_LINE_COMPARE0 0x0E
#define REG_SCRN1_LINE_COMPARE1 0x0F
#define REG_SCRN1_DISP_START_ADDR0 0x10
#define REG_SCRN1_DISP_START_ADDR1 0x11
#define REG_SCRN1_DISP_START_ADDR2 0x12
#define REG_SCRN2_DISP_START_ADDR0 0x13
#define REG_SCRN2_DISP_START_ADDR1 0x14
#define REG_SCRN2_DISP_START_ADDR2 0x15
#define REG_MEM_ADDR_OFFSET0 0x16
#define REG_MEM_ADDR_OFFSET1 0x17
#define REG_PIXEL_PANNING 0x18
#define REG_CLOCK_CONFIG 0x19
#define REG_POWER_SAVE_CONFIG 0x1A
#define REG_MISC 0x1B
#define REG_MD_CONFIG_READBACK0 0x1C
#define REG_MD_CONFIG_READBACK1 0x1D
#define REG_GPIO_CONFIG0 0x1E
#define REG_GPIO_CONFIG1 0x1F
#define REG_GPIO_CONTROL0 0x20
#define REG_GPIO_CONTROL1 0x21
#define REG_PERF_ENHANCEMENT0 0x22
#define REG_PERF_ENHANCEMENT1 0x23
#define REG_LUT_ADDR 0x24
#define REG_RESERVED_1 0x25
#define REG_LUT_DATA 0x26
#define REG_INK_CURSOR_CONTROL 0x27
#define REG_CURSOR_X_POSITION0 0x28
#define REG_CURSOR_X_POSITION1 0x29
#define REG_CURSOR_Y_POSITION0 0x2A
#define REG_CURSOR_Y_POSITION1 0x2B
#define REG_INK_CURSOR_COLOR0_0 0x2C
#define REG_INK_CURSOR_COLOR0_1 0x2D
#define REG_INK_CURSOR_COLOR1_0 0x2E
#define REG_INK_CURSOR_COLOR1_1 0x2F
#define REG_INK_CURSOR_START_ADDR 0x30
#define REG_ALTERNATE_FRM 0x31
#endif
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