Commit 438a0f0a authored by Bjorn Helgaas's avatar Bjorn Helgaas

iwlwifi: Use standard #defines for PCIe Capability ASPM fields

Use the standard #defines rather than creating local definitions for
PCIe Capability ASPM fields.
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarJohannes Berg <johannes.berg@intel.com>
parent b9d146e3
...@@ -670,8 +670,6 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans) ...@@ -670,8 +670,6 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
/* PCI registers */ /* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT 0x041 #define PCI_CFG_RETRY_TIMEOUT 0x041
#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
static void iwl_apm_config(struct iwl_trans *trans) static void iwl_apm_config(struct iwl_trans *trans)
{ {
...@@ -688,8 +686,7 @@ static void iwl_apm_config(struct iwl_trans *trans) ...@@ -688,8 +686,7 @@ static void iwl_apm_config(struct iwl_trans *trans)
*/ */
pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
PCI_CFG_LINK_CTRL_VAL_L1_EN) {
/* L1-ASPM enabled; disable(!) L0S */ /* L1-ASPM enabled; disable(!) L0S */
iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
dev_printk(KERN_INFO, trans->dev, dev_printk(KERN_INFO, trans->dev,
...@@ -700,7 +697,7 @@ static void iwl_apm_config(struct iwl_trans *trans) ...@@ -700,7 +697,7 @@ static void iwl_apm_config(struct iwl_trans *trans)
dev_printk(KERN_INFO, trans->dev, dev_printk(KERN_INFO, trans->dev,
"L1 Disabled; Enabling L0S\n"); "L1 Disabled; Enabling L0S\n");
} }
trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
} }
/* /*
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment