Skip to content

L
linux
Commit 4426cc65 authored by Dan O'Donovan's avatar Dan O'Donovan Committed by Sasha Levin
Browse files
Options

pinctrl: cherryview: prevent concurrent access to GPIO controllers 

[ Upstream commit 0bd50d71 ]

Due to a silicon issue on the Atom X5-Z8000 "Cherry Trail" processor
series, a common lock must be used to prevent concurrent accesses
across the 4 GPIO controllers managed by this driver.

See Intel Atom Z8000 Processor Series Specification Update
(Rev. 005), errata #CHT34, for further information.

Cc: stable <stable@vger.kernel.org>
Signed-off-by: default avatarDan O'Donovan <dan@emutex.com>
Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarSasha Levin <alexander.levin@verizon.com>
parent 40357fd7
Hide whitespace changes
Inline Side-by-side
Showing with 44 additions and 36 deletions
drivers/pinctrl/intel/pinctrl-cherryview.c
View file @ 4426cc65
......@@ -160,7 +160,6 @@ struct chv_pin_context {
* @pctldev: Pointer to the pin controller device
* @chip: GPIO chip in this pin controller
* @regs: MMIO registers
* @lock: Lock to serialize register accesses
* @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
* offset (in GPIO number space)
* @community: Community this pinctrl instance represents
......@@ -174,7 +173,6 @@ struct chv_pinctrl {
struct pinctrl_dev *pctldev;
struct gpio_chip chip;
void __iomem *regs;
raw_spinlock_t lock;
unsigned intr_lines[16];
const struct chv_community *community;
u32 saved_intmask;
......@@ -659,6 +657,17 @@ static const struct chv_community *chv_communities[] = {
&southeast_community,
};
/*
* Lock to serialize register accesses
*
* Due to a silicon issue, a shared lock must be used to prevent
* concurrent accesses across the 4 GPIO controllers.
*
* See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
* errata #CHT34, for further information.
*/
static DEFINE_RAW_SPINLOCK(chv_lock);
static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
unsigned reg)
{
......@@ -720,13 +729,13 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
u32 ctrl0, ctrl1;
bool locked;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
locked = chv_pad_locked(pctrl, offset);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
seq_puts(s, "GPIO ");
......@@ -789,14 +798,14 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
grp = &pctrl->community->groups[group];
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
/* Check first that the pad is not locked */
for (i = 0; i < grp->npins; i++) {
if (chv_pad_locked(pctrl, grp->pins[i])) {
dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
grp->pins[i]);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EBUSY;
}
}
......@@ -839,7 +848,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
}
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
......@@ -853,13 +862,13 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
void __iomem *reg;
u32 value;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
if (chv_pad_locked(pctrl, offset)) {
value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
if (!(value & CHV_PADCTRL0_GPIOEN)) {
/* Locked so cannot enable */
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EBUSY;
}
} else {
......@@ -899,7 +908,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
chv_writel(value, reg);
}
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
......@@ -913,13 +922,13 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
void __iomem *reg;
u32 value;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
chv_writel(value, reg);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
......@@ -931,7 +940,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned long flags;
u32 ctrl0;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
if (input)
......@@ -940,7 +949,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
chv_writel(ctrl0, reg);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
......@@ -965,10 +974,10 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
u16 arg = 0;
u32 term;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
......@@ -1042,7 +1051,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
unsigned long flags;
u32 ctrl0, pull;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(reg);
switch (param) {
......@@ -1065,7 +1074,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
break;
default:
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
......@@ -1083,7 +1092,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
break;
default:
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
......@@ -1091,12 +1100,12 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
break;
default:
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
chv_writel(ctrl0, reg);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
......@@ -1172,9 +1181,9 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
unsigned long flags;
u32 ctrl0, cfg;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
......@@ -1192,7 +1201,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
void __iomem *reg;
u32 ctrl0;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
ctrl0 = readl(reg);
......@@ -1204,7 +1213,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
chv_writel(ctrl0, reg);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
......@@ -1214,9 +1223,9 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
u32 ctrl0, direction;
unsigned long flags;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
......@@ -1254,14 +1263,14 @@ static void chv_gpio_irq_ack(struct irq_data *d)
int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
u32 intr_line;
raw_spin_lock(&pctrl->lock);
raw_spin_lock(&chv_lock);
intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
raw_spin_unlock(&pctrl->lock);
raw_spin_unlock(&chv_lock);
}
static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
......@@ -1272,7 +1281,7 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
u32 value, intr_line;
unsigned long flags;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
......@@ -1285,7 +1294,7 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
value |= BIT(intr_line);
chv_writel(value, pctrl->regs + CHV_INTMASK);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static void chv_gpio_irq_mask(struct irq_data *d)
......@@ -1319,7 +1328,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
unsigned long flags;
u32 intsel, value;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
intsel &= CHV_PADCTRL0_INTSEL_MASK;
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
......@@ -1334,7 +1343,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
__irq_set_handler_locked(d->irq, handler);
pctrl->intr_lines[intsel] = offset;
}
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
chv_gpio_irq_unmask(d);
......@@ -1350,7 +1359,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock_irqsave(&chv_lock, flags);
/*
* Pins which can be used as shared interrupt are configured in
......@@ -1399,7 +1408,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
else if (type & IRQ_TYPE_LEVEL_MASK)
__irq_set_handler_locked(d->irq, handle_level_irq);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
......@@ -1511,7 +1520,6 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
if (i == ARRAY_SIZE(chv_communities))
return -ENODEV;
raw_spin_lock_init(&pctrl->lock);
pctrl->dev = &pdev->dev;
#ifdef CONFIG_PM_SLEEP
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7