ARM: dts: imx6q: improve indentation for fsl,pins

Change the indentation for property fsl,pins a little bit, so that
the first and the last line get the same indentation with all other
lines.  Then it will be easier to copy and past any of these lines.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

arch/arm/boot/dts/imx6q.dtsi

@@ -513,16 +513,19 @@ iomuxc@020e0000 {
 				/* shared pinctrl settings */
 				audmux {
 					pinctrl_audmux_1: audmux-1 {
-						fsl,pins = <18   0x80000000	/* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+						fsl,pins = <
+							18   0x80000000	/* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
 							1586 0x80000000	/* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
 							11   0x80000000	/* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
-							    3    0x80000000>;	/* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+							3    0x80000000	/* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+						>;
 					};
 				};
 
 				gpmi-nand {
 					pinctrl_gpmi_nand_1: gpmi-nand-1 {
-						fsl,pins = <1328 0xb0b1		/* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+						fsl,pins = <
+							1328 0xb0b1	/* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
 							1336 0xb0b1	/* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
 							1344 0xb0b1	/* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
 							1352 0xb000	/* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
@@ -540,27 +543,33 @@ pinctrl_gpmi_nand_1: gpmi-nand-1 {
 							1437 0xb0b1	/* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
 							1445 0xb0b1	/* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
 							1453 0xb0b1	/* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
-							    1463 0x00b1>;	/* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+							1463 0x00b1	/* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+						>;
 					};
 				};
 
 				i2c1 {
 					pinctrl_i2c1_1: i2c1grp-1 {
-						fsl,pins = <137 0x4001b8b1	/* MX6Q_PAD_EIM_D21__I2C1_SCL */
-							    196 0x4001b8b1>;	/* MX6Q_PAD_EIM_D28__I2C1_SDA */
+						fsl,pins = <
+							137 0x4001b8b1	/* MX6Q_PAD_EIM_D21__I2C1_SCL */
+							196 0x4001b8b1	/* MX6Q_PAD_EIM_D28__I2C1_SDA */
+						>;
 					};
 				};
 
 				serial2 {
 					pinctrl_serial2_1: serial2grp-1 {
-						fsl,pins = <183 0x1b0b1		/* MX6Q_PAD_EIM_D26__UART2_TXD */
-							    191 0x1b0b1>;	/* MX6Q_PAD_EIM_D27__UART2_RXD */
+						fsl,pins = <
+							183 0x1b0b1	/* MX6Q_PAD_EIM_D26__UART2_TXD */
+							191 0x1b0b1	/* MX6Q_PAD_EIM_D27__UART2_RXD */
+						>;
 					};
 				};
 
 				usdhc3 {
 					pinctrl_usdhc3_1: usdhc3grp-1 {
-						fsl,pins = <1273 0x17059	/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+						fsl,pins = <
+							1273 0x17059	/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
 							1281 0x10059	/* MX6Q_PAD_SD3_CLK__USDHC3_CLK	*/
 							1289 0x17059	/* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
 							1297 0x17059	/* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
@@ -569,13 +578,15 @@ pinctrl_usdhc3_1: usdhc3grp-1 {
 							1265 0x17059	/* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
 							1257 0x17059	/* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
 							1249 0x17059	/* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
-							    1241 0x17059>;	/* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+							1241 0x17059	/* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+						>;
 					};
 				};
 
 				usdhc4 {
 					pinctrl_usdhc4_1: usdhc4grp-1 {
-						fsl,pins = <1386 0x17059	/* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+						fsl,pins = <
+							1386 0x17059	/* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
 							1392 0x10059	/* MX6Q_PAD_SD4_CLK__USDHC4_CLK	*/
 							1462 0x17059	/* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
 							1470 0x17059	/* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
@@ -584,15 +595,18 @@ pinctrl_usdhc4_1: usdhc4grp-1 {
 							1493 0x17059	/* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
 							1501 0x17059	/* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
 							1509 0x17059	/* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
-							    1517 0x17059>;	/* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+							1517 0x17059	/* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+						>;
 					};
 				};
 
 				ecspi1 {
 					pinctrl_ecspi1_1: ecspi1grp-1 {
-						fsl,pins = <101 0x100b1		/* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+						fsl,pins = <
+							101 0x100b1	/* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
 							109 0x100b1	/* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
-							    94  0x100b1>;	/* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+							94  0x100b1	/* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+						>;
 					};
 				};
 			};