Commit 44b37eb7 authored by leilk.liu's avatar leilk.liu Committed by Mark Brown

spi: mediatek: use correct SPI_CFG2_REG MACRO

this patch use correct SPI_CFG2_REG offset.
Signed-off-by: default avatarleilk.liu <leilk.liu@mediatek.com>
Link: https://lore.kernel.org/r/20200701090020.7935-1-leilk.liu@mediatek.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent cf961fce
...@@ -36,7 +36,6 @@ ...@@ -36,7 +36,6 @@
#define SPI_CFG0_SCK_LOW_OFFSET 8 #define SPI_CFG0_SCK_LOW_OFFSET 8
#define SPI_CFG0_CS_HOLD_OFFSET 16 #define SPI_CFG0_CS_HOLD_OFFSET 16
#define SPI_CFG0_CS_SETUP_OFFSET 24 #define SPI_CFG0_CS_SETUP_OFFSET 24
#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
...@@ -48,6 +47,8 @@ ...@@ -48,6 +47,8 @@
#define SPI_CFG1_CS_IDLE_MASK 0xff #define SPI_CFG1_CS_IDLE_MASK 0xff
#define SPI_CFG1_PACKET_LOOP_MASK 0xff00 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
#define SPI_CFG2_SCK_HIGH_OFFSET 0
#define SPI_CFG2_SCK_LOW_OFFSET 16
#define SPI_CMD_ACT BIT(0) #define SPI_CMD_ACT BIT(0)
#define SPI_CMD_RESUME BIT(1) #define SPI_CMD_RESUME BIT(1)
...@@ -283,7 +284,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable) ...@@ -283,7 +284,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
static void mtk_spi_prepare_transfer(struct spi_master *master, static void mtk_spi_prepare_transfer(struct spi_master *master,
struct spi_transfer *xfer) struct spi_transfer *xfer)
{ {
u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0; u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
struct mtk_spi *mdata = spi_master_get_devdata(master); struct mtk_spi *mdata = spi_master_get_devdata(master);
spi_clk_hz = clk_get_rate(mdata->spi_clk); spi_clk_hz = clk_get_rate(mdata->spi_clk);
...@@ -296,18 +297,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master, ...@@ -296,18 +297,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master,
cs_time = sck_time * 2; cs_time = sck_time * 2;
if (mdata->dev_comp->enhance_timing) { if (mdata->dev_comp->enhance_timing) {
reg_val = (((sck_time - 1) & 0xffff)
<< SPI_CFG2_SCK_HIGH_OFFSET);
reg_val |= (((sck_time - 1) & 0xffff) reg_val |= (((sck_time - 1) & 0xffff)
<< SPI_CFG0_SCK_HIGH_OFFSET); << SPI_CFG2_SCK_LOW_OFFSET);
reg_val |= (((sck_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
writel(reg_val, mdata->base + SPI_CFG2_REG); writel(reg_val, mdata->base + SPI_CFG2_REG);
reg_val |= (((cs_time - 1) & 0xffff) reg_val = (((cs_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET); << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
reg_val |= (((cs_time - 1) & 0xffff) reg_val |= (((cs_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET); << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
writel(reg_val, mdata->base + SPI_CFG0_REG); writel(reg_val, mdata->base + SPI_CFG0_REG);
} else { } else {
reg_val |= (((sck_time - 1) & 0xff) reg_val = (((sck_time - 1) & 0xff)
<< SPI_CFG0_SCK_HIGH_OFFSET); << SPI_CFG0_SCK_HIGH_OFFSET);
reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
......
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