Commit 44cd9050 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'renesas-fixes-for-v5.1' of...

Merge tag 'renesas-fixes-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/fixes

Renesas ARM Based SoC Fixes for v5.1

R-Car Gen3 E3 (r8a77990) and RZ/G2E (r8a774c0) SoCs:
* Correct SCIF5 DMA channels

* tag 'renesas-fixes-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: renesas: r8a774c0: Fix SCIF5 DMA channels
  arm64: dts: renesas: r8a77990: Fix SCIF5 DMA channels
parents 2dbed152 c21cd4ae
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* Device Tree Source for the RZ/G2E (R8A774C0) SoC * Device Tree Source for the RZ/G2E (R8A774C0) SoC
* *
* Copyright (C) 2018 Renesas Electronics Corp. * Copyright (C) 2018-2019 Renesas Electronics Corp.
*/ */
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h> #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
...@@ -1150,9 +1150,8 @@ scif5: serial@e6f30000 { ...@@ -1150,9 +1150,8 @@ scif5: serial@e6f30000 {
<&cpg CPG_CORE R8A774C0_CLK_S3D1C>, <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
<&dmac2 0x5b>, <&dmac2 0x5a>; dma-names = "tx", "rx";
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 202>; resets = <&cpg 202>;
status = "disabled"; status = "disabled";
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* Device Tree Source for the R-Car E3 (R8A77990) SoC * Device Tree Source for the R-Car E3 (R8A77990) SoC
* *
* Copyright (C) 2018 Renesas Electronics Corp. * Copyright (C) 2018-2019 Renesas Electronics Corp.
*/ */
#include <dt-bindings/clock/r8a77990-cpg-mssr.h> #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
...@@ -1067,9 +1067,8 @@ scif5: serial@e6f30000 { ...@@ -1067,9 +1067,8 @@ scif5: serial@e6f30000 {
<&cpg CPG_CORE R8A77990_CLK_S3D1C>, <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
<&dmac2 0x5b>, <&dmac2 0x5a>; dma-names = "tx", "rx";
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 202>; resets = <&cpg 202>;
status = "disabled"; status = "disabled";
......
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