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Commit 45acc86b authored by Takashi Iwai's avatar Takashi Iwai
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Merge branch 'topic/hda-ca0132-dsp' into for-next

parents 0186f4f4 24f3cede
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sound/pci/hda/Kconfig
View file @ 45acc86b
......@@ -15,6 +15,9 @@ menuconfig SND_HDA_INTEL
if SND_HDA_INTEL
config SND_HDA_DSP_LOADER
bool
config SND_HDA_PREALLOC_SIZE
int "Pre-allocated buffer size for HD-audio driver"
range 0 32768
......@@ -200,6 +203,17 @@ config SND_HDA_CODEC_CA0132
snd-hda-codec-ca0132.
This module is automatically loaded at probing.
config SND_HDA_CODEC_CA0132_DSP
bool "Support new DSP code for CA0132 codec"
depends on SND_HDA_CODEC_CA0132 && FW_LOADER
select SND_HDA_DSP_LOADER
help
Say Y here to enable the DSP for Creative CA0132 for extended
features like equalizer or echo cancellation.
Note that this option requires the external firmware file
(ctefx.bin).
config SND_HDA_CODEC_CMEDIA
bool "Build C-Media HD-audio codec support"
default y
......
sound/pci/hda/ca0132_regs.h 0 → 100644
View file @ 45acc86b
/*
* HD audio interface patch for Creative CA0132 chip.
* CA0132 registers defines.
*
* Copyright (c) 2011, Creative Technology Ltd.
*
* This driver is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This driver is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __CA0132_REGS_H
#define __CA0312_REGS_H
#define DSP_CHIP_OFFSET 0x100000
#define DSP_DBGCNTL_MODULE_OFFSET 0xE30
#define DSP_DBGCNTL_INST_OFFSET \
(DSP_CHIP_OFFSET + DSP_DBGCNTL_MODULE_OFFSET)
#define DSP_DBGCNTL_EXEC_LOBIT 0x0
#define DSP_DBGCNTL_EXEC_HIBIT 0x3
#define DSP_DBGCNTL_EXEC_MASK 0xF
#define DSP_DBGCNTL_SS_LOBIT 0x4
#define DSP_DBGCNTL_SS_HIBIT 0x7
#define DSP_DBGCNTL_SS_MASK 0xF0
#define DSP_DBGCNTL_STATE_LOBIT 0xA
#define DSP_DBGCNTL_STATE_HIBIT 0xD
#define DSP_DBGCNTL_STATE_MASK 0x3C00
#define XRAM_CHIP_OFFSET 0x0
#define XRAM_XRAM_CHANNEL_COUNT 0xE000
#define XRAM_XRAM_MODULE_OFFSET 0x0
#define XRAM_XRAM_CHAN_INCR 4
#define XRAM_XRAM_INST_OFFSET(_chan) \
(XRAM_CHIP_OFFSET + XRAM_XRAM_MODULE_OFFSET + \
(_chan * XRAM_XRAM_CHAN_INCR))
#define YRAM_CHIP_OFFSET 0x40000
#define YRAM_YRAM_CHANNEL_COUNT 0x8000
#define YRAM_YRAM_MODULE_OFFSET 0x0
#define YRAM_YRAM_CHAN_INCR 4
#define YRAM_YRAM_INST_OFFSET(_chan) \
(YRAM_CHIP_OFFSET + YRAM_YRAM_MODULE_OFFSET + \
(_chan * YRAM_YRAM_CHAN_INCR))
#define UC_CHIP_OFFSET 0x80000
#define UC_UC_CHANNEL_COUNT 0x10000
#define UC_UC_MODULE_OFFSET 0x0
#define UC_UC_CHAN_INCR 4
#define UC_UC_INST_OFFSET(_chan) \
(UC_CHIP_OFFSET + UC_UC_MODULE_OFFSET + \
(_chan * UC_UC_CHAN_INCR))
#define AXRAM_CHIP_OFFSET 0x3C000
#define AXRAM_AXRAM_CHANNEL_COUNT 0x1000
#define AXRAM_AXRAM_MODULE_OFFSET 0x0
#define AXRAM_AXRAM_CHAN_INCR 4
#define AXRAM_AXRAM_INST_OFFSET(_chan) \
(AXRAM_CHIP_OFFSET + AXRAM_AXRAM_MODULE_OFFSET + \
(_chan * AXRAM_AXRAM_CHAN_INCR))
#define AYRAM_CHIP_OFFSET 0x78000
#define AYRAM_AYRAM_CHANNEL_COUNT 0x1000
#define AYRAM_AYRAM_MODULE_OFFSET 0x0
#define AYRAM_AYRAM_CHAN_INCR 4
#define AYRAM_AYRAM_INST_OFFSET(_chan) \
(AYRAM_CHIP_OFFSET + AYRAM_AYRAM_MODULE_OFFSET + \
(_chan * AYRAM_AYRAM_CHAN_INCR))
#define DSPDMAC_CHIP_OFFSET 0x110000
#define DSPDMAC_DMA_CFG_CHANNEL_COUNT 12
#define DSPDMAC_DMACFG_MODULE_OFFSET 0xF00
#define DSPDMAC_DMACFG_CHAN_INCR 0x10
#define DSPDMAC_DMACFG_INST_OFFSET(_chan) \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_DMACFG_MODULE_OFFSET + \
(_chan * DSPDMAC_DMACFG_CHAN_INCR))
#define DSPDMAC_DMACFG_DBADR_LOBIT 0x0
#define DSPDMAC_DMACFG_DBADR_HIBIT 0x10
#define DSPDMAC_DMACFG_DBADR_MASK 0x1FFFF
#define DSPDMAC_DMACFG_LP_LOBIT 0x11
#define DSPDMAC_DMACFG_LP_HIBIT 0x11
#define DSPDMAC_DMACFG_LP_MASK 0x20000
#define DSPDMAC_DMACFG_AINCR_LOBIT 0x12
#define DSPDMAC_DMACFG_AINCR_HIBIT 0x12
#define DSPDMAC_DMACFG_AINCR_MASK 0x40000
#define DSPDMAC_DMACFG_DWR_LOBIT 0x13
#define DSPDMAC_DMACFG_DWR_HIBIT 0x13
#define DSPDMAC_DMACFG_DWR_MASK 0x80000
#define DSPDMAC_DMACFG_AJUMP_LOBIT 0x14
#define DSPDMAC_DMACFG_AJUMP_HIBIT 0x17
#define DSPDMAC_DMACFG_AJUMP_MASK 0xF00000
#define DSPDMAC_DMACFG_AMODE_LOBIT 0x18
#define DSPDMAC_DMACFG_AMODE_HIBIT 0x19
#define DSPDMAC_DMACFG_AMODE_MASK 0x3000000
#define DSPDMAC_DMACFG_LK_LOBIT 0x1A
#define DSPDMAC_DMACFG_LK_HIBIT 0x1A
#define DSPDMAC_DMACFG_LK_MASK 0x4000000
#define DSPDMAC_DMACFG_AICS_LOBIT 0x1B
#define DSPDMAC_DMACFG_AICS_HIBIT 0x1F
#define DSPDMAC_DMACFG_AICS_MASK 0xF8000000
#define DSPDMAC_DMACFG_LP_SINGLE 0
#define DSPDMAC_DMACFG_LP_LOOPING 1
#define DSPDMAC_DMACFG_AINCR_XANDY 0
#define DSPDMAC_DMACFG_AINCR_XORY 1
#define DSPDMAC_DMACFG_DWR_DMA_RD 0
#define DSPDMAC_DMACFG_DWR_DMA_WR 1
#define DSPDMAC_DMACFG_AMODE_LINEAR 0
#define DSPDMAC_DMACFG_AMODE_RSV1 1
#define DSPDMAC_DMACFG_AMODE_WINTLV 2
#define DSPDMAC_DMACFG_AMODE_GINTLV 3
#define DSPDMAC_DSP_ADR_OFS_CHANNEL_COUNT 12
#define DSPDMAC_DSPADROFS_MODULE_OFFSET 0xF04
#define DSPDMAC_DSPADROFS_CHAN_INCR 0x10
#define DSPDMAC_DSPADROFS_INST_OFFSET(_chan) \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADROFS_MODULE_OFFSET + \
(_chan * DSPDMAC_DSPADROFS_CHAN_INCR))
#define DSPDMAC_DSPADROFS_COFS_LOBIT 0x0
#define DSPDMAC_DSPADROFS_COFS_HIBIT 0xF
#define DSPDMAC_DSPADROFS_COFS_MASK 0xFFFF
#define DSPDMAC_DSPADROFS_BOFS_LOBIT 0x10
#define DSPDMAC_DSPADROFS_BOFS_HIBIT 0x1F
#define DSPDMAC_DSPADROFS_BOFS_MASK 0xFFFF0000
#define DSPDMAC_DSP_ADR_WOFS_CHANNEL_COUNT 12
#define DSPDMAC_DSPADRWOFS_MODULE_OFFSET 0xF04
#define DSPDMAC_DSPADRWOFS_CHAN_INCR 0x10
#define DSPDMAC_DSPADRWOFS_INST_OFFSET(_chan) \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADRWOFS_MODULE_OFFSET + \
(_chan * DSPDMAC_DSPADRWOFS_CHAN_INCR))
#define DSPDMAC_DSPADRWOFS_WCOFS_LOBIT 0x0
#define DSPDMAC_DSPADRWOFS_WCOFS_HIBIT 0xA
#define DSPDMAC_DSPADRWOFS_WCOFS_MASK 0x7FF
#define DSPDMAC_DSPADRWOFS_WCBFR_LOBIT 0xB
#define DSPDMAC_DSPADRWOFS_WCBFR_HIBIT 0xF
#define DSPDMAC_DSPADRWOFS_WCBFR_MASK 0xF800
#define DSPDMAC_DSPADRWOFS_WBOFS_LOBIT 0x10
#define DSPDMAC_DSPADRWOFS_WBOFS_HIBIT 0x1A
#define DSPDMAC_DSPADRWOFS_WBOFS_MASK 0x7FF0000
#define DSPDMAC_DSPADRWOFS_WBBFR_LOBIT 0x1B
#define DSPDMAC_DSPADRWOFS_WBBFR_HIBIT 0x1F
#define DSPDMAC_DSPADRWOFS_WBBFR_MASK 0xF8000000
#define DSPDMAC_DSP_ADR_GOFS_CHANNEL_COUNT 12
#define DSPDMAC_DSPADRGOFS_MODULE_OFFSET 0xF04
#define DSPDMAC_DSPADRGOFS_CHAN_INCR 0x10
#define DSPDMAC_DSPADRGOFS_INST_OFFSET(_chan) \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADRGOFS_MODULE_OFFSET + \
(_chan * DSPDMAC_DSPADRGOFS_CHAN_INCR))
#define DSPDMAC_DSPADRGOFS_GCOFS_LOBIT 0x0
#define DSPDMAC_DSPADRGOFS_GCOFS_HIBIT 0x9
#define DSPDMAC_DSPADRGOFS_GCOFS_MASK 0x3FF
#define DSPDMAC_DSPADRGOFS_GCS_LOBIT 0xA
#define DSPDMAC_DSPADRGOFS_GCS_HIBIT 0xC
#define DSPDMAC_DSPADRGOFS_GCS_MASK 0x1C00
#define DSPDMAC_DSPADRGOFS_GCBFR_LOBIT 0xD
#define DSPDMAC_DSPADRGOFS_GCBFR_HIBIT 0xF
#define DSPDMAC_DSPADRGOFS_GCBFR_MASK 0xE000
#define DSPDMAC_DSPADRGOFS_GBOFS_LOBIT 0x10
#define DSPDMAC_DSPADRGOFS_GBOFS_HIBIT 0x19
#define DSPDMAC_DSPADRGOFS_GBOFS_MASK 0x3FF0000
#define DSPDMAC_DSPADRGOFS_GBS_LOBIT 0x1A
#define DSPDMAC_DSPADRGOFS_GBS_HIBIT 0x1C
#define DSPDMAC_DSPADRGOFS_GBS_MASK 0x1C000000
#define DSPDMAC_DSPADRGOFS_GBBFR_LOBIT 0x1D
#define DSPDMAC_DSPADRGOFS_GBBFR_HIBIT 0x1F
#define DSPDMAC_DSPADRGOFS_GBBFR_MASK 0xE0000000
#define DSPDMAC_XFR_CNT_CHANNEL_COUNT 12
#define DSPDMAC_XFRCNT_MODULE_OFFSET 0xF08
#define DSPDMAC_XFRCNT_CHAN_INCR 0x10
#define DSPDMAC_XFRCNT_INST_OFFSET(_chan) \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_XFRCNT_MODULE_OFFSET + \
(_chan * DSPDMAC_XFRCNT_CHAN_INCR))
#define DSPDMAC_XFRCNT_CCNT_LOBIT 0x0
#define DSPDMAC_XFRCNT_CCNT_HIBIT 0xF
#define DSPDMAC_XFRCNT_CCNT_MASK 0xFFFF
#define DSPDMAC_XFRCNT_BCNT_LOBIT 0x10
#define DSPDMAC_XFRCNT_BCNT_HIBIT 0x1F
#define DSPDMAC_XFRCNT_BCNT_MASK 0xFFFF0000
#define DSPDMAC_IRQ_CNT_CHANNEL_COUNT 12
#define DSPDMAC_IRQCNT_MODULE_OFFSET 0xF0C
#define DSPDMAC_IRQCNT_CHAN_INCR 0x10
#define DSPDMAC_IRQCNT_INST_OFFSET(_chan) \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_IRQCNT_MODULE_OFFSET + \
(_chan * DSPDMAC_IRQCNT_CHAN_INCR))
#define DSPDMAC_IRQCNT_CICNT_LOBIT 0x0
#define DSPDMAC_IRQCNT_CICNT_HIBIT 0xF
#define DSPDMAC_IRQCNT_CICNT_MASK 0xFFFF
#define DSPDMAC_IRQCNT_BICNT_LOBIT 0x10
#define DSPDMAC_IRQCNT_BICNT_HIBIT 0x1F
#define DSPDMAC_IRQCNT_BICNT_MASK 0xFFFF0000
#define DSPDMAC_AUD_CHSEL_CHANNEL_COUNT 12
#define DSPDMAC_AUDCHSEL_MODULE_OFFSET 0xFC0
#define DSPDMAC_AUDCHSEL_CHAN_INCR 0x4
#define DSPDMAC_AUDCHSEL_INST_OFFSET(_chan) \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_AUDCHSEL_MODULE_OFFSET + \
(_chan * DSPDMAC_AUDCHSEL_CHAN_INCR))
#define DSPDMAC_AUDCHSEL_ACS_LOBIT 0x0
#define DSPDMAC_AUDCHSEL_ACS_HIBIT 0x1F
#define DSPDMAC_AUDCHSEL_ACS_MASK 0xFFFFFFFF
#define DSPDMAC_CHNLSTART_MODULE_OFFSET 0xFF0
#define DSPDMAC_CHNLSTART_INST_OFFSET \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLSTART_MODULE_OFFSET)
#define DSPDMAC_CHNLSTART_EN_LOBIT 0x0
#define DSPDMAC_CHNLSTART_EN_HIBIT 0xB
#define DSPDMAC_CHNLSTART_EN_MASK 0xFFF
#define DSPDMAC_CHNLSTART_VAI1_LOBIT 0xC
#define DSPDMAC_CHNLSTART_VAI1_HIBIT 0xF
#define DSPDMAC_CHNLSTART_VAI1_MASK 0xF000
#define DSPDMAC_CHNLSTART_DIS_LOBIT 0x10
#define DSPDMAC_CHNLSTART_DIS_HIBIT 0x1B
#define DSPDMAC_CHNLSTART_DIS_MASK 0xFFF0000
#define DSPDMAC_CHNLSTART_VAI2_LOBIT 0x1C
#define DSPDMAC_CHNLSTART_VAI2_HIBIT 0x1F
#define DSPDMAC_CHNLSTART_VAI2_MASK 0xF0000000
#define DSPDMAC_CHNLSTATUS_MODULE_OFFSET 0xFF4
#define DSPDMAC_CHNLSTATUS_INST_OFFSET \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLSTATUS_MODULE_OFFSET)
#define DSPDMAC_CHNLSTATUS_ISC_LOBIT 0x0
#define DSPDMAC_CHNLSTATUS_ISC_HIBIT 0xB
#define DSPDMAC_CHNLSTATUS_ISC_MASK 0xFFF
#define DSPDMAC_CHNLSTATUS_AOO_LOBIT 0xC
#define DSPDMAC_CHNLSTATUS_AOO_HIBIT 0xC
#define DSPDMAC_CHNLSTATUS_AOO_MASK 0x1000
#define DSPDMAC_CHNLSTATUS_AOU_LOBIT 0xD
#define DSPDMAC_CHNLSTATUS_AOU_HIBIT 0xD
#define DSPDMAC_CHNLSTATUS_AOU_MASK 0x2000
#define DSPDMAC_CHNLSTATUS_AIO_LOBIT 0xE
#define DSPDMAC_CHNLSTATUS_AIO_HIBIT 0xE
#define DSPDMAC_CHNLSTATUS_AIO_MASK 0x4000
#define DSPDMAC_CHNLSTATUS_AIU_LOBIT 0xF
#define DSPDMAC_CHNLSTATUS_AIU_HIBIT 0xF
#define DSPDMAC_CHNLSTATUS_AIU_MASK 0x8000
#define DSPDMAC_CHNLSTATUS_IEN_LOBIT 0x10
#define DSPDMAC_CHNLSTATUS_IEN_HIBIT 0x1B
#define DSPDMAC_CHNLSTATUS_IEN_MASK 0xFFF0000
#define DSPDMAC_CHNLSTATUS_VAI0_LOBIT 0x1C
#define DSPDMAC_CHNLSTATUS_VAI0_HIBIT 0x1F
#define DSPDMAC_CHNLSTATUS_VAI0_MASK 0xF0000000
#define DSPDMAC_CHNLPROP_MODULE_OFFSET 0xFF8
#define DSPDMAC_CHNLPROP_INST_OFFSET \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLPROP_MODULE_OFFSET)
#define DSPDMAC_CHNLPROP_DCON_LOBIT 0x0
#define DSPDMAC_CHNLPROP_DCON_HIBIT 0xB
#define DSPDMAC_CHNLPROP_DCON_MASK 0xFFF
#define DSPDMAC_CHNLPROP_FFS_LOBIT 0xC
#define DSPDMAC_CHNLPROP_FFS_HIBIT 0xC
#define DSPDMAC_CHNLPROP_FFS_MASK 0x1000
#define DSPDMAC_CHNLPROP_NAJ_LOBIT 0xD
#define DSPDMAC_CHNLPROP_NAJ_HIBIT 0xD
#define DSPDMAC_CHNLPROP_NAJ_MASK 0x2000
#define DSPDMAC_CHNLPROP_ENH_LOBIT 0xE
#define DSPDMAC_CHNLPROP_ENH_HIBIT 0xE
#define DSPDMAC_CHNLPROP_ENH_MASK 0x4000
#define DSPDMAC_CHNLPROP_MSPCE_LOBIT 0x10
#define DSPDMAC_CHNLPROP_MSPCE_HIBIT 0x1B
#define DSPDMAC_CHNLPROP_MSPCE_MASK 0xFFF0000
#define DSPDMAC_CHNLPROP_AC_LOBIT 0x1C
#define DSPDMAC_CHNLPROP_AC_HIBIT 0x1F
#define DSPDMAC_CHNLPROP_AC_MASK 0xF0000000
#define DSPDMAC_ACTIVE_MODULE_OFFSET 0xFFC
#define DSPDMAC_ACTIVE_INST_OFFSET \
(DSPDMAC_CHIP_OFFSET + DSPDMAC_ACTIVE_MODULE_OFFSET)
#define DSPDMAC_ACTIVE_AAR_LOBIT 0x0
#define DSPDMAC_ACTIVE_AAR_HIBIT 0xB
#define DSPDMAC_ACTIVE_AAR_MASK 0xFFF
#define DSPDMAC_ACTIVE_WFR_LOBIT 0xC
#define DSPDMAC_ACTIVE_WFR_HIBIT 0x17
#define DSPDMAC_ACTIVE_WFR_MASK 0xFFF000
#define DSP_AUX_MEM_BASE 0xE000
#define INVALID_CHIP_ADDRESS (~0UL)
#define X_SIZE (XRAM_XRAM_CHANNEL_COUNT * XRAM_XRAM_CHAN_INCR)
#define Y_SIZE (YRAM_YRAM_CHANNEL_COUNT * YRAM_YRAM_CHAN_INCR)
#define AX_SIZE (AXRAM_AXRAM_CHANNEL_COUNT * AXRAM_AXRAM_CHAN_INCR)
#define AY_SIZE (AYRAM_AYRAM_CHANNEL_COUNT * AYRAM_AYRAM_CHAN_INCR)
#define UC_SIZE (UC_UC_CHANNEL_COUNT * UC_UC_CHAN_INCR)
#define XEXT_SIZE (X_SIZE + AX_SIZE)
#define YEXT_SIZE (Y_SIZE + AY_SIZE)
#define U64K 0x10000UL
#define X_END (XRAM_CHIP_OFFSET + X_SIZE)
#define X_EXT (XRAM_CHIP_OFFSET + XEXT_SIZE)
#define AX_END (XRAM_CHIP_OFFSET + U64K*4)
#define Y_END (YRAM_CHIP_OFFSET + Y_SIZE)
#define Y_EXT (YRAM_CHIP_OFFSET + YEXT_SIZE)
#define AY_END (YRAM_CHIP_OFFSET + U64K*4)
#define UC_END (UC_CHIP_OFFSET + UC_SIZE)
#define X_RANGE_MAIN(a, s) \
(((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < X_END))
#define X_RANGE_AUX(a, s) \
(((a) >= X_END) && ((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END))
#define X_RANGE_EXT(a, s) \
(((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < X_EXT))
#define X_RANGE_ALL(a, s) \
(((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END))
#define Y_RANGE_MAIN(a, s) \
(((a) >= YRAM_CHIP_OFFSET) && \
((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < Y_END))
#define Y_RANGE_AUX(a, s) \
(((a) >= Y_END) && \
((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END))
#define Y_RANGE_EXT(a, s) \
(((a) >= YRAM_CHIP_OFFSET) && \
((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < Y_EXT))
#define Y_RANGE_ALL(a, s) \
(((a) >= YRAM_CHIP_OFFSET) && \
((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END))
#define UC_RANGE(a, s) \
(((a) >= UC_CHIP_OFFSET) && \
((a)+((s)-1)*UC_UC_CHAN_INCR < UC_END))
#define X_OFF(a) \
(((a) - XRAM_CHIP_OFFSET) / XRAM_XRAM_CHAN_INCR)
#define AX_OFF(a) \
(((a) % (AXRAM_AXRAM_CHANNEL_COUNT * \
AXRAM_AXRAM_CHAN_INCR)) / AXRAM_AXRAM_CHAN_INCR)
#define Y_OFF(a) \
(((a) - YRAM_CHIP_OFFSET) / YRAM_YRAM_CHAN_INCR)
#define AY_OFF(a) \
(((a) % (AYRAM_AYRAM_CHANNEL_COUNT * \
AYRAM_AYRAM_CHAN_INCR)) / AYRAM_AYRAM_CHAN_INCR)
#define UC_OFF(a) (((a) - UC_CHIP_OFFSET) / UC_UC_CHAN_INCR)
#define X_EXT_MAIN_SIZE(a) (XRAM_XRAM_CHANNEL_COUNT - X_OFF(a))
#define X_EXT_AUX_SIZE(a, s) ((s) - X_EXT_MAIN_SIZE(a))
#define Y_EXT_MAIN_SIZE(a) (YRAM_YRAM_CHANNEL_COUNT - Y_OFF(a))
#define Y_EXT_AUX_SIZE(a, s) ((s) - Y_EXT_MAIN_SIZE(a))
#endif
sound/pci/hda/hda_codec.h
View file @ 45acc86b
......@@ -618,6 +618,17 @@ struct hda_bus_ops {
/* notify power-up/down from codec to controller */
void (*pm_notify)(struct hda_bus *bus, bool power_up);
#endif
#ifdef CONFIG_SND_HDA_DSP_LOADER
/* prepare DSP transfer */
int (*load_dsp_prepare)(struct hda_bus *bus, unsigned int format,
unsigned int byte_size,
struct snd_dma_buffer *bufp);
/* start/stop DSP transfer */
void (*load_dsp_trigger)(struct hda_bus *bus, bool start);
/* clean up DSP transfer */
void (*load_dsp_cleanup)(struct hda_bus *bus,
struct snd_dma_buffer *dmab);
#endif
};
/* template to pass to the bus constructor */
......@@ -1150,6 +1161,40 @@ static inline void snd_hda_power_sync(struct hda_codec *codec)
int snd_hda_load_patch(struct hda_bus *bus, size_t size, const void *buf);
#endif
#ifdef CONFIG_SND_HDA_DSP_LOADER
static inline int
snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
unsigned int size,
struct snd_dma_buffer *bufp)
{
return codec->bus->ops.load_dsp_prepare(codec->bus, format, size, bufp);
}
static inline void
snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
{
return codec->bus->ops.load_dsp_trigger(codec->bus, start);
}
static inline void
snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
struct snd_dma_buffer *dmab)
{
return codec->bus->ops.load_dsp_cleanup(codec->bus, dmab);
}
#else
static inline int
snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
unsigned int size,
struct snd_dma_buffer *bufp)
{
return -ENOSYS;
}
static inline void
snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start) {}
static inline void
snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
struct snd_dma_buffer *dmab) {}
#endif
/*
* Codec modularization
*/
......
sound/pci/hda/hda_intel.c
View file @ 45acc86b
......@@ -1085,6 +1085,15 @@ static unsigned int azx_get_response(struct hda_bus *bus,
static void azx_power_notify(struct hda_bus *bus, bool power_up);
#endif
#ifdef CONFIG_SND_HDA_DSP_LOADER
static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
unsigned int byte_size,
struct snd_dma_buffer *bufp);
static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
static void azx_load_dsp_cleanup(struct hda_bus *bus,
struct snd_dma_buffer *dmab);
#endif
/* reset codec link */
static int azx_reset(struct azx *chip, int full_reset)
{
......@@ -1408,7 +1417,7 @@ static irqreturn_t azx_interrupt(int irq, void *dev_id)
* set up a BDL entry
*/
static int setup_bdle(struct azx *chip,
struct snd_pcm_substream *substream,
struct snd_dma_buffer *dmab,
struct azx_dev *azx_dev, u32 **bdlp,
int ofs, int size, int with_ioc)
{
......@@ -1421,12 +1430,12 @@ static int setup_bdle(struct azx *chip,
if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
return -EINVAL;
addr = snd_pcm_sgbuf_get_addr(substream, ofs);
addr = snd_sgbuf_get_addr(dmab, ofs);
/* program the address field of the BDL entry */
bdl[0] = cpu_to_le32((u32)addr);
bdl[1] = cpu_to_le32(upper_32_bits(addr));
/* program the size field of the BDL entry */
chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
/* one BDLE cannot cross 4K boundary on CTHDA chips */
if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
u32 remain = 0x1000 - (ofs & 0xfff);
......@@ -1485,7 +1494,8 @@ static int azx_setup_periods(struct azx *chip,
pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
pos_adj = 0;
} else {
ofs = setup_bdle(chip, substream, azx_dev,
ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
azx_dev,
&bdl, ofs, pos_adj, true);
if (ofs < 0)
goto error;
......@@ -1494,10 +1504,12 @@ static int azx_setup_periods(struct azx *chip,
pos_adj = 0;
for (i = 0; i < periods; i++) {
if (i == periods - 1 && pos_adj)
ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
azx_dev, &bdl, ofs,
period_bytes - pos_adj, 0);
else
ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
azx_dev, &bdl, ofs,
period_bytes,
!azx_dev->no_period_wakeup);
if (ofs < 0)
......@@ -1675,6 +1687,11 @@ static int azx_codec_create(struct azx *chip, const char *model)
bus_temp.power_save = &power_save;
bus_temp.ops.pm_notify = azx_power_notify;
#endif
#ifdef CONFIG_SND_HDA_DSP_LOADER
bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
#endif
err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
if (err < 0)
......@@ -2583,6 +2600,93 @@ static void azx_stop_chip(struct azx *chip)
chip->initialized = 0;
}
#ifdef CONFIG_SND_HDA_DSP_LOADER
/*
* DSP loading code (e.g. for CA0132)
*/
/* use the first stream for loading DSP */
static struct azx_dev *
azx_get_dsp_loader_dev(struct azx *chip)
{
return &chip->azx_dev[chip->playback_index_offset];
}
static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
unsigned int byte_size,
struct snd_dma_buffer *bufp)
{
u32 *bdl;
struct azx *chip = bus->private_data;
struct azx_dev *azx_dev;
int err;
if (snd_hda_lock_devices(bus))
return -EBUSY;
err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
snd_dma_pci_data(chip->pci),
byte_size, bufp);
if (err < 0)
goto error;
azx_dev = azx_get_dsp_loader_dev(chip);
azx_dev->bufsize = byte_size;
azx_dev->period_bytes = byte_size;
azx_dev->format_val = format;
azx_stream_reset(chip, azx_dev);
/* reset BDL address */
azx_sd_writel(azx_dev, SD_BDLPL, 0);
azx_sd_writel(azx_dev, SD_BDLPU, 0);
azx_dev->frags = 0;
bdl = (u32 *)azx_dev->bdl.area;
err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
if (err < 0)
goto error;
azx_setup_controller(chip, azx_dev);
return azx_dev->stream_tag;
error:
snd_hda_unlock_devices(bus);
return err;
}
static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
{
struct azx *chip = bus->private_data;
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
if (start)
azx_stream_start(chip, azx_dev);
else
azx_stream_stop(chip, azx_dev);
azx_dev->running = start;
}
static void azx_load_dsp_cleanup(struct hda_bus *bus,
struct snd_dma_buffer *dmab)
{
struct azx *chip = bus->private_data;
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
/* reset BDL address */
azx_sd_writel(azx_dev, SD_BDLPL, 0);
azx_sd_writel(azx_dev, SD_BDLPU, 0);
azx_sd_writel(azx_dev, SD_CTL, 0);
azx_dev->bufsize = 0;
azx_dev->period_bytes = 0;
azx_dev->format_val = 0;
snd_dma_free_pages(dmab);
snd_hda_unlock_devices(bus);
}
#endif /* CONFIG_SND_HDA_DSP_LOADER */
#ifdef CONFIG_PM
/* power-up/down the controller */
static void azx_power_notify(struct hda_bus *bus, bool power_up)
......
sound/pci/hda/patch_ca0132.c
View file @ 45acc86b
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