[SPARC64]: Fix _PAGE_EXEC handling.

First of all, use the known _PAGE_EXEC_{4U,4V} value instead
of loading _PAGE_EXEC from memory.  We either know which one
to use by context, or we can code patch the test.

Next, we need to check executability of a PTE in the generic
TSB miss handler.
Signed-off-by: David S. Miller <davem@davemloft.net>

arch/sparc64/kernel/itlb_miss.S

@@ -9,18 +9,18 @@
 	cmp	%g4, %g6			! Compare TAG
 
 /* ITLB ** ICACHE line 2: TSB compare and TLB load	*/
-	sethi	%hi(PAGE_EXEC), %g4		! Setup exec check
-	ldx	[%g4 + %lo(PAGE_EXEC)], %g4
 	bne,pn	%xcc, tsb_miss_itlb		! Miss
 	 mov	FAULT_CODE_ITLB, %g3
-	andcc	%g5, %g4, %g0			! Executable?
+	andcc	%g5, _PAGE_EXEC_4U, %g0		! Executable?
 	be,pn	%xcc, tsb_do_fault
 	 nop					! Delay slot, fill me
+	stxa	%g5, [%g0] ASI_ITLB_DATA_IN	! Load TLB
+	retry					! Trap done
 	nop
 
 /* ITLB ** ICACHE line 3: 				*/
-	stxa	%g5, [%g0] ASI_ITLB_DATA_IN	! Load TLB
-	retry					! Trap done
+	nop
+	nop
 	nop
 	nop
 	nop

arch/sparc64/kernel/sun4v_tlb_miss.S

@@ -58,11 +58,9 @@ sun4v_itlb_miss:
 	/* Load TSB tag/pte into %g2/%g3 and compare the tag.  */
 	ldda	[%g1] ASI_QUAD_LDD_PHYS_4V, %g2
 	cmp	%g2, %g6
-	sethi	%hi(PAGE_EXEC), %g7
-	ldx	[%g7 + %lo(PAGE_EXEC)], %g7
 	bne,a,pn %xcc, tsb_miss_page_table_walk
 	 mov	FAULT_CODE_ITLB, %g3
-	andcc	%g3, %g7, %g0
+	andcc	%g3, _PAGE_EXEC_4V, %g0
 	be,a,pn	%xcc, tsb_do_fault
 	 mov	FAULT_CODE_ITLB, %g3
 

arch/sparc64/kernel/tsb.S

@@ -103,6 +103,15 @@ tsb_dtlb_load:
 	 mov		%g5, %g3
 
 tsb_itlb_load:
+	/* Executable bit must be set.  */
+661:	andcc		%g5, _PAGE_EXEC_4U, %g0
+	.section	.sun4v_1insn_patch, "ax"
+	.word		661b
+	andcc		%g5, _PAGE_EXEC_4V, %g0
+	.previous
+
+	be,pn		%xcc, tsb_do_fault
+	 nop
 
 661:	stxa		%g5, [%g0] ASI_ITLB_DATA_IN
 	retry