Commit 462c272b authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher

drm/amdgpu: add psp support for dimgrey_cavefish(v2)

General psp support for dimgrey_cavefish.

v2: remove the checks for asd load and reroute ih.
Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0a305e34
......@@ -101,6 +101,7 @@ static int psp_early_init(void *handle)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH:
psp_v11_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
......@@ -1968,8 +1969,8 @@ static int psp_np_fw_load(struct psp_context *psp)
continue;
if (psp->autoload_supported &&
(adev->asic_type == CHIP_SIENNA_CICHLID ||
adev->asic_type == CHIP_NAVY_FLOUNDER) &&
(adev->asic_type >= CHIP_SIENNA_CICHLID &&
adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
(ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
......
......@@ -61,6 +61,8 @@ MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_asd.bin");
/* address block */
#define smnMP1_FIRMWARE_FLAGS 0x3010024
......@@ -110,6 +112,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
case CHIP_VANGOGH:
chip_name = "vangogh";
break;
case CHIP_DIMGREY_CAVEFISH:
chip_name = "dimgrey_cavefish";
break;
default:
BUG();
}
......@@ -194,6 +199,14 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
if (err)
return err;
break;
case CHIP_DIMGREY_CAVEFISH:
err = psp_init_sos_microcode(psp, chip_name);
if (err)
return err;
err = psp_init_asd_microcode(psp, chip_name);
if (err)
return err;
break;
case CHIP_VANGOGH:
err = psp_init_asd_microcode(psp, chip_name);
if (err)
......
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