Commit 46828886 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/smu: add peak profile support for navi12

Add defined peak sclk for navi12 peak profile mode.
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d24d2654
...@@ -1628,6 +1628,9 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu) ...@@ -1628,6 +1628,9 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu)
break; break;
} }
break; break;
case CHIP_NAVI12:
sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
break;
default: default:
ret = smu_get_dpm_level_count(smu, SMU_SCLK, &sclk_level); ret = smu_get_dpm_level_count(smu, SMU_SCLK, &sclk_level);
if (ret) if (ret)
......
...@@ -33,6 +33,8 @@ ...@@ -33,6 +33,8 @@
#define NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK (1717) #define NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK (1717)
#define NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK (1448) #define NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK (1448)
#define NAVI12_UMD_PSTATE_PEAK_GFXCLK (1100)
#define NAVI10_VOLTAGE_SCALE (4) #define NAVI10_VOLTAGE_SCALE (4)
#define smnPCIE_LC_SPEED_CNTL 0x11140290 #define smnPCIE_LC_SPEED_CNTL 0x11140290
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment