Commit 47bcc8c0 authored by Fugang Duan's avatar Fugang Duan Committed by Shawn Guo

ARM: dts: imx7d-sdb: add fec1 and fec2 support

Enable fec1 and fec2 for i.MX7d-sdb board.
Signed-off-by: default avatarFugang Duan <B38611@freescale.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 5b8e6ed4
...@@ -101,6 +101,45 @@ &cpu0 { ...@@ -101,6 +101,45 @@ &cpu0 {
arm-supply = <&sw1a_reg>; arm-supply = <&sw1a_reg>;
}; };
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
};
&i2c1 { &i2c1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
...@@ -270,6 +309,42 @@ &iomuxc { ...@@ -270,6 +309,42 @@ &iomuxc {
pinctrl-0 = <&pinctrl_hog>; pinctrl-0 = <&pinctrl_hog>;
imx7d-sdb { imx7d-sdb {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
>;
};
pinctrl_hog: hoggrp { pinctrl_hog: hoggrp {
fsl,pins = < fsl,pins = <
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
...@@ -305,7 +380,6 @@ MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f ...@@ -305,7 +380,6 @@ MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
>; >;
}; };
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
......
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