Skip to content

L
linux
Commit 482612af authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files
Options

Staging: pata_rdc: coding style fixes 

This fixes a number of coding style issues in the pata_rdc.h file

Cc: Kevin Huang  <Kevin.Huang@rdc.com.tw>
Cc: Tomy Wang <Tomy.Wang@rdc.com.tw>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent b079fa27
Hide whitespace changes
Inline Side-by-side
Showing with 1012 additions and 1412 deletions
drivers/staging/pata_rdc/pata_rdc.c
View file @ 482612af
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
#include "pata_rdc.h" #include "pata_rdc.h"
//#define DBGPRINTF /* #define DBGPRINTF */
#ifdef DBGPRINTF #ifdef DBGPRINTF
...@@ -22,113 +22,111 @@ ...@@ -22,113 +22,111 @@
#endif #endif
// Driver Info. /* Driver Info. */
#define DRIVER_NAME "pata_rdc" /* sata_rdc for SATA */
#define DRIVER_NAME "pata_rdc" // sata_rdc for SATA #define DRIVER_VERSION "2.6.28" /* based on kernel version. */
#define DRIVER_VERSION "2.6.28" // based on kernel version. /* because each kernel main version has
// because each kernel main version has its libata, we follow kernel to determine the last libata version. * its libata, we follow kernel to
* determine the last libata version.
*/
static const struct pci_device_id rdc_pata_id_table[] = { static const struct pci_device_id rdc_pata_id_table[] = {
{ 0x17F3, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31011}, { 0x17F3, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31011},
{ 0x17F3, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31012}, { 0x17F3, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31012},
{ } /* terminate list */ { } /* terminate list */
}; };
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
MODULE_AUTHOR("this version author is RDC"); // replace "RDC" with the last maintainer. MODULE_AUTHOR("this version author is RDC"); /* replace "RDC" with the last maintainer. */
MODULE_DESCRIPTION("RDC PCI IDE Driver"); MODULE_DESCRIPTION("RDC PCI IDE Driver");
MODULE_DEVICE_TABLE(pci, rdc_pata_id_table); MODULE_DEVICE_TABLE(pci, rdc_pata_id_table);
MODULE_VERSION(DRIVER_VERSION); MODULE_VERSION(DRIVER_VERSION);
// a pci driver /* a pci driver */
static struct pci_driver rdc_pata_driver = { static struct pci_driver rdc_pata_driver = {
.name = DRIVER_NAME, .name = DRIVER_NAME,
.id_table = rdc_pata_id_table, .id_table = rdc_pata_id_table,
.probe = rdc_init_one, .probe = rdc_init_one,
.remove = ata_pci_remove_one, .remove = ata_pci_remove_one,
#ifdef CONFIG_PM #ifdef CONFIG_PM
.suspend = ata_pci_device_suspend, .suspend = ata_pci_device_suspend,
.resume = ata_pci_device_resume, .resume = ata_pci_device_resume,
#endif #endif
}; };
static unsigned int in_module_init = 1; // hotplugging check??? static unsigned int in_module_init = 1; /* hotplugging check??? */
static int __init pata_rdc_init(void) static int __init pata_rdc_init(void)
{ {
int rc; int rc;
dbgprintf("pata_rdc_init\n"); dbgprintf("pata_rdc_init\n");
rc = pci_register_driver(&rdc_pata_driver); rc = pci_register_driver(&rdc_pata_driver);
if (rc) if (rc) {
{ dbgprintf("pata_rdc_init faile\n");
dbgprintf("pata_rdc_init faile\n"); return rc;
return rc; }
}
in_module_init = 0; in_module_init = 0;
return 0; return 0;
} }
static void __exit pata_rdc_exit(void) static void __exit pata_rdc_exit(void)
{ {
dbgprintf("pata_rdc_exit\n"); dbgprintf("pata_rdc_exit\n");
pci_unregister_driver(&rdc_pata_driver); pci_unregister_driver(&rdc_pata_driver);
} }
module_init(pata_rdc_init); module_init(pata_rdc_init);
module_exit(pata_rdc_exit); module_exit(pata_rdc_exit);
// ata device data /* ata device data */
static struct pci_bits ATA_Decode_Enable_Bits[] = { // see ATA Host Adapters Standards. /* see ATA Host Adapters Standards. */
{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 0 */ static struct pci_bits ATA_Decode_Enable_Bits[] = {
{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 1 */ { 0x41U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 0 */
{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 1 */
}; };
static struct scsi_host_template rdc_pata_sht = { // pata host template /* pata host template */
ATA_BMDMA_SHT(DRIVER_NAME), static struct scsi_host_template rdc_pata_sht = {
ATA_BMDMA_SHT(DRIVER_NAME),
}; };
static const struct ata_port_operations rdc_pata_ops = { static const struct ata_port_operations rdc_pata_ops = {
.inherits = &ata_bmdma_port_ops, .inherits = &ata_bmdma_port_ops,
.port_start = rdc_pata_port_start, .port_start = rdc_pata_port_start,
.port_stop = rdc_pata_port_stop, .port_stop = rdc_pata_port_stop,
.prereset = rdc_pata_prereset, .prereset = rdc_pata_prereset,
.cable_detect = rdc_pata_cable_detect, .cable_detect = rdc_pata_cable_detect,
.set_piomode = rdc_pata_set_piomode, .set_piomode = rdc_pata_set_piomode,
.set_dmamode = rdc_pata_set_dmamode, .set_dmamode = rdc_pata_set_dmamode,
}; };
static struct ata_port_info rdc_pata_port_info[] = { static struct ata_port_info rdc_pata_port_info[] = {
[RDC_17F31011] = [RDC_17F31011] = {
{ .flags = ATA_FLAG_SLAVE_POSS,
.flags = ATA_FLAG_SLAVE_POSS, .pio_mask = 0x1f, /* pio0-4 */
.pio_mask = 0x1f, /* pio0-4 */ .mwdma_mask = 0x07, /* mwdma0-2 */
.mwdma_mask = 0x07, /* mwdma0-2 */ .udma_mask = ATA_UDMA5, /* udma0-5 */
.udma_mask = ATA_UDMA5, /* udma0-5 */ .port_ops = &rdc_pata_ops,
.port_ops = &rdc_pata_ops, },
},
[RDC_17F31012] = {
[RDC_17F31012] = .flags = ATA_FLAG_SLAVE_POSS,
{ .pio_mask = 0x1f, /* pio0-4 */
.flags = ATA_FLAG_SLAVE_POSS, .mwdma_mask = 0x07, /* mwdma0-2 */
.pio_mask = 0x1f, /* pio0-4 */ .udma_mask = ATA_UDMA5, /* udma0-5 */
.mwdma_mask = 0x07, /* mwdma0-2 */ .port_ops = &rdc_pata_ops,
.udma_mask = ATA_UDMA5, /* udma0-5 */ },
.port_ops = &rdc_pata_ops,
},
}; };
// callback function for pci_driver /* callback function for pci_driver */
/** /**
* Register ATA PCI device with kernel services * Register ATA PCI device with kernel services
...@@ -141,43 +139,39 @@ static struct ata_port_info rdc_pata_port_info[] = { ...@@ -141,43 +139,39 @@ static struct ata_port_info rdc_pata_port_info[] = {
* RETURNS: * RETURNS:
* Zero on success, or -ERRNO value. * Zero on success, or -ERRNO value.
*/ */
static int __devinit rdc_init_one( static int __devinit rdc_init_one(struct pci_dev *pdev,
struct pci_dev *pdev, const struct pci_device_id *ent)
const struct pci_device_id *ent
)
{ {
//struct device *dev = &pdev->dev; /*struct device *dev = &pdev->dev; */
struct ata_port_info port_info[2]; struct ata_port_info port_info[2];
const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] }; const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] };
int rc; int rc;
dbgprintf("rdc_init_one\n"); dbgprintf("rdc_init_one\n");
/* no hotplugging support (FIXME) */ // why??? /* no hotplugging support (FIXME) */ /* why??? */
if (!in_module_init) if (!in_module_init) {
{ dbgprintf("rdc_init_one in_module_init == 0 failed \n");
dbgprintf("rdc_init_one in_module_init == 0 failed \n"); return -ENODEV;
return -ENODEV; }
} port_info[0] = rdc_pata_port_info[ent->driver_data];
port_info[0] = rdc_pata_port_info[ent->driver_data]; port_info[1] = rdc_pata_port_info[ent->driver_data];
port_info[1] = rdc_pata_port_info[ent->driver_data];
/* enable device and prepare host */
/* enable device and prepare host */ rc = pci_enable_device(pdev);
rc = pci_enable_device(pdev); if (rc) {
if (rc) dbgprintf("rdc_init_one pci_enable_device failed \n");
{ return rc;
dbgprintf("rdc_init_one pci_enable_device failed \n"); }
return rc; /* initialize controller */
}
/* initialize controller */ pci_intx(pdev, 1); /* enable interrupt */
pci_intx(pdev, 1); // enable interrupt return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL);
return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL);
} }
// callback function for ata_port /* callback function for ata_port */
/** /**
* Set port up for dma. * Set port up for dma.
...@@ -196,34 +190,27 @@ static int __devinit rdc_init_one( ...@@ -196,34 +190,27 @@ static int __devinit rdc_init_one(
* LOCKING: * LOCKING:
* Inherited from caller. * Inherited from caller.
*/ */
static int rdc_pata_port_start( static int rdc_pata_port_start(struct ata_port *ap)
struct ata_port *ap
)
{ {
uint Channel; uint Channel;
Channel = ap->port_no; Channel = ap->port_no;
dbgprintf("rdc_pata_port_start Channel: %u \n", Channel); dbgprintf("rdc_pata_port_start Channel: %u \n", Channel);
if (ap->ioaddr.bmdma_addr) if (ap->ioaddr.bmdma_addr) {
{ return ata_port_start(ap);
return ata_port_start(ap); } else {
} dbgprintf("rdc_pata_port_start return 0 !!!\n");
else return 0;
{ }
dbgprintf("rdc_pata_port_start return 0 !!!\n");
return 0;
}
} }
static void rdc_pata_port_stop( static void rdc_pata_port_stop(struct ata_port *ap)
struct ata_port *ap
)
{ {
uint Channel; uint Channel;
Channel = ap->port_no; Channel = ap->port_no;
dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel); dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel);
} }
/** /**
...@@ -234,34 +221,27 @@ static void rdc_pata_port_stop( ...@@ -234,34 +221,27 @@ static void rdc_pata_port_stop(
* LOCKING: * LOCKING:
* None (inherited from caller). * None (inherited from caller).
*/ */
static int rdc_pata_prereset( static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
struct ata_link *link,
unsigned long deadline
)
{ {
struct pci_dev *pdev; struct pci_dev *pdev;
struct ata_port *ap; struct ata_port *ap;
uint Channel;
uint Channel;
dbgprintf("rdc_pata_prereset\n"); dbgprintf("rdc_pata_prereset\n");
ap = link->ap; ap = link->ap;
pdev = to_pci_dev(ap->host->dev); pdev = to_pci_dev(ap->host->dev);
Channel = ap->port_no; Channel = ap->port_no;
// test ATA Decode Enable Bits, should be enable. /* test ATA Decode Enable Bits, should be enable. */
if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) {
{ dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel);
dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel); return -ENOENT;
return -ENOENT; } else {
} dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel);
else return ata_std_prereset(link, deadline);
{ }
dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel);
return ata_std_prereset(link, deadline);
}
} }
/** /**
...@@ -274,46 +254,34 @@ static int rdc_pata_prereset( ...@@ -274,46 +254,34 @@ static int rdc_pata_prereset(
* LOCKING: * LOCKING:
* None (inherited from caller). * None (inherited from caller).
*/ */
static int rdc_pata_cable_detect(struct ata_port *ap)
static int rdc_pata_cable_detect(
struct ata_port *ap
)
{ {
struct pci_dev *pdev; struct pci_dev *pdev;
uint Channel;
uint Mask;
u32 u32Value;
uint Channel; dbgprintf("rdc_pata_cable_detect\n");
uint Mask; pdev = to_pci_dev(ap->host->dev);
u32 u32Value;
dbgprintf("rdc_pata_cable_detect\n"); Channel = ap->port_no;
pdev = to_pci_dev(ap->host->dev); if (Channel == 0)
Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report;
else
Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report;
Channel = ap->port_no; /* check BIOS cable detect results */
pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value);
if (Channel == 0) if ((u32Value & Mask) == 0) {
{ dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel);
Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report; return ATA_CBL_PATA40;
} } else {
else dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel);
{ return ATA_CBL_PATA80;
Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report; }
}
/* check BIOS cable detect results */
pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value);
if ((u32Value & Mask) == 0)
{
dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel);
return ATA_CBL_PATA40;
}
else
{
dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel);
return ATA_CBL_PATA80;
}
} }
/** /**
...@@ -326,80 +294,73 @@ static int rdc_pata_cable_detect( ...@@ -326,80 +294,73 @@ static int rdc_pata_cable_detect(
* LOCKING: * LOCKING:
* None (inherited from caller). * None (inherited from caller).
*/ */
static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev)
static void rdc_pata_set_piomode(
struct ata_port *ap,
struct ata_device *adev
)
{ {
struct pci_dev *pdev; struct pci_dev *pdev;
uint Channel;
uint Channel; uint DeviceID;
uint DeviceID; uint PIOTimingMode;
uint PrefetchPostingEnable;
uint PIOTimingMode;
uint PrefetchPostingEnable; dbgprintf("rdc_pata_set_piomode\n");
dbgprintf("rdc_pata_set_piomode\n"); pdev = to_pci_dev(ap->host->dev);
pdev = to_pci_dev(ap->host->dev); Channel = ap->port_no;
DeviceID = adev->devno;
Channel = ap->port_no; /*
DeviceID = adev->devno; * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1,
PIOTimingMode = adev->pio_mode - XFER_PIO_0; // piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... * XFER_PIO_2, XFER_PIO_3...
*/
if (adev->class == ATA_DEV_ATA) PIOTimingMode = adev->pio_mode - XFER_PIO_0;
{
PrefetchPostingEnable = TRUE; if (adev->class == ATA_DEV_ATA) {
} PrefetchPostingEnable = TRUE;
else } else {
{ // ATAPI, CD DVD Rom /* ATAPI, CD DVD Rom */
PrefetchPostingEnable = FALSE; PrefetchPostingEnable = FALSE;
} }
/* PIO configuration clears DTE unconditionally. It will be /* PIO configuration clears DTE unconditionally. It will be
* programmed in set_dmamode which is guaranteed to be called * programmed in set_dmamode which is guaranteed to be called
* after set_piomode if any DMA mode is available. * after set_piomode if any DMA mode is available.
*/ */
/* Ensure the UDMA bit is off - it will be turned back on if /* Ensure the UDMA bit is off - it will be turned back on if UDMA is
UDMA is selected */ * selected */
if (Channel == 0) if (Channel == 0) {
{ ATAHostAdapter_SetPrimaryPIO(
ATAHostAdapter_SetPrimaryPIO( pdev,
pdev, DeviceID,
DeviceID, PIOTimingMode,
PIOTimingMode, TRUE,/* DMAEnable, */
TRUE,//DMAEnable, PrefetchPostingEnable
PrefetchPostingEnable );
);
ATAHostAdapter_SetPrimaryUDMA(
ATAHostAdapter_SetPrimaryUDMA( pdev,
pdev, DeviceID,
DeviceID, FALSE,/* UDMAEnable, */
FALSE,//UDMAEnable, UDMA0
UDMA0 );
); } else {
} ATAHostAdapter_SetSecondaryPIO(
else pdev,
{ DeviceID,
ATAHostAdapter_SetSecondaryPIO( PIOTimingMode,
pdev, TRUE,/* DMAEnable, */
DeviceID, PrefetchPostingEnable
PIOTimingMode, );
TRUE,//DMAEnable,
PrefetchPostingEnable ATAHostAdapter_SetSecondaryUDMA(
); pdev,
DeviceID,
ATAHostAdapter_SetSecondaryUDMA( FALSE,/* UDMAEnable, */
pdev, UDMA0
DeviceID, );
FALSE,//UDMAEnable, }
UDMA0 dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel, DeviceID, PIOTimingMode);
);
}
dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel, DeviceID, PIOTimingMode);
} }
/** /**
...@@ -412,992 +373,694 @@ static void rdc_pata_set_piomode( ...@@ -412,992 +373,694 @@ static void rdc_pata_set_piomode(
* LOCKING: * LOCKING:
* None (inherited from caller). * None (inherited from caller).
*/ */
static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
static void rdc_pata_set_dmamode(
struct ata_port *ap,
struct ata_device *adev
)
{ {
struct pci_dev *pdev; struct pci_dev *pdev;
uint Channel;
uint Channel; uint DeviceID;
uint DeviceID; uint PIOTimingMode;
uint PrefetchPostingEnable;
uint PIOTimingMode; uint DMATimingMode;
uint PrefetchPostingEnable; uint UDMAEnable;
uint DMATimingMode;
uint UDMAEnable; dbgprintf("rdc_pata_set_dmamode\n");
dbgprintf("rdc_pata_set_dmamode\n"); pdev = to_pci_dev(ap->host->dev);
pdev = to_pci_dev(ap->host->dev); Channel = ap->port_no;
DeviceID = adev->devno;
Channel = ap->port_no; PIOTimingMode = adev->pio_mode - XFER_PIO_0; /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */
DeviceID = adev->devno; DMATimingMode = adev->dma_mode; /* UDMA or MDMA */
PIOTimingMode = adev->pio_mode - XFER_PIO_0; // piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3...
DMATimingMode = adev->dma_mode; // UDMA or MDMA if (adev->class == ATA_DEV_ATA) {
PrefetchPostingEnable = TRUE;
if (adev->class == ATA_DEV_ATA) } else {
{ /* ATAPI, CD DVD Rom */
PrefetchPostingEnable = TRUE; PrefetchPostingEnable = FALSE;
} }
else
{ // ATAPI, CD DVD Rom if (ap->udma_mask == 0) {
PrefetchPostingEnable = FALSE; /* ata_port dont support udma. depend on hardware spec. */
} UDMAEnable = FALSE;
} else {
if (ap->udma_mask == 0) UDMAEnable = TRUE;
{ // ata_port dont support udma. depend on hardware spec. }
UDMAEnable = FALSE;
} /*if (ap->mdma_mask == 0) {
else }*/
{
UDMAEnable = TRUE; if (Channel == 0) {
} if (DMATimingMode >= XFER_UDMA_0) {
/* UDMA */
/*if (ap->mdma_mask == 0) ATAHostAdapter_SetPrimaryPIO(pdev,
{ DeviceID,
}*/ PIOTimingMode,
TRUE,/*DMAEnable,*/
if (Channel == 0) PrefetchPostingEnable);
{
if (DMATimingMode >= XFER_UDMA_0) ATAHostAdapter_SetPrimaryUDMA(pdev,
{ // UDMA DeviceID,
ATAHostAdapter_SetPrimaryPIO( UDMAEnable,
pdev, DMATimingMode - XFER_UDMA_0);
DeviceID, dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
PIOTimingMode, } else {
TRUE,//DMAEnable, /* MDMA */
PrefetchPostingEnable ATAHostAdapter_SetPrimaryPIO(pdev,
); DeviceID,
(DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
ATAHostAdapter_SetPrimaryUDMA( TRUE,/*DMAEnable,*/
pdev, PrefetchPostingEnable);
DeviceID,
UDMAEnable, ATAHostAdapter_SetPrimaryUDMA(pdev,
DMATimingMode - XFER_UDMA_0 DeviceID,
); FALSE,/*UDMAEnable,*/
dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0)); UDMA0);
} dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
else }
{ // MDMA } else {
ATAHostAdapter_SetPrimaryPIO( if (DMATimingMode >= XFER_UDMA_0) {
pdev, /* UDMA */
DeviceID, ATAHostAdapter_SetSecondaryPIO(pdev,
(DMATimingMode - XFER_MW_DMA_0) + PIO2, // MDMA0 = PIO2 DeviceID,
TRUE,//DMAEnable, PIOTimingMode,
PrefetchPostingEnable TRUE,/*DMAEnable,*/
); PrefetchPostingEnable);
ATAHostAdapter_SetPrimaryUDMA( ATAHostAdapter_SetSecondaryUDMA(pdev,
pdev, DeviceID,
DeviceID, UDMAEnable,
FALSE,//UDMAEnable, DMATimingMode - XFER_UDMA_0);
UDMA0 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
); } else {
dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0)); /* MDMA */
} ATAHostAdapter_SetSecondaryPIO(pdev,
} DeviceID,
else (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
{ TRUE,/*DMAEnable,*/
if (DMATimingMode >= XFER_UDMA_0) PrefetchPostingEnable);
{ // UDMA
ATAHostAdapter_SetSecondaryPIO( ATAHostAdapter_SetSecondaryUDMA(pdev,
pdev, DeviceID,
DeviceID, FALSE,/*UDMAEnable,*/
PIOTimingMode, UDMA0);
TRUE,//DMAEnable, dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
PrefetchPostingEnable }
); }
ATAHostAdapter_SetSecondaryUDMA(
pdev,
DeviceID,
UDMAEnable,
DMATimingMode - XFER_UDMA_0
);
dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
}
else
{ // MDMA
ATAHostAdapter_SetSecondaryPIO(
pdev,
DeviceID,
(DMATimingMode - XFER_MW_DMA_0) + PIO2, // MDMA0 = PIO2
TRUE,//DMAEnable,
PrefetchPostingEnable
);
ATAHostAdapter_SetSecondaryUDMA(
pdev,
DeviceID,
FALSE,//UDMAEnable,
UDMA0
);
dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
}
}
} }
// modified PCIDeviceIO code. /* modified PCIDeviceIO code. */
static uint static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
PCIDeviceIO_ReadPCIConfiguration(
struct pci_dev *pdev,
uint Offset,
uint Length,
void* pBuffer
)
{ {
uint funcresult; uint funcresult;
unchar *pchar;
uint i;
unchar* pchar; funcresult = TRUE;
uint i; pchar = pBuffer;
funcresult = TRUE; for (i = 0; i < Length; i++) {
pci_read_config_byte(pdev, Offset, pchar);
Offset++;
pchar++;
}
pchar = pBuffer; funcresult = TRUE;
for (i = 0; i < Length; i++) goto funcexit;
{
pci_read_config_byte(pdev, Offset, pchar);
Offset++;
pchar++;
}
funcresult = TRUE;
goto funcexit;
funcexit: funcexit:
return funcresult; return funcresult;
} }
static uint static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
PCIDeviceIO_WritePCIConfiguration(
struct pci_dev *pdev,
uint Offset,
uint Length,
void* pBuffer
)
{ {
uint funcresult; uint funcresult;
unchar *pchar;
unchar* pchar; uint i;
uint i; funcresult = TRUE;
funcresult = TRUE; pchar = pBuffer;
pchar = pBuffer; for (i = 0; i < Length; i++) {
pci_write_config_byte(pdev, Offset, *pchar);
Offset++;
pchar++;
}
for (i = 0; i < Length; i++) funcresult = TRUE;
{
pci_write_config_byte(pdev, Offset, *pchar);
Offset++;
pchar++;
}
funcresult = TRUE; goto funcexit;
goto funcexit;
funcexit: funcexit:
return funcresult; return funcresult;
} }
/* modified ATAHostAdapter code. */
// modified ATAHostAdapter code. static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID,
uint PIOTimingMode, uint DMAEnable,
static uint uint PrefetchPostingEnable)
ATAHostAdapter_SetPrimaryPIO(
struct pci_dev *pdev,
uint DeviceID,
uint PIOTimingMode,
uint DMAEnable,
uint PrefetchPostingEnable
)
{ {
uint funcresult; uint funcresult;
uint result;
uint result; uint ATATimingRegister;
uint Device1TimingRegister;
uint ATATimingRegister;
uint Device1TimingRegister; funcresult = TRUE;
funcresult = TRUE; ATATimingRegister = 0;
Device1TimingRegister = 0;
ATATimingRegister = 0;
Device1TimingRegister = 0; result = PCIDeviceIO_ReadPCIConfiguration(pdev,
ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
result = PCIDeviceIO_ReadPCIConfiguration( ATAConfiguration_ID_PrimaryTiming_Size,
pdev, &ATATimingRegister);
ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset, if (result == FALSE) {
ATAConfiguration_ID_PrimaryTiming_Size, funcresult = FALSE;
&ATATimingRegister goto funcexit;
); }
if (result == FALSE)
{ result = PCIDeviceIO_ReadPCIConfiguration(pdev,
funcresult = FALSE; ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
goto funcexit; ATAConfiguration_ID_Device1Timing_Size,
} &Device1TimingRegister);
if (result == FALSE) {
result = PCIDeviceIO_ReadPCIConfiguration( funcresult = FALSE;
pdev, goto funcexit;
ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, }
ATAConfiguration_ID_Device1Timing_Size,
&Device1TimingRegister ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable;
);
if (result == FALSE) switch (DeviceID) {
{ case 0:
funcresult = FALSE; /* mask clear */
goto funcexit; ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable |
} ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable |
ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable |
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable; ATAConfiguration_PrimaryTiming_Device0DMATimingEnable |
ATAConfiguration_PrimaryTiming_Device0RecoveryMode |
switch(DeviceID) ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode);
{
case 0: if (PIOTimingMode > PIO0)
{ ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable;
// mask clear
ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable if (PIOTimingMode >= PIO3)
| ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
| ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable
| ATAConfiguration_PrimaryTiming_Device0DMATimingEnable if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
| ATAConfiguration_PrimaryTiming_Device0RecoveryMode ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable;
| ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode
); if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable;
if (PIOTimingMode > PIO0)
{ if (PIOTimingMode <= PIO2)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable; ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
} else if (PIOTimingMode == PIO3)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1;
if (PIOTimingMode >= PIO3) else if (PIOTimingMode == PIO4)
{ ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3;
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
} if (PIOTimingMode <= PIO1)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0;
if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) else if (PIOTimingMode == PIO2)
{ ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1;
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable; else if (PIOTimingMode <= PIO4)
} ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2;
break;
if (DMAEnable == TRUE case 1:
&& PIOTimingMode >= PIO2) ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable |
{ ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable |
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable; ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable |
} ATAConfiguration_PrimaryTiming_Device1DMATimingEnable);
if (PIOTimingMode <= PIO2) if (PIOTimingMode > PIO0)
{ ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable;
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
} if (PIOTimingMode >= PIO3)
else if (PIOTimingMode == PIO3) ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable;
{
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1; if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
} ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable;
else if (PIOTimingMode == PIO4)
{ if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3; ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable;
}
Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode |
if (PIOTimingMode <= PIO1) ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode);
{
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0; if (PIOTimingMode <= PIO2)
} Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0;
else if (PIOTimingMode == PIO2) else if (PIOTimingMode == PIO3)
{ Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1;
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1; else if (PIOTimingMode == PIO4)
} Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3;
else if (PIOTimingMode <= PIO4)
{ if (PIOTimingMode <= PIO1)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2; Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0;
} else if (PIOTimingMode == PIO2)
} Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1;
break; else if (PIOTimingMode <= PIO4)
case 1: Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2;
{ break;
ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable default:
| ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable funcresult = FALSE;
| ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable goto funcexit;
| ATAConfiguration_PrimaryTiming_Device1DMATimingEnable break;
); }
if (PIOTimingMode > PIO0) result = PCIDeviceIO_WritePCIConfiguration(pdev,
{ ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable; ATAConfiguration_ID_PrimaryTiming_Size,
} &ATATimingRegister);
if (result == FALSE) {
if (PIOTimingMode >= PIO3) funcresult = FALSE;
{ goto funcexit;
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable; }
}
result = PCIDeviceIO_WritePCIConfiguration(pdev,
if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
{ ATAConfiguration_ID_Device1Timing_Size,
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable; &Device1TimingRegister);
} if (result == FALSE) {
funcresult = FALSE;
if (DMAEnable == TRUE goto funcexit;
&& PIOTimingMode >= PIO2) }
{
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable; goto funcexit;
}
Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode | ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode);
if (PIOTimingMode <= PIO2)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0;
}
else if (PIOTimingMode == PIO3)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1;
}
else if (PIOTimingMode == PIO4)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3;
}
if (PIOTimingMode <= PIO1)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0;
}
else if (PIOTimingMode == PIO2)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1;
}
else if (PIOTimingMode <= PIO4)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2;
}
}
break;
default:
{
funcresult = FALSE;
goto funcexit;
}
break;
}
result = PCIDeviceIO_WritePCIConfiguration(
pdev,
ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_PrimaryTiming_Size,
&ATATimingRegister
);
if (result == FALSE)
{
funcresult = FALSE;
goto funcexit;
}
result = PCIDeviceIO_WritePCIConfiguration(
pdev,
ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_Device1Timing_Size,
&Device1TimingRegister
);
if (result == FALSE)
{
funcresult = FALSE;
goto funcexit;
}
goto funcexit;
funcexit: funcexit:
return funcresult; return funcresult;
} }
static uint static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID,
ATAHostAdapter_SetSecondaryPIO( uint PIOTimingMode, uint DMAEnable,
struct pci_dev *pdev, uint PrefetchPostingEnable)
uint DeviceID,
uint PIOTimingMode,
uint DMAEnable,
uint PrefetchPostingEnable
)
{ {
uint funcresult; uint funcresult;
uint result;
uint result; uint ATATimingRegister;
uint Device1TimingRegister;
uint ATATimingRegister;
uint Device1TimingRegister; funcresult = TRUE;
funcresult = TRUE; ATATimingRegister = 0;
Device1TimingRegister = 0;
ATATimingRegister = 0;
Device1TimingRegister = 0; result = PCIDeviceIO_ReadPCIConfiguration(pdev,
ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
result = PCIDeviceIO_ReadPCIConfiguration( ATAConfiguration_ID_SecondaryTiming_Size,
pdev, &ATATimingRegister);
ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset, if (result == FALSE) {
ATAConfiguration_ID_SecondaryTiming_Size, funcresult = FALSE;
&ATATimingRegister goto funcexit;
); }
if (result == FALSE)
{ result = PCIDeviceIO_ReadPCIConfiguration(pdev,
funcresult = FALSE; ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
goto funcexit; ATAConfiguration_ID_Device1Timing_Size,
} &Device1TimingRegister);
if (result == FALSE) {
result = PCIDeviceIO_ReadPCIConfiguration( funcresult = FALSE;
pdev, goto funcexit;
ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, }
ATAConfiguration_ID_Device1Timing_Size,
&Device1TimingRegister ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable;
);
if (result == FALSE) switch (DeviceID) {
{ case 0:
funcresult = FALSE; /* mask clear */
goto funcexit; ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable |
} ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable |
ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable |
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable; ATAConfiguration_PrimaryTiming_Device0DMATimingEnable |
ATAConfiguration_PrimaryTiming_Device0RecoveryMode |
switch(DeviceID) ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode);
{
case 0: if (PIOTimingMode > PIO0)
{ ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable;
// mask clear
ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable if (PIOTimingMode >= PIO3)
| ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
| ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable
| ATAConfiguration_PrimaryTiming_Device0DMATimingEnable if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
| ATAConfiguration_PrimaryTiming_Device0RecoveryMode ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable;
| ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode
); if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable;
if (PIOTimingMode > PIO0)
{ if (PIOTimingMode <= PIO2)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable; ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
} else if (PIOTimingMode == PIO3)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1;
if (PIOTimingMode >= PIO3) else if (PIOTimingMode == PIO4)
{ ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3;
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
} if (PIOTimingMode <= PIO1)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0;
if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) else if (PIOTimingMode == PIO2)
{ ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1;
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable; else if (PIOTimingMode <= PIO4)
} ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2;
break;
if (DMAEnable == TRUE case 1:
&& PIOTimingMode >= PIO2) ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable |
{ ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable |
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable; ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable |
} ATAConfiguration_PrimaryTiming_Device1DMATimingEnable);
if (PIOTimingMode <= PIO2) if (PIOTimingMode > PIO0)
{ ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable;
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
} if (PIOTimingMode >= PIO3)
else if (PIOTimingMode == PIO3) ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable;
{
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1; if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
} ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable;
else if (PIOTimingMode == PIO4)
{ if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3; ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable;
}
Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode |
if (PIOTimingMode <= PIO1) ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode);
{
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0; if (PIOTimingMode <= PIO2)
} Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0;
else if (PIOTimingMode == PIO2) else if (PIOTimingMode == PIO3)
{ Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1;
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1; else if (PIOTimingMode == PIO4)
} Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3;
else if (PIOTimingMode <= PIO4)
{ if (PIOTimingMode <= PIO1)
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2; Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0;
} else if (PIOTimingMode == PIO2)
} Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1;
break; else if (PIOTimingMode <= PIO4)
case 1: Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2;
{ break;
ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable default:
| ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable funcresult = FALSE;
| ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable goto funcexit;
| ATAConfiguration_PrimaryTiming_Device1DMATimingEnable break;
); }
if (PIOTimingMode > PIO0) result = PCIDeviceIO_WritePCIConfiguration(pdev,
{ ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable; ATAConfiguration_ID_SecondaryTiming_Size,
} &ATATimingRegister);
if (result == FALSE) {
if (PIOTimingMode >= PIO3) funcresult = FALSE;
{ goto funcexit;
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable; }
}
result = PCIDeviceIO_WritePCIConfiguration(pdev,
if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
{ ATAConfiguration_ID_Device1Timing_Size,
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable; &Device1TimingRegister);
} if (result == FALSE) {
funcresult = FALSE;
if (DMAEnable == TRUE goto funcexit;
&& PIOTimingMode >= PIO2) }
{
ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable; goto funcexit;
}
Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode | ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode);
if (PIOTimingMode <= PIO2)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0;
}
else if (PIOTimingMode == PIO3)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1;
}
else if (PIOTimingMode == PIO4)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3;
}
if (PIOTimingMode <= PIO1)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0;
}
else if (PIOTimingMode == PIO2)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1;
}
else if (PIOTimingMode <= PIO4)
{
Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2;
}
}
break;
default:
{
funcresult = FALSE;
goto funcexit;
}
break;
}
result = PCIDeviceIO_WritePCIConfiguration(
pdev,
ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_SecondaryTiming_Size,
&ATATimingRegister
);
if (result == FALSE)
{
funcresult = FALSE;
goto funcexit;
}
result = PCIDeviceIO_WritePCIConfiguration(
pdev,
ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_Device1Timing_Size,
&Device1TimingRegister
);
if (result == FALSE)
{
funcresult = FALSE;
goto funcexit;
}
goto funcexit;
funcexit: funcexit:
return funcresult;
return funcresult;
} }
static uint static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID,
ATAHostAdapter_SetPrimaryUDMA( uint UDMAEnable, uint UDMATimingMode)
struct pci_dev *pdev,
uint DeviceID,
uint UDMAEnable,
uint UDMATimingMode
)
{ {
uint funcresult; uint funcresult;
uint result;
uint result; uint UDMAControlRegister;
uint UDMATimingRegister;
uint UDMAControlRegister; ulong IDEIOConfigurationRegister;
uint UDMATimingRegister;
ulong IDEIOConfigurationRegister; funcresult = TRUE;
UDMAControlRegister = 0;
funcresult = TRUE; UDMATimingRegister = 0;
IDEIOConfigurationRegister = 0;
UDMAControlRegister = 0;
UDMATimingRegister = 0; result = PCIDeviceIO_ReadPCIConfiguration(pdev,
IDEIOConfigurationRegister = 0; ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_UDMAControl_Size,
result = PCIDeviceIO_ReadPCIConfiguration( &UDMAControlRegister);
pdev, if (result == FALSE) {
ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, funcresult = FALSE;
ATAConfiguration_ID_UDMAControl_Size, goto funcexit;
&UDMAControlRegister }
);
if (result == FALSE) result = PCIDeviceIO_ReadPCIConfiguration(pdev,
{ ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
funcresult = FALSE; ATAConfiguration_ID_UDMATiming_Size,
goto funcexit; &UDMATimingRegister);
} if (result == FALSE) {
funcresult = FALSE;
result = PCIDeviceIO_ReadPCIConfiguration( goto funcexit;
pdev, }
ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_UDMATiming_Size, result = PCIDeviceIO_ReadPCIConfiguration(pdev,
&UDMATimingRegister ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
); ATAConfiguration_ID_IDEIOConfiguration_Size,
if (result == FALSE) &IDEIOConfigurationRegister);
{ if (result == FALSE) {
funcresult = FALSE; funcresult = FALSE;
goto funcexit; goto funcexit;
} }
result = PCIDeviceIO_ReadPCIConfiguration( /*Rom Code will determine the device cable type and ATA 100.*/
pdev, /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;*/
ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported;*/
ATAConfiguration_ID_IDEIOConfiguration_Size,
&IDEIOConfigurationRegister switch (DeviceID) {
); case 0:
if (result == FALSE) UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable);
{ if (UDMAEnable == TRUE)
funcresult = FALSE; UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable;
goto funcexit;
} IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable |
ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable);
//Rom Code will determine the device cable type and ATA 100.
//IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; if (UDMATimingMode >= UDMA5)
//IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable;
else if (UDMATimingMode >= UDMA3)
switch(DeviceID) IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable;
{
case 0: /* if 80 cable report */
{ UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime);
UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable);
if (UDMAEnable == TRUE) if (UDMATimingMode == UDMA0) {
{ UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0;
UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable; } else if (UDMATimingMode == UDMA1 ||
} UDMATimingMode == UDMA3 ||
UDMATimingMode == UDMA5) {
IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1;
| ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable } else if (UDMATimingMode == UDMA2 ||
); UDMATimingMode == UDMA4) {
UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2;
if (UDMATimingMode >= UDMA5) }
{ break;
IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable; case 1:
} UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable);
else if (UDMATimingMode >= UDMA3) if (UDMAEnable == TRUE)
{ UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable;
IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable;
} IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable |
ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable);
// if 80 cable report
if (UDMATimingMode >= UDMA5)
UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime); IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable;
else if (UDMATimingMode >= UDMA3)
if (UDMATimingMode == UDMA0) IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable;
{
UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0; /* if 80 cable report */
} UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime);
else if (UDMATimingMode == UDMA1 || UDMATimingMode == UDMA3 || UDMATimingMode == UDMA5)
{ if (UDMATimingMode == UDMA0) {
UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1; UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0;
} } else if (UDMATimingMode == UDMA1 ||
else if (UDMATimingMode == UDMA2 || UDMATimingMode == UDMA4) UDMATimingMode == UDMA3 ||
{ UDMATimingMode == UDMA5) {
UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2; UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1;
} } else if (UDMATimingMode == UDMA2 ||
} UDMATimingMode == UDMA4) {
break; UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2;
case 1: }
{ break;
UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable); default:
if (UDMAEnable == TRUE) funcresult = FALSE;
{ goto funcexit;
UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable; break;
} }
IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable result = PCIDeviceIO_WritePCIConfiguration(pdev,
| ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
); ATAConfiguration_ID_UDMAControl_Size,
&UDMAControlRegister);
if (UDMATimingMode >= UDMA5) if (result == FALSE) {
{ funcresult = FALSE;
IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable; goto funcexit;
} }
else if (UDMATimingMode >= UDMA3)
{ result = PCIDeviceIO_WritePCIConfiguration(pdev,
IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable; ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
} ATAConfiguration_ID_UDMATiming_Size,
&UDMATimingRegister);
// if 80 cable report if (result == FALSE) {
funcresult = FALSE;
UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime); goto funcexit;
}
if (UDMATimingMode == UDMA0)
{ result = PCIDeviceIO_WritePCIConfiguration(pdev,
UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0; ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
} ATAConfiguration_ID_IDEIOConfiguration_Size,
else if (UDMATimingMode == UDMA1 || UDMATimingMode == UDMA3 || UDMATimingMode == UDMA5) &IDEIOConfigurationRegister);
{ if (result == FALSE) {
UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1; funcresult = FALSE;
} goto funcexit;
else if (UDMATimingMode == UDMA2 || UDMATimingMode == UDMA4) }
{
UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2; goto funcexit;
}
}
break;
default:
{
funcresult = FALSE;
goto funcexit;
}
break;
}
result = PCIDeviceIO_WritePCIConfiguration(
pdev,
ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_UDMAControl_Size,
&UDMAControlRegister
);
if (result == FALSE)
{
funcresult = FALSE;
goto funcexit;
}
result = PCIDeviceIO_WritePCIConfiguration(
pdev,
ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_UDMATiming_Size,
&UDMATimingRegister
);
if (result == FALSE)
{
funcresult = FALSE;
goto funcexit;
}
result = PCIDeviceIO_WritePCIConfiguration(
pdev,
ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_IDEIOConfiguration_Size,
&IDEIOConfigurationRegister
);
if (result == FALSE)
{
funcresult = FALSE;
goto funcexit;
}
goto funcexit;
funcexit: funcexit:
return funcresult;
return funcresult;
} }
static uint static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID,
ATAHostAdapter_SetSecondaryUDMA( uint UDMAEnable, uint UDMATimingMode)
struct pci_dev *pdev,
uint DeviceID,
uint UDMAEnable,
uint UDMATimingMode
)
{ {
uint funcresult; uint funcresult;
uint result;
uint result; uint UDMAControlRegister;
uint UDMATimingRegister;
uint UDMAControlRegister; ulong IDEIOConfigurationRegister;
uint UDMATimingRegister;
ulong IDEIOConfigurationRegister; funcresult = TRUE;
funcresult = TRUE; UDMAControlRegister = 0;
UDMATimingRegister = 0;
UDMAControlRegister = 0; IDEIOConfigurationRegister = 0;
UDMATimingRegister = 0;
IDEIOConfigurationRegister = 0; result = PCIDeviceIO_ReadPCIConfiguration(pdev,
ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
result = PCIDeviceIO_ReadPCIConfiguration( ATAConfiguration_ID_UDMAControl_Size,
pdev, &UDMAControlRegister);
ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, if (result == FALSE) {
ATAConfiguration_ID_UDMAControl_Size, funcresult = FALSE;
&UDMAControlRegister goto funcexit;
); }
if (result == FALSE)
{ result = PCIDeviceIO_ReadPCIConfiguration(pdev,
funcresult = FALSE; ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
goto funcexit; ATAConfiguration_ID_UDMATiming_Size,
} &UDMATimingRegister);
if (result == FALSE) {
result = PCIDeviceIO_ReadPCIConfiguration( funcresult = FALSE;
pdev, goto funcexit;
ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, }
ATAConfiguration_ID_UDMATiming_Size,
&UDMATimingRegister result = PCIDeviceIO_ReadPCIConfiguration(pdev,
); ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
if (result == FALSE) ATAConfiguration_ID_IDEIOConfiguration_Size,
{ &IDEIOConfigurationRegister);
funcresult = FALSE; if (result == FALSE) {
goto funcexit; funcresult = FALSE;
} goto funcexit;
}
result = PCIDeviceIO_ReadPCIConfiguration(
pdev, /* Rom Code will determine the device cable type and ATA 100. */
ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; */
ATAConfiguration_ID_IDEIOConfiguration_Size, /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; */
&IDEIOConfigurationRegister
); switch (DeviceID) {
if (result == FALSE) case 0:
{ UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable);
funcresult = FALSE; if (UDMAEnable == TRUE)
goto funcexit; UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable;
}
IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable |
//Rom Code will determine the device cable type and ATA 100. ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable);
//IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;
//IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; if (UDMATimingMode >= UDMA5)
IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable;
switch(DeviceID) else if (UDMATimingMode >= UDMA3)
{ IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable;
case 0:
{ /* if 80 cable report */
UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable); UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime);
if (UDMAEnable == TRUE)
{ if (UDMATimingMode == UDMA0) {
UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable; UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0;
} } else if (UDMATimingMode == UDMA1 ||
UDMATimingMode == UDMA3 ||
IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable UDMATimingMode == UDMA5) {
| ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1;
); } else if (UDMATimingMode == UDMA2 ||
UDMATimingMode == UDMA4) {
if (UDMATimingMode >= UDMA5) UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2;
{ }
IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable; break;
} case 1:
else if (UDMATimingMode >= UDMA3) UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable);
{ if (UDMAEnable == TRUE)
IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable; UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable;
}
IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable |
// if 80 cable report ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable);
UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime); if (UDMATimingMode >= UDMA5)
IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable;
if (UDMATimingMode == UDMA0) else if (UDMATimingMode >= UDMA3)
{ IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable;
UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0;
} /* if 80 cable report */
else if (UDMATimingMode == UDMA1 || UDMATimingMode == UDMA3 || UDMATimingMode == UDMA5) UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime);
{
UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1; if (UDMATimingMode == UDMA0) {
} UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0;
else if (UDMATimingMode == UDMA2 || UDMATimingMode == UDMA4) } else if (UDMATimingMode == UDMA1 ||
{ UDMATimingMode == UDMA3 ||
UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2; UDMATimingMode == UDMA5) {
} UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1;
} } else if (UDMATimingMode == UDMA2 ||
break; UDMATimingMode == UDMA4) {
case 1: UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2;
{ }
UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable); break;
if (UDMAEnable == TRUE) default:
{ funcresult = FALSE;
UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable; goto funcexit;
} break;
}
IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable
| ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable result = PCIDeviceIO_WritePCIConfiguration(pdev,
); ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_UDMAControl_Size,
if (UDMATimingMode >= UDMA5) &UDMAControlRegister);
{ if (result == FALSE) {
IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable; funcresult = FALSE;
} goto funcexit;
else if (UDMATimingMode >= UDMA3) }
{
IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable; result = PCIDeviceIO_WritePCIConfiguration(pdev,
} ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_UDMATiming_Size,
// if 80 cable report &UDMATimingRegister);
if (result == FALSE) {
UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime); funcresult = FALSE;
goto funcexit;
if (UDMATimingMode == UDMA0) }
{
UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0; result = PCIDeviceIO_WritePCIConfiguration(pdev,
} ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
else if (UDMATimingMode == UDMA1 || UDMATimingMode == UDMA3 || UDMATimingMode == UDMA5) ATAConfiguration_ID_IDEIOConfiguration_Size,
{ &IDEIOConfigurationRegister);
UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1; if (result == FALSE) {
} funcresult = FALSE;
else if (UDMATimingMode == UDMA2 || UDMATimingMode == UDMA4) goto funcexit;
{ }
UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2;
} goto funcexit;
}
break;
default:
{
funcresult = FALSE;
goto funcexit;
}
break;
}
result = PCIDeviceIO_WritePCIConfiguration(
pdev,
ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_UDMAControl_Size,
&UDMAControlRegister
);
if (result == FALSE)
{
funcresult = FALSE;
goto funcexit;
}
result = PCIDeviceIO_WritePCIConfiguration(
pdev,
ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_UDMATiming_Size,
&UDMATimingRegister
);
if (result == FALSE)
{
funcresult = FALSE;
goto funcexit;
}
result = PCIDeviceIO_WritePCIConfiguration(
pdev,
ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
ATAConfiguration_ID_IDEIOConfiguration_Size,
&IDEIOConfigurationRegister
);
if (result == FALSE)
{
funcresult = FALSE;
goto funcexit;
}
goto funcexit;
funcexit: funcexit:
return funcresult;
return funcresult;
} }
drivers/staging/pata_rdc/pata_rdc.h
View file @ 482612af
...@@ -2,139 +2,136 @@ ...@@ -2,139 +2,136 @@
#define pata_rdc_H #define pata_rdc_H
#ifndef TRUE #ifndef TRUE
#define TRUE 1 #define TRUE 1
#endif #endif
#ifndef FALSE #ifndef FALSE
#define FALSE 0 #define FALSE 0
#endif #endif
// ATA Configuration Register ID offset address size /* ATA Configuration Register ID offset address size */
#define ATAConfiguration_PCIOffset 0x40 #define ATAConfiguration_PCIOffset 0x40
#define ATAConfiguration_ID_PrimaryTiming 0x00 #define ATAConfiguration_ID_PrimaryTiming 0x00
#define ATAConfiguration_ID_SecondaryTiming 0x02 #define ATAConfiguration_ID_SecondaryTiming 0x02
#define ATAConfiguration_ID_Device1Timing 0x04 #define ATAConfiguration_ID_Device1Timing 0x04
#define ATAConfiguration_ID_UDMAControl 0x08 #define ATAConfiguration_ID_UDMAControl 0x08
#define ATAConfiguration_ID_UDMATiming 0x0A #define ATAConfiguration_ID_UDMATiming 0x0A
#define ATAConfiguration_ID_IDEIOConfiguration 0x14 #define ATAConfiguration_ID_IDEIOConfiguration 0x14
#define ATAConfiguration_ID_PrimaryTiming_Size 2 #define ATAConfiguration_ID_PrimaryTiming_Size 2
#define ATAConfiguration_ID_SecondaryTiming_Size 2 #define ATAConfiguration_ID_SecondaryTiming_Size 2
#define ATAConfiguration_ID_Device1Timing_Size 1 #define ATAConfiguration_ID_Device1Timing_Size 1
#define ATAConfiguration_ID_UDMAControl_Size 1 #define ATAConfiguration_ID_UDMAControl_Size 1
#define ATAConfiguration_ID_UDMATiming_Size 2 #define ATAConfiguration_ID_UDMATiming_Size 2
#define ATAConfiguration_ID_IDEIOConfiguration_Size 4 #define ATAConfiguration_ID_IDEIOConfiguration_Size 4
// ATA Configuration Register bit define /* ATA Configuration Register bit define */
#define ATAConfiguration_PrimaryTiming_Device0FastTimingEnable 0x0001 #define ATAConfiguration_PrimaryTiming_Device0FastTimingEnable 0x0001
#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable 0x0002 // PIO 3 or greater #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable 0x0002 /* PIO 3 or greater */
#define ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable 0x0004 // PIO 2 or greater #define ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable 0x0004 /* PIO 2 or greater */
#define ATAConfiguration_PrimaryTiming_Device0DMATimingEnable 0x0008 #define ATAConfiguration_PrimaryTiming_Device0DMATimingEnable 0x0008
#define ATAConfiguration_PrimaryTiming_Device1FastTimingEnable 0x0010 #define ATAConfiguration_PrimaryTiming_Device1FastTimingEnable 0x0010
#define ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable 0x0020 // PIO 3 or greater #define ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable 0x0020 /* PIO 3 or greater */
#define ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable 0x0040 // PIO 2 or greater #define ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable 0x0040 /* PIO 2 or greater */
#define ATAConfiguration_PrimaryTiming_Device1DMATimingEnable 0x0080 #define ATAConfiguration_PrimaryTiming_Device1DMATimingEnable 0x0080
#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode 0x0300 #define ATAConfiguration_PrimaryTiming_Device0RecoveryMode 0x0300
#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0 0x0000 // PIO 0, PIO 2, MDMA 0 #define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0 0x0000 /* PIO 0, PIO 2, MDMA 0 */
#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1 0x0100 // PIO 3, MDMA 1 #define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1 0x0100 /* PIO 3, MDMA 1 */
#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_2 0x0200 // X #define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_2 0x0200 /* X */
#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3 0x0300 // PIO 4, MDMA 2 #define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3 0x0300 /* PIO 4, MDMA 2 */
#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode 0x3000 #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode 0x3000
#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0 0x0000 // PIO 0 #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0 0x0000 /* PIO 0 */
#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1 0x1000 // PIO 2, MDMA 0 #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1 0x1000 /* PIO 2, MDMA 0 */
#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2 0x2000 // PIO 3, PIO 4, MDMA 1, MDMA 2 #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2 0x2000 /* PIO 3, PIO 4, MDMA 1, MDMA 2 */
#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_3 0x3000 // X #define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_3 0x3000 /* X */
#define ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable 0x4000 #define ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable 0x4000
#define ATAConfiguration_PrimaryTiming_IDEDecodeEnable 0x8000 #define ATAConfiguration_PrimaryTiming_IDEDecodeEnable 0x8000
#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode 0x0003 #define ATAConfiguration_Device1Timing_PrimaryRecoveryMode 0x0003
#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0 0x0000 #define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0 0x0000
#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1 0x0001 #define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1 0x0001
#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_2 0x0002 #define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_2 0x0002
#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3 0x0003 #define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3 0x0003
#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode 0x000C #define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode 0x000C
#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0 0x0000 #define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0 0x0000
#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1 0x0004 #define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1 0x0004
#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2 0x0008 #define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2 0x0008
#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_3 0x000C #define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_3 0x000C
#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode 0x0030 #define ATAConfiguration_Device1Timing_SecondaryRecoveryMode 0x0030
#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0 0x0000 #define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0 0x0000
#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1 0x0010 #define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1 0x0010
#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_2 0x0020 #define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_2 0x0020
#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3 0x0030 #define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3 0x0030
#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode 0x00C0 #define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode 0x00C0
#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0 0x0000 #define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0 0x0000
#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1 0x0040 #define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1 0x0040
#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2 0x0080 #define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2 0x0080
#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_3 0x00C0 #define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_3 0x00C0
#define ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable 0x0001 #define ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable 0x0001
#define ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable 0x0002 #define ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable 0x0002
#define ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable 0x0004 #define ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable 0x0004
#define ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable 0x0008 #define ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable 0x0008
#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime 0x0003 #define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime 0x0003
#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0 0x0000 // UDMA 0 #define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0 0x0000 /* UDMA 0 */
#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1 0x0001 // UDMA 1, UDMA 3, UDMA 5 #define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1 0x0001 /* UDMA 1, UDMA 3, UDMA 5 */
#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2 0x0002 // UDMA 2, UDMA 4 #define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2 0x0002 /* UDMA 2, UDMA 4 */
#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_3 0x0003 // X #define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_3 0x0003 /* X */
#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime 0x0030 #define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime 0x0030
#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0 0x0000 // UDMA 0 #define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0 0x0000 /* UDMA 0 */
#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1 0x0010 // UDMA 1, UDMA 3, UDMA 5 #define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1 0x0010 /* UDMA 1, UDMA 3, UDMA 5 */
#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2 0x0020 // UDMA 2, UDMA 4 #define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2 0x0020 /* UDMA 2, UDMA 4 */
#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_3 0x0030 // X #define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_3 0x0030 /* X */
#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime 0x0300 #define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime 0x0300
#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0 0x0000 // UDMA 0 #define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0 0x0000 /* UDMA 0 */
#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1 0x0100 // UDMA 1, UDMA 3, UDMA 5 #define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1 0x0100 /* UDMA 1, UDMA 3, UDMA 5 */
#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2 0x0200 // UDMA 2, UDMA 4 #define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2 0x0200 /* UDMA 2, UDMA 4 */
#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_3 0x0300 // X #define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_3 0x0300 /* X */
#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime 0x3000 #define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime 0x3000
#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0 0x0000 // UDMA 0 #define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0 0x0000 /* UDMA 0 */
#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1 0x1000 // UDMA 1, UDMA 3, UDMA 5 #define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1 0x1000 /* UDMA 1, UDMA 3, UDMA 5 */
#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2 0x2000 // UDMA 2, UDMA 4 #define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2 0x2000 /* UDMA 2, UDMA 4 */
#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_3 0x3000 // X #define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_3 0x3000 /* X */
#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable 0x00000001 // UDMA 3, UDMA 4 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable 0x00000001 /* UDMA 3, UDMA 4 */
#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable 0x00000002 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable 0x00000002
#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable 0x00000004 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable 0x00000004
#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable 0x00000008 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable 0x00000008
#define ATAConfiguration_IDEIOConfiguration_DeviceCable80Report 0x000000F0 #define ATAConfiguration_IDEIOConfiguration_DeviceCable80Report 0x000000F0
#define ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report 0x00000030 #define ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report 0x00000030
#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0Cable80Report 0x00000010 // UDMA 3, UDMA 4, UDMA 5 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0Cable80Report 0x00000010 /* UDMA 3, UDMA 4, UDMA 5 */
#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1Cable80Report 0x00000020 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1Cable80Report 0x00000020
#define ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report 0x000000C0 #define ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report 0x000000C0
#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0Cable80Report 0x00000040 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0Cable80Report 0x00000040
#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1Cable80Report 0x00000080 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1Cable80Report 0x00000080
#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable 0x00001000 // UDMA 5 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable 0x00001000 /* UDMA 5 */
#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable 0x00002000 #define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable 0x00002000
#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable 0x00004000 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable 0x00004000
#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable 0x00008000 #define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable 0x00008000
#define ATAConfiguration_IDEIOConfiguration_ATA100IsSupported 0x00F00000 #define ATAConfiguration_IDEIOConfiguration_ATA100IsSupported 0x00F00000
enum _PIOTimingMode enum _PIOTimingMode {
{ PIO0 = 0,
PIO0 = 0, PIO1,
PIO1, PIO2, /* MDMA 0 */
PIO2, // MDMA 0 PIO3, /* MDMA 1 */
PIO3, // MDMA 1 PIO4 /* MDMA 2 */
PIO4 // MDMA 2
}; };
enum _DMATimingMode enum _DMATimingMode {
{ MDMA0 = 0,
MDMA0 = 0, MDMA1,
MDMA1, MDMA2
MDMA2
}; };
enum _UDMATimingMode enum _UDMATimingMode {
{ UDMA0 = 0,
UDMA0 = 0, UDMA1,
UDMA1, UDMA2,
UDMA2, UDMA3,
UDMA3, UDMA4,
UDMA4, UDMA5
UDMA5
}; };
...@@ -144,94 +141,34 @@ enum rdc_controller_ids { ...@@ -144,94 +141,34 @@ enum rdc_controller_ids {
RDC_17F31012 RDC_17F31012
}; };
// callback function for driver /* callback function for driver */
static int rdc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
static int __devinit rdc_init_one(
struct pci_dev *pdev, /* callback function for ata_port */
const struct pci_device_id *ent static int rdc_pata_port_start(struct ata_port *ap);
);
static void rdc_pata_port_stop(struct ata_port *ap);
// callback function for ata_port
static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline);
static int rdc_pata_port_start(
struct ata_port *ap static int rdc_pata_cable_detect(struct ata_port *ap);
);
static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev);
static void rdc_pata_port_stop(
struct ata_port *ap static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev);
);
/* modified PCIDeviceIO code. */
static int rdc_pata_prereset( static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer);
struct ata_link *link,
unsigned long deadline static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer);
);
/* modify ATAHostAdapter code */
static int rdc_pata_cable_detect( static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID, uint PIOTimingMode, uint DMAEnable, uint PrefetchPostingEnable);
struct ata_port *ap
); static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID, uint PIOTimingMode, uint DMAEnable, uint PrefetchPostingEnable);
static void rdc_pata_set_piomode( static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID, uint UDMAEnable, uint UDMATimingMode);
struct ata_port *ap,
struct ata_device *adev static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID, uint UDMAEnable, uint UDMATimingMode);
);
static void rdc_pata_set_dmamode(
struct ata_port *ap,
struct ata_device *adev
);
// modified PCIDeviceIO code.
static uint
PCIDeviceIO_ReadPCIConfiguration(
struct pci_dev *pdev,
uint Offset,
uint Length,
void* pBuffer
);
static uint
PCIDeviceIO_WritePCIConfiguration(
struct pci_dev *pdev,
uint Offset,
uint Length,
void* pBuffer
);
// modify ATAHostAdapter code
static uint
ATAHostAdapter_SetPrimaryPIO(
struct pci_dev *pdev,
uint DeviceID,
uint PIOTimingMode,
uint DMAEnable,
uint PrefetchPostingEnable
);
static uint
ATAHostAdapter_SetSecondaryPIO(
struct pci_dev *pdev,
uint DeviceID,
uint PIOTimingMode,
uint DMAEnable,
uint PrefetchPostingEnable
);
static uint
ATAHostAdapter_SetPrimaryUDMA(
struct pci_dev *pdev,
uint DeviceID,
uint UDMAEnable,
uint UDMATimingMode
);
static uint
ATAHostAdapter_SetSecondaryUDMA(
struct pci_dev *pdev,
uint DeviceID,
uint UDMAEnable,
uint UDMATimingMode
);
#endif #endif
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7