Skip to content

L
linux
Commit 48e27874 authored by Adam Thomson's avatar Adam Thomson Committed by Mark Brown
Browse files
Options

ASoC: codecs: Add DA732x codec driver 

This patch adds support for Dialog DA732x audio codecs.
Signed-off-by: default avatarMichal Hajduk <Michal.Hajduk@diasemi.com>
Signed-off-by: default avatarAdam Thomson <Adam.Thomson@diasemi.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent af691fb6
Hide whitespace changes
Inline Side-by-side
Showing with 2420 additions and 0 deletions
sound/soc/codecs/Kconfig
View file @ 48e27874
...@@ -36,6 +36,7 @@ config SND_SOC_ALL_CODECS ...@@ -36,6 +36,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_CS4271 if SND_SOC_I2C_AND_SPI select SND_SOC_CS4271 if SND_SOC_I2C_AND_SPI
select SND_SOC_CX20442 select SND_SOC_CX20442
select SND_SOC_DA7210 if I2C select SND_SOC_DA7210 if I2C
select SND_SOC_DA732X if I2C
select SND_SOC_DFBMCS320 select SND_SOC_DFBMCS320
select SND_SOC_ISABELLE if I2C select SND_SOC_ISABELLE if I2C
select SND_SOC_JZ4740_CODEC select SND_SOC_JZ4740_CODEC
...@@ -224,6 +225,9 @@ config SND_SOC_L3 ...@@ -224,6 +225,9 @@ config SND_SOC_L3
config SND_SOC_DA7210 config SND_SOC_DA7210
tristate tristate
config SND_SOC_DA732X
tristate
config SND_SOC_DFBMCS320 config SND_SOC_DFBMCS320
tristate tristate
......
sound/soc/codecs/Makefile
View file @ 48e27874
...@@ -22,6 +22,7 @@ snd-soc-cs4270-objs := cs4270.o ...@@ -22,6 +22,7 @@ snd-soc-cs4270-objs := cs4270.o
snd-soc-cs4271-objs := cs4271.o snd-soc-cs4271-objs := cs4271.o
snd-soc-cx20442-objs := cx20442.o snd-soc-cx20442-objs := cx20442.o
snd-soc-da7210-objs := da7210.o snd-soc-da7210-objs := da7210.o
snd-soc-da732x-objs := da732x.o
snd-soc-dfbmcs320-objs := dfbmcs320.o snd-soc-dfbmcs320-objs := dfbmcs320.o
snd-soc-dmic-objs := dmic.o snd-soc-dmic-objs := dmic.o
snd-soc-isabelle-objs := isabelle.o snd-soc-isabelle-objs := isabelle.o
...@@ -135,6 +136,7 @@ obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o ...@@ -135,6 +136,7 @@ obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
obj-$(CONFIG_SND_SOC_CS4271) += snd-soc-cs4271.o obj-$(CONFIG_SND_SOC_CS4271) += snd-soc-cs4271.o
obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o
obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o
obj-$(CONFIG_SND_SOC_DA732X) += snd-soc-da732x.o
obj-$(CONFIG_SND_SOC_DFBMCS320) += snd-soc-dfbmcs320.o obj-$(CONFIG_SND_SOC_DFBMCS320) += snd-soc-dfbmcs320.o
obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o
obj-$(CONFIG_SND_SOC_ISABELLE) += snd-soc-isabelle.o obj-$(CONFIG_SND_SOC_ISABELLE) += snd-soc-isabelle.o
......
sound/soc/codecs/da732x.c 0 → 100644
View file @ 48e27874
/*
* da732x.c --- Dialog DA732X ALSA SoC Audio Driver
*
* Copyright (C) 2012 Dialog Semiconductor GmbH
*
* Author: Michal Hajduk <Michal.Hajduk@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <asm/div64.h>
#include "da732x.h"
#include "da732x_reg.h"
struct da732x_priv {
struct regmap *regmap;
struct snd_soc_codec *codec;
unsigned int sysclk;
bool pll_en;
};
/*
* da732x register cache - default settings
*/
static struct reg_default da732x_reg_cache[] = {
{ DA732X_REG_REF1 , 0x02 },
{ DA732X_REG_BIAS_EN , 0x80 },
{ DA732X_REG_BIAS1 , 0x00 },
{ DA732X_REG_BIAS2 , 0x00 },
{ DA732X_REG_BIAS3 , 0x00 },
{ DA732X_REG_BIAS4 , 0x00 },
{ DA732X_REG_MICBIAS2 , 0x00 },
{ DA732X_REG_MICBIAS1 , 0x00 },
{ DA732X_REG_MICDET , 0x00 },
{ DA732X_REG_MIC1_PRE , 0x01 },
{ DA732X_REG_MIC1 , 0x40 },
{ DA732X_REG_MIC2_PRE , 0x01 },
{ DA732X_REG_MIC2 , 0x40 },
{ DA732X_REG_AUX1L , 0x75 },
{ DA732X_REG_AUX1R , 0x75 },
{ DA732X_REG_MIC3_PRE , 0x01 },
{ DA732X_REG_MIC3 , 0x40 },
{ DA732X_REG_INP_PINBIAS , 0x00 },
{ DA732X_REG_INP_ZC_EN , 0x00 },
{ DA732X_REG_INP_MUX , 0x50 },
{ DA732X_REG_HP_DET , 0x00 },
{ DA732X_REG_HPL_DAC_OFFSET , 0x00 },
{ DA732X_REG_HPL_DAC_OFF_CNTL , 0x00 },
{ DA732X_REG_HPL_OUT_OFFSET , 0x00 },
{ DA732X_REG_HPL , 0x40 },
{ DA732X_REG_HPL_VOL , 0x0F },
{ DA732X_REG_HPR_DAC_OFFSET , 0x00 },
{ DA732X_REG_HPR_DAC_OFF_CNTL , 0x00 },
{ DA732X_REG_HPR_OUT_OFFSET , 0x00 },
{ DA732X_REG_HPR , 0x40 },
{ DA732X_REG_HPR_VOL , 0x0F },
{ DA732X_REG_LIN2 , 0x4F },
{ DA732X_REG_LIN3 , 0x4F },
{ DA732X_REG_LIN4 , 0x4F },
{ DA732X_REG_OUT_ZC_EN , 0x00 },
{ DA732X_REG_HP_LIN1_GNDSEL , 0x00 },
{ DA732X_REG_CP_HP1 , 0x0C },
{ DA732X_REG_CP_HP2 , 0x03 },
{ DA732X_REG_CP_CTRL1 , 0x00 },
{ DA732X_REG_CP_CTRL2 , 0x99 },
{ DA732X_REG_CP_CTRL3 , 0x25 },
{ DA732X_REG_CP_LEVEL_MASK , 0x3F },
{ DA732X_REG_CP_DET , 0x00 },
{ DA732X_REG_CP_STATUS , 0x00 },
{ DA732X_REG_CP_THRESH1 , 0x00 },
{ DA732X_REG_CP_THRESH2 , 0x00 },
{ DA732X_REG_CP_THRESH3 , 0x00 },
{ DA732X_REG_CP_THRESH4 , 0x00 },
{ DA732X_REG_CP_THRESH5 , 0x00 },
{ DA732X_REG_CP_THRESH6 , 0x00 },
{ DA732X_REG_CP_THRESH7 , 0x00 },
{ DA732X_REG_CP_THRESH8 , 0x00 },
{ DA732X_REG_PLL_DIV_LO , 0x00 },
{ DA732X_REG_PLL_DIV_MID , 0x00 },
{ DA732X_REG_PLL_DIV_HI , 0x00 },
{ DA732X_REG_PLL_CTRL , 0x02 },
{ DA732X_REG_CLK_CTRL , 0xaa },
{ DA732X_REG_CLK_DSP , 0x07 },
{ DA732X_REG_CLK_EN1 , 0x00 },
{ DA732X_REG_CLK_EN2 , 0x00 },
{ DA732X_REG_CLK_EN3 , 0x00 },
{ DA732X_REG_CLK_EN4 , 0x00 },
{ DA732X_REG_CLK_EN5 , 0x00 },
{ DA732X_REG_AIF_MCLK , 0x00 },
{ DA732X_REG_AIFA1 , 0x02 },
{ DA732X_REG_AIFA2 , 0x00 },
{ DA732X_REG_AIFA3 , 0x08 },
{ DA732X_REG_AIFB1 , 0x02 },
{ DA732X_REG_AIFB2 , 0x00 },
{ DA732X_REG_AIFB3 , 0x08 },
{ DA732X_REG_PC_CTRL , 0xC0 },
{ DA732X_REG_DATA_ROUTE , 0x00 },
{ DA732X_REG_DSP_CTRL , 0x00 },
{ DA732X_REG_CIF_CTRL2 , 0x00 },
{ DA732X_REG_HANDSHAKE , 0x00 },
{ DA732X_REG_SPARE1_OUT , 0x00 },
{ DA732X_REG_SPARE2_OUT , 0x00 },
{ DA732X_REG_SPARE1_IN , 0x00 },
{ DA732X_REG_ADC1_PD , 0x00 },
{ DA732X_REG_ADC1_HPF , 0x00 },
{ DA732X_REG_ADC1_SEL , 0x00 },
{ DA732X_REG_ADC1_EQ12 , 0x00 },
{ DA732X_REG_ADC1_EQ34 , 0x00 },
{ DA732X_REG_ADC1_EQ5 , 0x00 },
{ DA732X_REG_ADC2_PD , 0x00 },
{ DA732X_REG_ADC2_HPF , 0x00 },
{ DA732X_REG_ADC2_SEL , 0x00 },
{ DA732X_REG_ADC2_EQ12 , 0x00 },
{ DA732X_REG_ADC2_EQ34 , 0x00 },
{ DA732X_REG_ADC2_EQ5 , 0x00 },
{ DA732X_REG_DAC1_HPF , 0x00 },
{ DA732X_REG_DAC1_L_VOL , 0x00 },
{ DA732X_REG_DAC1_R_VOL , 0x00 },
{ DA732X_REG_DAC1_SEL , 0x00 },
{ DA732X_REG_DAC1_SOFTMUTE , 0x00 },
{ DA732X_REG_DAC1_EQ12 , 0x00 },
{ DA732X_REG_DAC1_EQ34 , 0x00 },
{ DA732X_REG_DAC1_EQ5 , 0x00 },
{ DA732X_REG_DAC2_HPF , 0x00 },
{ DA732X_REG_DAC2_L_VOL , 0x00 },
{ DA732X_REG_DAC2_R_VOL , 0x00 },
{ DA732X_REG_DAC2_SEL , 0x00 },
{ DA732X_REG_DAC2_SOFTMUTE , 0x00 },
{ DA732X_REG_DAC2_EQ12 , 0x00 },
{ DA732X_REG_DAC2_EQ34 , 0x00 },
{ DA732X_REG_DAC2_EQ5 , 0x00 },
{ DA732X_REG_DAC3_HPF , 0x00 },
{ DA732X_REG_DAC3_VOL , 0x00 },
{ DA732X_REG_DAC3_SEL , 0x00 },
{ DA732X_REG_DAC3_SOFTMUTE , 0x00 },
{ DA732X_REG_DAC3_EQ12 , 0x00 },
{ DA732X_REG_DAC3_EQ34 , 0x00 },
{ DA732X_REG_DAC3_EQ5 , 0x00 },
{ DA732X_REG_BIQ_BYP , 0x00 },
{ DA732X_REG_DMA_CMD , 0x00 },
{ DA732X_REG_DMA_ADDR0 , 0x00 },
{ DA732X_REG_DMA_ADDR1 , 0x00 },
{ DA732X_REG_DMA_DATA0 , 0x00 },
{ DA732X_REG_DMA_DATA1 , 0x00 },
{ DA732X_REG_DMA_DATA2 , 0x00 },
{ DA732X_REG_DMA_DATA3 , 0x00 },
{ DA732X_REG_UNLOCK , 0x00 },
};
static inline int da732x_get_input_div(struct snd_soc_codec *codec, int sysclk)
{
int val;
int ret;
if (sysclk < DA732X_MCLK_10MHZ) {
val = DA732X_MCLK_RET_0_10MHZ;
ret = DA732X_MCLK_VAL_0_10MHZ;
} else if ((sysclk >= DA732X_MCLK_10MHZ) &&
(sysclk < DA732X_MCLK_20MHZ)) {
val = DA732X_MCLK_RET_10_20MHZ;
ret = DA732X_MCLK_VAL_10_20MHZ;
} else if ((sysclk >= DA732X_MCLK_20MHZ) &&
(sysclk < DA732X_MCLK_40MHZ)) {
val = DA732X_MCLK_RET_20_40MHZ;
ret = DA732X_MCLK_VAL_20_40MHZ;
} else if ((sysclk >= DA732X_MCLK_40MHZ) &&
(sysclk <= DA732X_MCLK_54MHZ)) {
val = DA732X_MCLK_RET_40_54MHZ;
ret = DA732X_MCLK_VAL_40_54MHZ;
} else {
return -EINVAL;
}
snd_soc_write(codec, DA732X_REG_PLL_CTRL, val);
return ret;
}
static void da732x_set_charge_pump(struct snd_soc_codec *codec, int state)
{
switch (state) {
case DA732X_ENABLE_CP:
snd_soc_write(codec, DA732X_REG_CLK_EN2, DA732X_CP_CLK_EN);
snd_soc_write(codec, DA732X_REG_CP_HP2, DA732X_HP_CP_EN |
DA732X_HP_CP_REG | DA732X_HP_CP_PULSESKIP);
snd_soc_write(codec, DA732X_REG_CP_CTRL1, DA732X_CP_EN |
DA732X_CP_CTRL_CPVDD1);
snd_soc_write(codec, DA732X_REG_CP_CTRL2,
DA732X_CP_MANAGE_MAGNITUDE | DA732X_CP_BOOST);
snd_soc_write(codec, DA732X_REG_CP_CTRL3, DA732X_CP_1MHZ);
break;
case DA732X_DISABLE_CP:
snd_soc_write(codec, DA732X_REG_CLK_EN2, DA732X_CP_CLK_DIS);
snd_soc_write(codec, DA732X_REG_CP_HP2, DA732X_HP_CP_DIS);
snd_soc_write(codec, DA732X_REG_CP_CTRL1, DA723X_CP_DIS);
break;
default:
pr_err(KERN_ERR "Wrong charge pump state\n");
break;
}
}
static const DECLARE_TLV_DB_SCALE(mic_boost_tlv, DA732X_MIC_PRE_VOL_DB_MIN,
DA732X_MIC_PRE_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, DA732X_MIC_VOL_DB_MIN,
DA732X_MIC_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(aux_pga_tlv, DA732X_AUX_VOL_DB_MIN,
DA732X_AUX_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(hp_pga_tlv, DA732X_HP_VOL_DB_MIN,
DA732X_AUX_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(lin2_pga_tlv, DA732X_LIN2_VOL_DB_MIN,
DA732X_LIN2_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(lin3_pga_tlv, DA732X_LIN3_VOL_DB_MIN,
DA732X_LIN3_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(lin4_pga_tlv, DA732X_LIN4_VOL_DB_MIN,
DA732X_LIN4_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(adc_pga_tlv, DA732X_ADC_VOL_DB_MIN,
DA732X_ADC_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(dac_pga_tlv, DA732X_DAC_VOL_DB_MIN,
DA732X_DAC_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(eq_band_pga_tlv, DA732X_EQ_BAND_VOL_DB_MIN,
DA732X_EQ_BAND_VOL_DB_INC, 0);
static const DECLARE_TLV_DB_SCALE(eq_overall_tlv, DA732X_EQ_OVERALL_VOL_DB_MIN,
DA732X_EQ_OVERALL_VOL_DB_INC, 0);
/* High Pass Filter */
static const char *da732x_hpf_mode[] = {
"Disable", "Music", "Voice",
};
static const char *da732x_hpf_music[] = {
"1.8Hz", "3.75Hz", "7.5Hz", "15Hz",
};
static const char *da732x_hpf_voice[] = {
"2.5Hz", "25Hz", "50Hz", "100Hz",
"150Hz", "200Hz", "300Hz", "400Hz"
};
static const struct soc_enum da732x_dac1_hpf_mode_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_DAC1_HPF, DA732X_HPF_MODE_SHIFT,
DA732X_HPF_MODE_MAX, da732x_hpf_mode)
};
static const struct soc_enum da732x_dac2_hpf_mode_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_DAC2_HPF, DA732X_HPF_MODE_SHIFT,
DA732X_HPF_MODE_MAX, da732x_hpf_mode)
};
static const struct soc_enum da732x_dac3_hpf_mode_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_DAC3_HPF, DA732X_HPF_MODE_SHIFT,
DA732X_HPF_MODE_MAX, da732x_hpf_mode)
};
static const struct soc_enum da732x_adc1_hpf_mode_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_ADC1_HPF, DA732X_HPF_MODE_SHIFT,
DA732X_HPF_MODE_MAX, da732x_hpf_mode)
};
static const struct soc_enum da732x_adc2_hpf_mode_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_ADC2_HPF, DA732X_HPF_MODE_SHIFT,
DA732X_HPF_MODE_MAX, da732x_hpf_mode)
};
static const struct soc_enum da732x_dac1_hp_filter_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_DAC1_HPF, DA732X_HPF_MUSIC_SHIFT,
DA732X_HPF_MUSIC_MAX, da732x_hpf_music)
};
static const struct soc_enum da732x_dac2_hp_filter_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_DAC2_HPF, DA732X_HPF_MUSIC_SHIFT,
DA732X_HPF_MUSIC_MAX, da732x_hpf_music)
};
static const struct soc_enum da732x_dac3_hp_filter_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_DAC3_HPF, DA732X_HPF_MUSIC_SHIFT,
DA732X_HPF_MUSIC_MAX, da732x_hpf_music)
};
static const struct soc_enum da732x_adc1_hp_filter_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_ADC1_HPF, DA732X_HPF_MUSIC_SHIFT,
DA732X_HPF_MUSIC_MAX, da732x_hpf_music)
};
static const struct soc_enum da732x_adc2_hp_filter_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_ADC2_HPF, DA732X_HPF_MUSIC_SHIFT,
DA732X_HPF_MUSIC_MAX, da732x_hpf_music)
};
static const struct soc_enum da732x_dac1_voice_filter_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_DAC1_HPF, DA732X_HPF_VOICE_SHIFT,
DA732X_HPF_VOICE_MAX, da732x_hpf_voice)
};
static const struct soc_enum da732x_dac2_voice_filter_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_DAC2_HPF, DA732X_HPF_VOICE_SHIFT,
DA732X_HPF_VOICE_MAX, da732x_hpf_voice)
};
static const struct soc_enum da732x_dac3_voice_filter_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_DAC3_HPF, DA732X_HPF_VOICE_SHIFT,
DA732X_HPF_VOICE_MAX, da732x_hpf_voice)
};
static const struct soc_enum da732x_adc1_voice_filter_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_ADC1_HPF, DA732X_HPF_VOICE_SHIFT,
DA732X_HPF_VOICE_MAX, da732x_hpf_voice)
};
static const struct soc_enum da732x_adc2_voice_filter_enum[] = {
SOC_ENUM_SINGLE(DA732X_REG_ADC2_HPF, DA732X_HPF_VOICE_SHIFT,
DA732X_HPF_VOICE_MAX, da732x_hpf_voice)
};
static int da732x_hpf_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value;
unsigned int reg = enum_ctrl->reg;
unsigned int sel = ucontrol->value.integer.value[0];
unsigned int bits;
switch (sel) {
case DA732X_HPF_DISABLED:
bits = DA732X_HPF_DIS;
break;
case DA732X_HPF_VOICE:
bits = DA732X_HPF_VOICE_EN;
break;
case DA732X_HPF_MUSIC:
bits = DA732X_HPF_MUSIC_EN;
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, reg, DA732X_HPF_MASK, bits);
return 0;
}
static int da732x_hpf_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value;
unsigned int reg = enum_ctrl->reg;
int val;
val = snd_soc_read(codec, reg) & DA732X_HPF_MASK;
switch (val) {
case DA732X_HPF_VOICE_EN:
ucontrol->value.integer.value[0] = DA732X_HPF_VOICE;
break;
case DA732X_HPF_MUSIC_EN:
ucontrol->value.integer.value[0] = DA732X_HPF_MUSIC;
break;
default:
ucontrol->value.integer.value[0] = DA732X_HPF_DISABLED;
break;
}
return 0;
}
static const struct snd_kcontrol_new da732x_snd_controls[] = {
/* Input PGAs */
SOC_SINGLE_RANGE_TLV("MIC1 Boost Volume", DA732X_REG_MIC1_PRE,
DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
SOC_SINGLE_RANGE_TLV("MIC2 Boost Volume", DA732X_REG_MIC2_PRE,
DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
SOC_SINGLE_RANGE_TLV("MIC3 Boost Volume", DA732X_REG_MIC3_PRE,
DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
/* MICs */
SOC_SINGLE("MIC1 Switch", DA732X_REG_MIC1, DA732X_MIC_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_RANGE_TLV("MIC1 Volume", DA732X_REG_MIC1,
DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
SOC_SINGLE("MIC2 Switch", DA732X_REG_MIC2, DA732X_MIC_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_RANGE_TLV("MIC2 Volume", DA732X_REG_MIC2,
DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
SOC_SINGLE("MIC3 Switch", DA732X_REG_MIC3, DA732X_MIC_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_RANGE_TLV("MIC3 Volume", DA732X_REG_MIC3,
DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
/* AUXs */
SOC_SINGLE("AUX1L Switch", DA732X_REG_AUX1L, DA732X_AUX_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("AUX1L Volume", DA732X_REG_AUX1L,
DA732X_AUX_VOL_SHIFT, DA732X_AUX_VOL_VAL_MAX,
DA732X_NO_INVERT, aux_pga_tlv),
SOC_SINGLE("AUX1R Switch", DA732X_REG_AUX1R, DA732X_AUX_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("AUX1R Volume", DA732X_REG_AUX1R,
DA732X_AUX_VOL_SHIFT, DA732X_AUX_VOL_VAL_MAX,
DA732X_NO_INVERT, aux_pga_tlv),
/* ADCs */
SOC_DOUBLE_TLV("ADC1 Volume", DA732X_REG_ADC1_SEL,
DA732X_ADCL_VOL_SHIFT, DA732X_ADCR_VOL_SHIFT,
DA732X_ADC_VOL_VAL_MAX, DA732X_INVERT, adc_pga_tlv),
SOC_DOUBLE_TLV("ADC2 Volume", DA732X_REG_ADC2_SEL,
DA732X_ADCL_VOL_SHIFT, DA732X_ADCR_VOL_SHIFT,
DA732X_ADC_VOL_VAL_MAX, DA732X_INVERT, adc_pga_tlv),
/* DACs */
SOC_DOUBLE("Digital Playback DAC12 Switch", DA732X_REG_DAC1_SEL,
DA732X_DACL_MUTE_SHIFT, DA732X_DACR_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_DOUBLE_R_TLV("Digital Playback DAC12 Volume", DA732X_REG_DAC1_L_VOL,
DA732X_REG_DAC1_R_VOL, DA732X_DAC_VOL_SHIFT,
DA732X_DAC_VOL_VAL_MAX, DA732X_INVERT, dac_pga_tlv),
SOC_SINGLE("Digital Playback DAC3 Switch", DA732X_REG_DAC2_SEL,
DA732X_DACL_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Digital Playback DAC3 Volume", DA732X_REG_DAC2_L_VOL,
DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
DA732X_INVERT, dac_pga_tlv),
SOC_SINGLE("Digital Playback DAC4 Switch", DA732X_REG_DAC2_SEL,
DA732X_DACR_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Digital Playback DAC4 Volume", DA732X_REG_DAC2_R_VOL,
DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
DA732X_INVERT, dac_pga_tlv),
SOC_SINGLE("Digital Playback DAC5 Switch", DA732X_REG_DAC3_SEL,
DA732X_DACL_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Digital Playback DAC5 Volume", DA732X_REG_DAC3_VOL,
DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
DA732X_INVERT, dac_pga_tlv),
/* High Pass Filters */
SOC_ENUM_EXT("DAC1 High Pass Filter Mode",
da732x_dac1_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
SOC_ENUM("DAC1 High Pass Filter", da732x_dac1_hp_filter_enum),
SOC_ENUM("DAC1 Voice Filter", da732x_dac1_voice_filter_enum),
SOC_ENUM_EXT("DAC2 High Pass Filter Mode",
da732x_dac2_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
SOC_ENUM("DAC2 High Pass Filter", da732x_dac2_hp_filter_enum),
SOC_ENUM("DAC2 Voice Filter", da732x_dac2_voice_filter_enum),
SOC_ENUM_EXT("DAC3 High Pass Filter Mode",
da732x_dac3_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
SOC_ENUM("DAC3 High Pass Filter", da732x_dac3_hp_filter_enum),
SOC_ENUM("DAC3 Filter Mode", da732x_dac3_voice_filter_enum),
SOC_ENUM_EXT("ADC1 High Pass Filter Mode",
da732x_adc1_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
SOC_ENUM("ADC1 High Pass Filter", da732x_adc1_hp_filter_enum),
SOC_ENUM("ADC1 Voice Filter", da732x_adc1_voice_filter_enum),
SOC_ENUM_EXT("ADC2 High Pass Filter Mode",
da732x_adc2_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
SOC_ENUM("ADC2 High Pass Filter", da732x_adc2_hp_filter_enum),
SOC_ENUM("ADC2 Voice Filter", da732x_adc2_voice_filter_enum),
/* Equalizers */
SOC_SINGLE("ADC1 EQ Switch", DA732X_REG_ADC1_EQ5,
DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
SOC_SINGLE_TLV("ADC1 EQ Band 1 Volume", DA732X_REG_ADC1_EQ12,
DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC1 EQ Band 2 Volume", DA732X_REG_ADC1_EQ12,
DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC1 EQ Band 3 Volume", DA732X_REG_ADC1_EQ34,
DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC1 EQ Band 4 Volume", DA732X_REG_ADC1_EQ34,
DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC1 EQ Band 5 Volume", DA732X_REG_ADC1_EQ5,
DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC1 EQ Overall Volume", DA732X_REG_ADC1_EQ5,
DA732X_EQ_OVERALL_SHIFT, DA732X_EQ_OVERALL_VOL_VAL_MAX,
DA732X_INVERT, eq_overall_tlv),
SOC_SINGLE("ADC2 EQ Switch", DA732X_REG_ADC2_EQ5,
DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
SOC_SINGLE_TLV("ADC2 EQ Band 1 Volume", DA732X_REG_ADC2_EQ12,
DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC2 EQ Band 2 Volume", DA732X_REG_ADC2_EQ12,
DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC2 EQ Band 3 Volume", DA732X_REG_ADC2_EQ34,
DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ACD2 EQ Band 4 Volume", DA732X_REG_ADC2_EQ34,
DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ACD2 EQ Band 5 Volume", DA732X_REG_ADC2_EQ5,
DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("ADC2 EQ Overall Volume", DA732X_REG_ADC1_EQ5,
DA732X_EQ_OVERALL_SHIFT, DA732X_EQ_OVERALL_VOL_VAL_MAX,
DA732X_INVERT, eq_overall_tlv),
SOC_SINGLE("DAC1 EQ Switch", DA732X_REG_DAC1_EQ5,
DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
SOC_SINGLE_TLV("DAC1 EQ Band 1 Volume", DA732X_REG_DAC1_EQ12,
DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC1 EQ Band 2 Volume", DA732X_REG_DAC1_EQ12,
DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC1 EQ Band 3 Volume", DA732X_REG_DAC1_EQ34,
DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC1 EQ Band 4 Volume", DA732X_REG_DAC1_EQ34,
DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC1 EQ Band 5 Volume", DA732X_REG_DAC1_EQ5,
DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE("DAC2 EQ Switch", DA732X_REG_DAC2_EQ5,
DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
SOC_SINGLE_TLV("DAC2 EQ Band 1 Volume", DA732X_REG_DAC2_EQ12,
DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC2 EQ Band 2 Volume", DA732X_REG_DAC2_EQ12,
DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC2 EQ Band 3 Volume", DA732X_REG_DAC2_EQ34,
DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC2 EQ Band 4 Volume", DA732X_REG_DAC2_EQ34,
DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC2 EQ Band 5 Volume", DA732X_REG_DAC2_EQ5,
DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE("DAC3 EQ Switch", DA732X_REG_DAC3_EQ5,
DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
SOC_SINGLE_TLV("DAC3 EQ Band 1 Volume", DA732X_REG_DAC3_EQ12,
DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC3 EQ Band 2 Volume", DA732X_REG_DAC3_EQ12,
DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC3 EQ Band 3 Volume", DA732X_REG_DAC3_EQ34,
DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC3 EQ Band 4 Volume", DA732X_REG_DAC3_EQ34,
DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
SOC_SINGLE_TLV("DAC3 EQ Band 5 Volume", DA732X_REG_DAC3_EQ5,
DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
DA732X_INVERT, eq_band_pga_tlv),
/* Lineout 2 Reciever*/
SOC_SINGLE("Lineout 2 Switch", DA732X_REG_LIN2, DA732X_LOUT_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Lineout 2 Volume", DA732X_REG_LIN2,
DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
DA732X_NO_INVERT, lin2_pga_tlv),
/* Lineout 3 SPEAKER*/
SOC_SINGLE("Lineout 3 Switch", DA732X_REG_LIN3, DA732X_LOUT_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Lineout 3 Volume", DA732X_REG_LIN3,
DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
DA732X_NO_INVERT, lin3_pga_tlv),
/* Lineout 4 */
SOC_SINGLE("Lineout 4 Switch", DA732X_REG_LIN4, DA732X_LOUT_MUTE_SHIFT,
DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_SINGLE_TLV("Lineout 4 Volume", DA732X_REG_LIN4,
DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
DA732X_NO_INVERT, lin4_pga_tlv),
/* Headphones */
SOC_DOUBLE_R("Headphone Switch", DA732X_REG_HPR, DA732X_REG_HPL,
DA732X_HP_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
SOC_DOUBLE_R_TLV("Headphone Volume", DA732X_REG_HPL_VOL,
DA732X_REG_HPR_VOL, DA732X_HP_VOL_SHIFT,
DA732X_HP_VOL_VAL_MAX, DA732X_NO_INVERT, hp_pga_tlv),
};
static int da732x_adc_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
switch (w->reg) {
case DA732X_REG_ADC1_PD:
snd_soc_update_bits(codec, DA732X_REG_CLK_EN3,
DA732X_ADCA_BB_CLK_EN,
DA732X_ADCA_BB_CLK_EN);
break;
case DA732X_REG_ADC2_PD:
snd_soc_update_bits(codec, DA732X_REG_CLK_EN3,
DA732X_ADCC_BB_CLK_EN,
DA732X_ADCC_BB_CLK_EN);
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, w->reg, DA732X_ADC_RST_MASK,
DA732X_ADC_SET_ACT);
snd_soc_update_bits(codec, w->reg, DA732X_ADC_PD_MASK,
DA732X_ADC_ON);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_update_bits(codec, w->reg, DA732X_ADC_PD_MASK,
DA732X_ADC_OFF);
snd_soc_update_bits(codec, w->reg, DA732X_ADC_RST_MASK,
DA732X_ADC_SET_RST);
switch (w->reg) {
case DA732X_REG_ADC1_PD:
snd_soc_update_bits(codec, DA732X_REG_CLK_EN3,
DA732X_ADCA_BB_CLK_EN, 0);
break;
case DA732X_REG_ADC2_PD:
snd_soc_update_bits(codec, DA732X_REG_CLK_EN3,
DA732X_ADCC_BB_CLK_EN, 0);
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return 0;
}
static int da732x_out_pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, w->reg,
(1 << w->shift) | DA732X_OUT_HIZ_EN,
(1 << w->shift) | DA732X_OUT_HIZ_EN);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_update_bits(codec, w->reg,
(1 << w->shift) | DA732X_OUT_HIZ_EN,
(1 << w->shift) | DA732X_OUT_HIZ_DIS);
break;
default:
return -EINVAL;
}
return 0;
}
static const char *adcl_text[] = {
"AUX1L", "MIC1"
};
static const char *adcr_text[] = {
"AUX1R", "MIC2", "MIC3"
};
static const char *enable_text[] = {
"Disabled",
"Enabled"
};
/* ADC1LMUX */
static const struct soc_enum adc1l_enum =
SOC_ENUM_SINGLE(DA732X_REG_INP_MUX, DA732X_ADC1L_MUX_SEL_SHIFT,
DA732X_ADCL_MUX_MAX, adcl_text);
static const struct snd_kcontrol_new adc1l_mux =
SOC_DAPM_ENUM("ADC Route", adc1l_enum);
/* ADC1RMUX */
static const struct soc_enum adc1r_enum =
SOC_ENUM_SINGLE(DA732X_REG_INP_MUX, DA732X_ADC1R_MUX_SEL_SHIFT,
DA732X_ADCR_MUX_MAX, adcr_text);
static const struct snd_kcontrol_new adc1r_mux =
SOC_DAPM_ENUM("ADC Route", adc1r_enum);
/* ADC2LMUX */
static const struct soc_enum adc2l_enum =
SOC_ENUM_SINGLE(DA732X_REG_INP_MUX, DA732X_ADC2L_MUX_SEL_SHIFT,
DA732X_ADCL_MUX_MAX, adcl_text);
static const struct snd_kcontrol_new adc2l_mux =
SOC_DAPM_ENUM("ADC Route", adc2l_enum);
/* ADC2RMUX */
static const struct soc_enum adc2r_enum =
SOC_ENUM_SINGLE(DA732X_REG_INP_MUX, DA732X_ADC2R_MUX_SEL_SHIFT,
DA732X_ADCR_MUX_MAX, adcr_text);
static const struct snd_kcontrol_new adc2r_mux =
SOC_DAPM_ENUM("ADC Route", adc2r_enum);
static const struct soc_enum da732x_hp_left_output =
SOC_ENUM_SINGLE(DA732X_REG_HPL, DA732X_HP_OUT_DAC_EN_SHIFT,
DA732X_DAC_EN_MAX, enable_text);
static const struct snd_kcontrol_new hpl_mux =
SOC_DAPM_ENUM("HPL Switch", da732x_hp_left_output);
static const struct soc_enum da732x_hp_right_output =
SOC_ENUM_SINGLE(DA732X_REG_HPR, DA732X_HP_OUT_DAC_EN_SHIFT,
DA732X_DAC_EN_MAX, enable_text);
static const struct snd_kcontrol_new hpr_mux =
SOC_DAPM_ENUM("HPR Switch", da732x_hp_right_output);
static const struct soc_enum da732x_speaker_output =
SOC_ENUM_SINGLE(DA732X_REG_LIN3, DA732X_LOUT_DAC_EN_SHIFT,
DA732X_DAC_EN_MAX, enable_text);
static const struct snd_kcontrol_new spk_mux =
SOC_DAPM_ENUM("SPK Switch", da732x_speaker_output);
static const struct soc_enum da732x_lout4_output =
SOC_ENUM_SINGLE(DA732X_REG_LIN4, DA732X_LOUT_DAC_EN_SHIFT,
DA732X_DAC_EN_MAX, enable_text);
static const struct snd_kcontrol_new lout4_mux =
SOC_DAPM_ENUM("LOUT4 Switch", da732x_lout4_output);
static const struct soc_enum da732x_lout2_output =
SOC_ENUM_SINGLE(DA732X_REG_LIN2, DA732X_LOUT_DAC_EN_SHIFT,
DA732X_DAC_EN_MAX, enable_text);
static const struct snd_kcontrol_new lout2_mux =
SOC_DAPM_ENUM("LOUT2 Switch", da732x_lout2_output);
static const struct snd_soc_dapm_widget da732x_dapm_widgets[] = {
/* Supplies */
SND_SOC_DAPM_SUPPLY("ADC1 Supply", DA732X_REG_ADC1_PD, 0,
DA732X_NO_INVERT, da732x_adc_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ADC2 Supply", DA732X_REG_ADC2_PD, 0,
DA732X_NO_INVERT, da732x_adc_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DAC1 CLK", DA732X_REG_CLK_EN4,
DA732X_DACA_BB_CLK_SHIFT, DA732X_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC2 CLK", DA732X_REG_CLK_EN4,
DA732X_DACC_BB_CLK_SHIFT, DA732X_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC3 CLK", DA732X_REG_CLK_EN5,
DA732X_DACE_BB_CLK_SHIFT, DA732X_NO_INVERT,
NULL, 0),
/* Micbias */
SND_SOC_DAPM_SUPPLY("MICBIAS1", DA732X_REG_MICBIAS1,
DA732X_MICBIAS_EN_SHIFT,
DA732X_NO_INVERT, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", DA732X_REG_MICBIAS2,
DA732X_MICBIAS_EN_SHIFT,
DA732X_NO_INVERT, NULL, 0),
/* Inputs */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("MIC3"),
SND_SOC_DAPM_INPUT("AUX1L"),
SND_SOC_DAPM_INPUT("AUX1R"),
/* Outputs */
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
SND_SOC_DAPM_OUTPUT("ClassD"),
/* ADCs */
SND_SOC_DAPM_ADC("ADC1L", NULL, DA732X_REG_ADC1_SEL,
DA732X_ADCL_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_ADC("ADC1R", NULL, DA732X_REG_ADC1_SEL,
DA732X_ADCR_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_ADC("ADC2L", NULL, DA732X_REG_ADC2_SEL,
DA732X_ADCL_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_ADC("ADC2R", NULL, DA732X_REG_ADC2_SEL,
DA732X_ADCR_EN_SHIFT, DA732X_NO_INVERT),
/* DACs */
SND_SOC_DAPM_DAC("DAC1L", NULL, DA732X_REG_DAC1_SEL,
DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_DAC("DAC1R", NULL, DA732X_REG_DAC1_SEL,
DA732X_DACR_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_DAC("DAC2L", NULL, DA732X_REG_DAC2_SEL,
DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_DAC("DAC2R", NULL, DA732X_REG_DAC2_SEL,
DA732X_DACR_EN_SHIFT, DA732X_NO_INVERT),
SND_SOC_DAPM_DAC("DAC3", NULL, DA732X_REG_DAC3_SEL,
DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
/* Input Pgas */
SND_SOC_DAPM_PGA("MIC1 PGA", DA732X_REG_MIC1, DA732X_MIC_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("MIC2 PGA", DA732X_REG_MIC2, DA732X_MIC_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("MIC3 PGA", DA732X_REG_MIC3, DA732X_MIC_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("AUX1L PGA", DA732X_REG_AUX1L, DA732X_AUX_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("AUX1R PGA", DA732X_REG_AUX1R, DA732X_AUX_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA_E("HP Left", DA732X_REG_HPL, DA732X_HP_OUT_EN_SHIFT,
0, NULL, 0, da732x_out_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("HP Right", DA732X_REG_HPR, DA732X_HP_OUT_EN_SHIFT,
0, NULL, 0, da732x_out_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LIN2", DA732X_REG_LIN2, DA732X_LIN_OUT_EN_SHIFT,
0, NULL, 0, da732x_out_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LIN3", DA732X_REG_LIN3, DA732X_LIN_OUT_EN_SHIFT,
0, NULL, 0, da732x_out_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("LIN4", DA732X_REG_LIN4, DA732X_LIN_OUT_EN_SHIFT,
0, NULL, 0, da732x_out_pga_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
/* MUXs */
SND_SOC_DAPM_MUX("ADC1 Left MUX", SND_SOC_NOPM, 0, 0, &adc1l_mux),
SND_SOC_DAPM_MUX("ADC1 Right MUX", SND_SOC_NOPM, 0, 0, &adc1r_mux),
SND_SOC_DAPM_MUX("ADC2 Left MUX", SND_SOC_NOPM, 0, 0, &adc2l_mux),
SND_SOC_DAPM_MUX("ADC2 Right MUX", SND_SOC_NOPM, 0, 0, &adc2r_mux),
SND_SOC_DAPM_MUX("HP Left MUX", SND_SOC_NOPM, 0, 0, &hpl_mux),
SND_SOC_DAPM_MUX("HP Right MUX", SND_SOC_NOPM, 0, 0, &hpr_mux),
SND_SOC_DAPM_MUX("Speaker MUX", SND_SOC_NOPM, 0, 0, &spk_mux),
SND_SOC_DAPM_MUX("LOUT2 MUX", SND_SOC_NOPM, 0, 0, &lout2_mux),
SND_SOC_DAPM_MUX("LOUT4 MUX", SND_SOC_NOPM, 0, 0, &lout4_mux),
/* AIF interfaces */
SND_SOC_DAPM_AIF_OUT("AIFA Output", "AIFA Capture", 0, DA732X_REG_AIFA3,
DA732X_AIF_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIFA Input", "AIFA Playback", 0, DA732X_REG_AIFA3,
DA732X_AIF_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIFB Output", "AIFB Capture", 0, DA732X_REG_AIFB3,
DA732X_AIF_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIFB Input", "AIFB Playback", 0, DA732X_REG_AIFB3,
DA732X_AIF_EN_SHIFT, 0),
};
static const struct snd_soc_dapm_route da732x_dapm_routes[] = {
/* Inputs */
{"AUX1L PGA", "NULL", "AUX1L"},
{"AUX1R PGA", "NULL", "AUX1R"},
{"MIC1 PGA", NULL, "MIC1"},
{"MIC2 PGA", "NULL", "MIC2"},
{"MIC3 PGA", "NULL", "MIC3"},
/* Capture Path */
{"ADC1 Left MUX", "MIC1", "MIC1 PGA"},
{"ADC1 Left MUX", "AUX1L", "AUX1L PGA"},
{"ADC1 Right MUX", "AUX1R", "AUX1R PGA"},
{"ADC1 Right MUX", "MIC2", "MIC2 PGA"},
{"ADC1 Right MUX", "MIC3", "MIC3 PGA"},
{"ADC2 Left MUX", "AUX1L", "AUX1L PGA"},
{"ADC2 Left MUX", "MIC1", "MIC1 PGA"},
{"ADC2 Right MUX", "AUX1R", "AUX1R PGA"},
{"ADC2 Right MUX", "MIC2", "MIC2 PGA"},
{"ADC2 Right MUX", "MIC3", "MIC3 PGA"},
{"ADC1L", NULL, "ADC1 Supply"},
{"ADC1R", NULL, "ADC1 Supply"},
{"ADC2L", NULL, "ADC2 Supply"},
{"ADC2R", NULL, "ADC2 Supply"},
{"ADC1L", NULL, "ADC1 Left MUX"},
{"ADC1R", NULL, "ADC1 Right MUX"},
{"ADC2L", NULL, "ADC2 Left MUX"},
{"ADC2R", NULL, "ADC2 Right MUX"},
{"AIFA Output", NULL, "ADC1L"},
{"AIFA Output", NULL, "ADC1R"},
{"AIFB Output", NULL, "ADC2L"},
{"AIFB Output", NULL, "ADC2R"},
{"HP Left MUX", "Enabled", "AIFA Input"},
{"HP Right MUX", "Enabled", "AIFA Input"},
{"Speaker MUX", "Enabled", "AIFB Input"},
{"LOUT2 MUX", "Enabled", "AIFB Input"},
{"LOUT4 MUX", "Enabled", "AIFB Input"},
{"DAC1L", NULL, "DAC1 CLK"},
{"DAC1R", NULL, "DAC1 CLK"},
{"DAC2L", NULL, "DAC2 CLK"},
{"DAC2R", NULL, "DAC2 CLK"},
{"DAC3", NULL, "DAC3 CLK"},
{"DAC1L", NULL, "HP Left MUX"},
{"DAC1R", NULL, "HP Right MUX"},
{"DAC2L", NULL, "Speaker MUX"},
{"DAC2R", NULL, "LOUT4 MUX"},
{"DAC3", NULL, "LOUT2 MUX"},
/* Output Pgas */
{"HP Left", NULL, "DAC1L"},
{"HP Right", NULL, "DAC1R"},
{"LIN3", NULL, "DAC2L"},
{"LIN4", NULL, "DAC2R"},
{"LIN2", NULL, "DAC3"},
/* Outputs */
{"ClassD", NULL, "LIN3"},
{"LOUTL", NULL, "LIN2"},
{"LOUTR", NULL, "LIN4"},
{"HPL", NULL, "HP Left"},
{"HPR", NULL, "HP Right"},
};
static int da732x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
u32 aif = 0;
u32 reg_aif;
u32 fs;
reg_aif = dai->driver->base;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
aif |= DA732X_AIF_WORD_16;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
aif |= DA732X_AIF_WORD_20;
break;
case SNDRV_PCM_FORMAT_S24_LE:
aif |= DA732X_AIF_WORD_24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
aif |= DA732X_AIF_WORD_32;
break;
default:
return -EINVAL;
}
switch (params_rate(params)) {
case 8000:
fs = DA732X_SR_8KHZ;
break;
case 11025:
fs = DA732X_SR_11_025KHZ;
break;
case 12000:
fs = DA732X_SR_12KHZ;
break;
case 16000:
fs = DA732X_SR_16KHZ;
break;
case 22050:
fs = DA732X_SR_22_05KHZ;
break;
case 24000:
fs = DA732X_SR_24KHZ;
break;
case 32000:
fs = DA732X_SR_32KHZ;
break;
case 44100:
fs = DA732X_SR_44_1KHZ;
break;
case 48000:
fs = DA732X_SR_48KHZ;
break;
case 88100:
fs = DA732X_SR_88_1KHZ;
break;
case 96000:
fs = DA732X_SR_96KHZ;
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, reg_aif, DA732X_AIF_WORD_MASK, aif);
snd_soc_update_bits(codec, DA732X_REG_CLK_CTRL, DA732X_SR1_MASK, fs);
return 0;
}
static int da732x_set_dai_fmt(struct snd_soc_dai *dai, u32 fmt)
{
struct snd_soc_codec *codec = dai->codec;
u32 aif_mclk, pc_count;
u32 reg_aif1, aif1;
u32 reg_aif3, aif3;
switch (dai->id) {
case DA732X_DAI_ID1:
reg_aif1 = DA732X_REG_AIFA1;
reg_aif3 = DA732X_REG_AIFA3;
pc_count = DA732X_PC_PULSE_AIFA | DA732X_PC_RESYNC_NOT_AUT |
DA732X_PC_SAME;
break;
case DA732X_DAI_ID2:
reg_aif1 = DA732X_REG_AIFB1;
reg_aif3 = DA732X_REG_AIFB3;
pc_count = DA732X_PC_PULSE_AIFB | DA732X_PC_RESYNC_NOT_AUT |
DA732X_PC_SAME;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
aif1 = DA732X_AIF_SLAVE;
aif_mclk = DA732X_AIFM_FRAME_64 | DA732X_AIFM_SRC_SEL_AIFA;
break;
case SND_SOC_DAIFMT_CBM_CFM:
aif1 = DA732X_AIF_CLK_FROM_SRC;
aif_mclk = DA732X_CLK_GENERATION_AIF_A;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
aif3 = DA732X_AIF_I2S_MODE;
break;
case SND_SOC_DAIFMT_RIGHT_J:
aif3 = DA732X_AIF_RIGHT_J_MODE;
break;
case SND_SOC_DAIFMT_LEFT_J:
aif3 = DA732X_AIF_LEFT_J_MODE;
break;
case SND_SOC_DAIFMT_DSP_B:
aif3 = DA732X_AIF_DSP_MODE;
break;
default:
return -EINVAL;
}
/* Clock inversion */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif3 |= DA732X_AIF_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif3 |= DA732X_AIF_BCLK_INV | DA732X_AIF_WCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif3 |= DA732X_AIF_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif3 |= DA732X_AIF_WCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_write(codec, DA732X_REG_AIF_MCLK, aif_mclk);
snd_soc_update_bits(codec, reg_aif1, DA732X_AIF1_CLK_MASK, aif1);
snd_soc_update_bits(codec, reg_aif3, DA732X_AIF_BCLK_INV |
DA732X_AIF_WCLK_INV | DA732X_AIF_MODE_MASK, aif3);
snd_soc_write(codec, DA732X_REG_PC_CTRL, pc_count);
return 0;
}
static int da732x_set_dai_pll(struct snd_soc_codec *codec, int pll_id,
int source, unsigned int freq_in,
unsigned int freq_out)
{
struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec);
int fref, indiv;
u8 div_lo, div_mid, div_hi;
u64 frac_div;
/* Disable PLL */
if (freq_out == 0) {
snd_soc_update_bits(codec, DA732X_REG_PLL_CTRL,
DA732X_PLL_EN, 0);
da732x->pll_en = false;
return 0;
}
if (da732x->pll_en)
return -EBUSY;
if (source == DA732X_SRCCLK_MCLK) {
/* Validate Sysclk rate */
switch (da732x->sysclk) {
case 11290000:
case 12288000:
case 22580000:
case 24576000:
case 45160000:
case 49152000:
snd_soc_write(codec, DA732X_REG_PLL_CTRL,
DA732X_PLL_BYPASS);
return 0;
default:
dev_err(codec->dev,
"Cannot use PLL Bypass, invalid SYSCLK rate\n");
return -EINVAL;
}
}
indiv = da732x_get_input_div(codec, da732x->sysclk);
if (indiv < 0)
return indiv;
fref = (da732x->sysclk / indiv);
div_hi = freq_out / fref;
frac_div = (u64)(freq_out % fref) * 8192ULL;
do_div(frac_div, fref);
div_mid = (frac_div >> DA732X_1BYTE_SHIFT) & DA732X_U8_MASK;
div_lo = (frac_div) & DA732X_U8_MASK;
snd_soc_write(codec, DA732X_REG_PLL_DIV_LO, div_lo);
snd_soc_write(codec, DA732X_REG_PLL_DIV_MID, div_mid);
snd_soc_write(codec, DA732X_REG_PLL_DIV_HI, div_hi);
snd_soc_update_bits(codec, DA732X_REG_PLL_CTRL, DA732X_PLL_EN,
DA732X_PLL_EN);
da732x->pll_en = true;
return 0;
}
static int da732x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_codec *codec = dai->codec;
struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec);
da732x->sysclk = freq;
return 0;
}
#define DA732X_RATES SNDRV_PCM_RATE_8000_96000
#define DA732X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_ops da732x_dai1_ops = {
.hw_params = da732x_hw_params,
.set_fmt = da732x_set_dai_fmt,
.set_sysclk = da732x_set_dai_sysclk,
};
static struct snd_soc_dai_ops da732x_dai2_ops = {
.hw_params = da732x_hw_params,
.set_fmt = da732x_set_dai_fmt,
.set_sysclk = da732x_set_dai_sysclk,
};
static struct snd_soc_dai_driver da732x_dai[] = {
{
.name = "DA732X_AIFA",
.id = DA732X_DAI_ID1,
.base = DA732X_REG_AIFA1,
.playback = {
.stream_name = "AIFA Playback",
.channels_min = 1,
.channels_max = 2,
.rates = DA732X_RATES,
.formats = DA732X_FORMATS,
},
.capture = {
.stream_name = "AIFA Capture",
.channels_min = 1,
.channels_max = 2,
.rates = DA732X_RATES,
.formats = DA732X_FORMATS,
},
.ops = &da732x_dai1_ops,
},
{
.name = "DA732X_AIFB",
.id = DA732X_DAI_ID2,
.base = DA732X_REG_AIFB1,
.playback = {
.stream_name = "AIFB Playback",
.channels_min = 1,
.channels_max = 2,
.rates = DA732X_RATES,
.formats = DA732X_FORMATS,
},
.capture = {
.stream_name = "AIFB Capture",
.channels_min = 1,
.channels_max = 2,
.rates = DA732X_RATES,
.formats = DA732X_FORMATS,
},
.ops = &da732x_dai2_ops,
},
};
static const struct regmap_config da732x_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = DA732X_MAX_REG,
.reg_defaults = da732x_reg_cache,
.num_reg_defaults = ARRAY_SIZE(da732x_reg_cache),
.cache_type = REGCACHE_RBTREE,
};
static void da732x_dac_offset_adjust(struct snd_soc_codec *codec)
{
u8 offset[DA732X_HP_DACS];
u8 sign[DA732X_HP_DACS];
u8 step = DA732X_DAC_OFFSET_STEP;
/* Initialize DAC offset calibration circuits and registers */
snd_soc_write(codec, DA732X_REG_HPL_DAC_OFFSET,
DA732X_HP_DAC_OFFSET_TRIM_VAL);
snd_soc_write(codec, DA732X_REG_HPR_DAC_OFFSET,
DA732X_HP_DAC_OFFSET_TRIM_VAL);
snd_soc_write(codec, DA732X_REG_HPL_DAC_OFF_CNTL,
DA732X_HP_DAC_OFF_CALIBRATION |
DA732X_HP_DAC_OFF_SCALE_STEPS);
snd_soc_write(codec, DA732X_REG_HPR_DAC_OFF_CNTL,
DA732X_HP_DAC_OFF_CALIBRATION |
DA732X_HP_DAC_OFF_SCALE_STEPS);
/* Wait for voltage stabilization */
msleep(DA732X_WAIT_FOR_STABILIZATION);
/* Check DAC offset sign */
sign[DA732X_HPL_DAC] = (codec->hw_read(codec, DA732X_REG_HPL_DAC_OFF_CNTL) &
DA732X_HP_DAC_OFF_CNTL_COMPO);
sign[DA732X_HPR_DAC] = (codec->hw_read(codec, DA732X_REG_HPR_DAC_OFF_CNTL) &
DA732X_HP_DAC_OFF_CNTL_COMPO);
/* Binary search DAC offset values (both channels at once) */
offset[DA732X_HPL_DAC] = sign[DA732X_HPL_DAC] << DA732X_HP_DAC_COMPO_SHIFT;
offset[DA732X_HPR_DAC] = sign[DA732X_HPR_DAC] << DA732X_HP_DAC_COMPO_SHIFT;
do {
offset[DA732X_HPL_DAC] |= step;
offset[DA732X_HPR_DAC] |= step;
snd_soc_write(codec, DA732X_REG_HPL_DAC_OFFSET,
~offset[DA732X_HPL_DAC] & DA732X_HP_DAC_OFF_MASK);
snd_soc_write(codec, DA732X_REG_HPR_DAC_OFFSET,
~offset[DA732X_HPR_DAC] & DA732X_HP_DAC_OFF_MASK);
msleep(DA732X_WAIT_FOR_STABILIZATION);
if ((codec->hw_read(codec, DA732X_REG_HPL_DAC_OFF_CNTL) &
DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPL_DAC])
offset[DA732X_HPL_DAC] &= ~step;
if ((codec->hw_read(codec, DA732X_REG_HPR_DAC_OFF_CNTL) &
DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPR_DAC])
offset[DA732X_HPR_DAC] &= ~step;
step >>= 1;
} while (step);
/* Write final DAC offsets to registers */
snd_soc_write(codec, DA732X_REG_HPL_DAC_OFFSET,
~offset[DA732X_HPL_DAC] & DA732X_HP_DAC_OFF_MASK);
snd_soc_write(codec, DA732X_REG_HPR_DAC_OFFSET,
~offset[DA732X_HPR_DAC] & DA732X_HP_DAC_OFF_MASK);
/* End DAC calibration mode */
snd_soc_write(codec, DA732X_REG_HPL_DAC_OFF_CNTL,
DA732X_HP_DAC_OFF_SCALE_STEPS);
snd_soc_write(codec, DA732X_REG_HPR_DAC_OFF_CNTL,
DA732X_HP_DAC_OFF_SCALE_STEPS);
}
static void da732x_output_offset_adjust(struct snd_soc_codec *codec)
{
u8 offset[DA732X_HP_AMPS];
u8 sign[DA732X_HP_AMPS];
u8 step = DA732X_OUTPUT_OFFSET_STEP;
offset[DA732X_HPL_AMP] = DA732X_HP_OUT_TRIM_VAL;
offset[DA732X_HPR_AMP] = DA732X_HP_OUT_TRIM_VAL;
/* Initialize output offset calibration circuits and registers */
snd_soc_write(codec, DA732X_REG_HPL_OUT_OFFSET, DA732X_HP_OUT_TRIM_VAL);
snd_soc_write(codec, DA732X_REG_HPR_OUT_OFFSET, DA732X_HP_OUT_TRIM_VAL);
snd_soc_write(codec, DA732X_REG_HPL,
DA732X_HP_OUT_COMP | DA732X_HP_OUT_EN);
snd_soc_write(codec, DA732X_REG_HPR,
DA732X_HP_OUT_COMP | DA732X_HP_OUT_EN);
/* Wait for voltage stabilization */
msleep(DA732X_WAIT_FOR_STABILIZATION);
/* Check output offset sign */
sign[DA732X_HPL_AMP] = codec->hw_read(codec, DA732X_REG_HPL) &
DA732X_HP_OUT_COMPO;
sign[DA732X_HPR_AMP] = codec->hw_read(codec, DA732X_REG_HPR) &
DA732X_HP_OUT_COMPO;
snd_soc_write(codec, DA732X_REG_HPL, DA732X_HP_OUT_COMP |
(sign[DA732X_HPL_AMP] >> DA732X_HP_OUT_COMPO_SHIFT) |
DA732X_HP_OUT_EN);
snd_soc_write(codec, DA732X_REG_HPR, DA732X_HP_OUT_COMP |
(sign[DA732X_HPR_AMP] >> DA732X_HP_OUT_COMPO_SHIFT) |
DA732X_HP_OUT_EN);
/* Binary search output offset values (both channels at once) */
do {
offset[DA732X_HPL_AMP] |= step;
offset[DA732X_HPR_AMP] |= step;
snd_soc_write(codec, DA732X_REG_HPL_OUT_OFFSET,
offset[DA732X_HPL_AMP]);
snd_soc_write(codec, DA732X_REG_HPR_OUT_OFFSET,
offset[DA732X_HPR_AMP]);
msleep(DA732X_WAIT_FOR_STABILIZATION);
if ((codec->hw_read(codec, DA732X_REG_HPL) &
DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPL_AMP])
offset[DA732X_HPL_AMP] &= ~step;
if ((codec->hw_read(codec, DA732X_REG_HPR) &
DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPR_AMP])
offset[DA732X_HPR_AMP] &= ~step;
step >>= 1;
} while (step);
/* Write final DAC offsets to registers */
snd_soc_write(codec, DA732X_REG_HPL_OUT_OFFSET, offset[DA732X_HPL_AMP]);
snd_soc_write(codec, DA732X_REG_HPR_OUT_OFFSET, offset[DA732X_HPR_AMP]);
}
static void da732x_hp_dc_offset_cancellation(struct snd_soc_codec *codec)
{
/* Make sure that we have Soft Mute enabled */
snd_soc_write(codec, DA732X_REG_DAC1_SOFTMUTE, DA732X_SOFTMUTE_EN |
DA732X_GAIN_RAMPED | DA732X_16_SAMPLES);
snd_soc_write(codec, DA732X_REG_DAC1_SEL, DA732X_DACL_EN |
DA732X_DACR_EN | DA732X_DACL_SDM | DA732X_DACR_SDM |
DA732X_DACL_MUTE | DA732X_DACR_MUTE);
snd_soc_write(codec, DA732X_REG_HPL, DA732X_HP_OUT_DAC_EN |
DA732X_HP_OUT_MUTE | DA732X_HP_OUT_EN);
snd_soc_write(codec, DA732X_REG_HPR, DA732X_HP_OUT_EN |
DA732X_HP_OUT_MUTE | DA732X_HP_OUT_DAC_EN);
da732x_dac_offset_adjust(codec);
da732x_output_offset_adjust(codec);
snd_soc_write(codec, DA732X_REG_DAC1_SEL, DA732X_DACS_DIS);
snd_soc_write(codec, DA732X_REG_HPL, DA732X_HP_DIS);
snd_soc_write(codec, DA732X_REG_HPR, DA732X_HP_DIS);
}
static int da732x_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec);
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_update_bits(codec, DA732X_REG_BIAS_EN,
DA732X_BIAS_BOOST_MASK,
DA732X_BIAS_BOOST_100PC);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
/* Init Codec */
snd_soc_write(codec, DA732X_REG_REF1,
DA732X_VMID_FASTCHG);
snd_soc_write(codec, DA732X_REG_BIAS_EN,
DA732X_BIAS_EN);
mdelay(DA732X_STARTUP_DELAY);
/* Disable Fast Charge and enable DAC ref voltage */
snd_soc_write(codec, DA732X_REG_REF1,
DA732X_REFBUFX2_EN);
/* Enable bypass DSP routing */
snd_soc_write(codec, DA732X_REG_DATA_ROUTE,
DA732X_BYPASS_DSP);
/* Enable Digital subsystem */
snd_soc_write(codec, DA732X_REG_DSP_CTRL,
DA732X_DIGITAL_EN);
snd_soc_write(codec, DA732X_REG_SPARE1_OUT,
DA732X_HP_DRIVER_EN |
DA732X_HP_GATE_LOW |
DA732X_HP_LOOP_GAIN_CTRL);
snd_soc_write(codec, DA732X_REG_HP_LIN1_GNDSEL,
DA732X_HP_OUT_GNDSEL);
da732x_set_charge_pump(codec, DA732X_ENABLE_CP);
snd_soc_write(codec, DA732X_REG_CLK_EN1,
DA732X_SYS3_CLK_EN | DA732X_PC_CLK_EN);
/* Enable Zero Crossing */
snd_soc_write(codec, DA732X_REG_INP_ZC_EN,
DA732X_MIC1_PRE_ZC_EN |
DA732X_MIC1_ZC_EN |
DA732X_MIC2_PRE_ZC_EN |
DA732X_MIC2_ZC_EN |
DA732X_AUXL_ZC_EN |
DA732X_AUXR_ZC_EN |
DA732X_MIC3_PRE_ZC_EN |
DA732X_MIC3_ZC_EN);
snd_soc_write(codec, DA732X_REG_OUT_ZC_EN,
DA732X_HPL_ZC_EN | DA732X_HPR_ZC_EN |
DA732X_LIN2_ZC_EN | DA732X_LIN3_ZC_EN |
DA732X_LIN4_ZC_EN);
da732x_hp_dc_offset_cancellation(codec);
regcache_cache_only(codec->control_data, false);
regcache_sync(codec->control_data);
} else {
snd_soc_update_bits(codec, DA732X_REG_BIAS_EN,
DA732X_BIAS_BOOST_MASK,
DA732X_BIAS_BOOST_50PC);
snd_soc_update_bits(codec, DA732X_REG_PLL_CTRL,
DA732X_PLL_EN, 0);
da732x->pll_en = false;
}
break;
case SND_SOC_BIAS_OFF:
regcache_cache_only(codec->control_data, true);
da732x_set_charge_pump(codec, DA732X_DISABLE_CP);
snd_soc_update_bits(codec, DA732X_REG_BIAS_EN, DA732X_BIAS_EN,
DA732X_BIAS_DIS);
da732x->pll_en = false;
break;
}
codec->dapm.bias_level = level;
return 0;
}
static int da732x_probe(struct snd_soc_codec *codec)
{
struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec);
struct snd_soc_dapm_context *dapm = &codec->dapm;
int ret = 0;
da732x->codec = codec;
dapm->idle_bias_off = false;
codec->control_data = da732x->regmap;
ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec.\n");
goto err;
}
da732x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
err:
return ret;
}
static int da732x_remove(struct snd_soc_codec *codec)
{
da732x_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
struct snd_soc_codec_driver soc_codec_dev_da732x = {
.probe = da732x_probe,
.remove = da732x_remove,
.set_bias_level = da732x_set_bias_level,
.controls = da732x_snd_controls,
.num_controls = ARRAY_SIZE(da732x_snd_controls),
.dapm_widgets = da732x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(da732x_dapm_widgets),
.dapm_routes = da732x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(da732x_dapm_routes),
.set_pll = da732x_set_dai_pll,
.reg_cache_size = ARRAY_SIZE(da732x_reg_cache),
};
static __devinit int da732x_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct da732x_priv *da732x;
unsigned int reg;
int ret;
da732x = devm_kzalloc(&i2c->dev, sizeof(struct da732x_priv),
GFP_KERNEL);
if (!da732x)
return -ENOMEM;
i2c_set_clientdata(i2c, da732x);
da732x->regmap = devm_regmap_init_i2c(i2c, &da732x_regmap);
if (IS_ERR(da732x->regmap)) {
ret = PTR_ERR(da732x->regmap);
dev_err(&i2c->dev, "Failed to initialize regmap\n");
goto err;
}
ret = regmap_read(da732x->regmap, DA732X_REG_ID, &reg);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
goto err;
}
dev_info(&i2c->dev, "Revision: %d.%d\n",
(reg & DA732X_ID_MAJOR_MASK), (reg & DA732X_ID_MINOR_MASK));
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_da732x,
da732x_dai, ARRAY_SIZE(da732x_dai));
if (ret != 0)
dev_err(&i2c->dev, "Failed to register codec.\n");
err:
return ret;
}
static __devexit int da732x_i2c_remove(struct i2c_client *client)
{
snd_soc_unregister_codec(&client->dev);
return 0;
}
static const struct i2c_device_id da732x_i2c_id[] = {
{ "da7320", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, da732x_i2c_id);
static struct i2c_driver da732x_i2c_driver = {
.driver = {
.name = "da7320",
.owner = THIS_MODULE,
},
.probe = da732x_i2c_probe,
.remove = __devexit_p(da732x_i2c_remove),
.id_table = da732x_i2c_id,
};
module_i2c_driver(da732x_i2c_driver);
MODULE_DESCRIPTION("ASoC DA732X driver");
MODULE_AUTHOR("Michal Hajduk <michal.hajduk@diasemi.com>");
MODULE_LICENSE("GPL");
sound/soc/codecs/da732x.h 0 → 100644
View file @ 48e27874
/*
* da732x.h -- Dialog DA732X ALSA SoC Audio Driver Header File
*
* Copyright (C) 2012 Dialog Semiconductor GmbH
*
* Author: Michal Hajduk <Michal.Hajduk@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DA732X_H_
#define __DA732X_H
#include <sound/soc.h>
/* General */
#define DA732X_U8_MASK 0xFF
#define DA732X_4BYTES 4
#define DA732X_3BYTES 3
#define DA732X_2BYTES 2
#define DA732X_1BYTE 1
#define DA732X_1BYTE_SHIFT 8
#define DA732X_2BYTES_SHIFT 16
#define DA732X_3BYTES_SHIFT 24
#define DA732X_4BYTES_SHIFT 32
#define DA732X_DACS_DIS 0x0
#define DA732X_HP_DIS 0x0
#define DA732X_CLEAR_REG 0x0
/* Calibration */
#define DA732X_DAC_OFFSET_STEP 0x20
#define DA732X_OUTPUT_OFFSET_STEP 0x80
#define DA732X_HP_OUT_TRIM_VAL 0x0
#define DA732X_WAIT_FOR_STABILIZATION 1
#define DA732X_HPL_DAC 0
#define DA732X_HPR_DAC 1
#define DA732X_HP_DACS 2
#define DA732X_HPL_AMP 0
#define DA732X_HPR_AMP 1
#define DA732X_HP_AMPS 2
/* Clock settings */
#define DA732X_STARTUP_DELAY 100
#define DA732X_PLL_OUT_196608 196608000
#define DA732X_PLL_OUT_180634 180633600
#define DA732X_PLL_OUT_SRM 188620800
#define DA732X_MCLK_10MHZ 10000000
#define DA732X_MCLK_20MHZ 20000000
#define DA732X_MCLK_40MHZ 40000000
#define DA732X_MCLK_54MHZ 54000000
#define DA732X_MCLK_RET_0_10MHZ 0
#define DA732X_MCLK_VAL_0_10MHZ 1
#define DA732X_MCLK_RET_10_20MHZ 1
#define DA732X_MCLK_VAL_10_20MHZ 2
#define DA732X_MCLK_RET_20_40MHZ 2
#define DA732X_MCLK_VAL_20_40MHZ 4
#define DA732X_MCLK_RET_40_54MHZ 3
#define DA732X_MCLK_VAL_40_54MHZ 8
#define DA732X_DAI_ID1 0
#define DA732X_DAI_ID2 1
#define DA732X_SRCCLK_PLL 0
#define DA732X_SRCCLK_MCLK 1
#define DA732X_LIN_LP_VOL 0x4F
#define DA732X_LP_VOL 0x40
/* Kcontrols */
#define DA732X_DAC_EN_MAX 2
#define DA732X_ADCL_MUX_MAX 2
#define DA732X_ADCR_MUX_MAX 3
#define DA732X_HPF_MODE_MAX 3
#define DA732X_HPF_MODE_SHIFT 4
#define DA732X_HPF_MUSIC_SHIFT 0
#define DA732X_HPF_MUSIC_MAX 4
#define DA732X_HPF_VOICE_SHIFT 4
#define DA732X_HPF_VOICE_MAX 8
#define DA732X_EQ_EN_MAX 1
#define DA732X_HPF_VOICE 1
#define DA732X_HPF_MUSIC 2
#define DA732X_HPF_DISABLED 0
#define DA732X_NO_INVERT 0
#define DA732X_INVERT 1
#define DA732X_SWITCH_MAX 1
#define DA732X_ENABLE_CP 1
#define DA732X_DISABLE_CP 0
#define DA732X_DISABLE_ALL_CLKS 0
#define DA732X_RESET_ADCS 0
/* dB values */
#define DA732X_MIC_VOL_DB_MIN 0
#define DA732X_MIC_VOL_DB_INC 50
#define DA732X_MIC_PRE_VOL_DB_MIN 0
#define DA732X_MIC_PRE_VOL_DB_INC 600
#define DA732X_AUX_VOL_DB_MIN -6000
#define DA732X_AUX_VOL_DB_INC 150
#define DA732X_HP_VOL_DB_MIN -2250
#define DA732X_HP_VOL_DB_INC 150
#define DA732X_LIN2_VOL_DB_MIN -1650
#define DA732X_LIN2_VOL_DB_INC 150
#define DA732X_LIN3_VOL_DB_MIN -1650
#define DA732X_LIN3_VOL_DB_INC 150
#define DA732X_LIN4_VOL_DB_MIN -2250
#define DA732X_LIN4_VOL_DB_INC 150
#define DA732X_EQ_BAND_VOL_DB_MIN -1050
#define DA732X_EQ_BAND_VOL_DB_INC 150
#define DA732X_DAC_VOL_DB_MIN -7725
#define DA732X_DAC_VOL_DB_INC 75
#define DA732X_ADC_VOL_DB_MIN 0
#define DA732X_ADC_VOL_DB_INC -1
#define DA732X_EQ_OVERALL_VOL_DB_MIN -1800
#define DA732X_EQ_OVERALL_VOL_DB_INC 600
#define DA732X_SOC_ENUM_DOUBLE_R(xreg, xrreg, xmax, xtext) \
{.reg = xreg, .reg2 = xrreg, .max = xmax, .texts = xtext}
enum da732x_sysctl {
DA732X_SR_8KHZ = 0x1,
DA732X_SR_11_025KHZ = 0x2,
DA732X_SR_12KHZ = 0x3,
DA732X_SR_16KHZ = 0x5,
DA732X_SR_22_05KHZ = 0x6,
DA732X_SR_24KHZ = 0x7,
DA732X_SR_32KHZ = 0x9,
DA732X_SR_44_1KHZ = 0xA,
DA732X_SR_48KHZ = 0xB,
DA732X_SR_88_1KHZ = 0xE,
DA732X_SR_96KHZ = 0xF,
};
#endif /* __DA732X_H_ */
sound/soc/codecs/da732x_reg.h 0 → 100644
View file @ 48e27874
/*
* da732x_reg.h --- Dialog DA732X ALSA SoC Audio Registers Header File
*
* Copyright (C) 2012 Dialog Semiconductor GmbH
*
* Author: Michal Hajduk <Michal.Hajduk@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DA732X_REG_H_
#define __DA732X_REG_H_
/* DA732X registers */
#define DA732X_REG_STATUS_EXT 0x00
#define DA732X_REG_STATUS 0x01
#define DA732X_REG_REF1 0x02
#define DA732X_REG_BIAS_EN 0x03
#define DA732X_REG_BIAS1 0x04
#define DA732X_REG_BIAS2 0x05
#define DA732X_REG_BIAS3 0x06
#define DA732X_REG_BIAS4 0x07
#define DA732X_REG_MICBIAS2 0x0F
#define DA732X_REG_MICBIAS1 0x10
#define DA732X_REG_MICDET 0x11
#define DA732X_REG_MIC1_PRE 0x12
#define DA732X_REG_MIC1 0x13
#define DA732X_REG_MIC2_PRE 0x14
#define DA732X_REG_MIC2 0x15
#define DA732X_REG_AUX1L 0x16
#define DA732X_REG_AUX1R 0x17
#define DA732X_REG_MIC3_PRE 0x18
#define DA732X_REG_MIC3 0x19
#define DA732X_REG_INP_PINBIAS 0x1A
#define DA732X_REG_INP_ZC_EN 0x1B
#define DA732X_REG_INP_MUX 0x1D
#define DA732X_REG_HP_DET 0x20
#define DA732X_REG_HPL_DAC_OFFSET 0x21
#define DA732X_REG_HPL_DAC_OFF_CNTL 0x22
#define DA732X_REG_HPL_OUT_OFFSET 0x23
#define DA732X_REG_HPL 0x24
#define DA732X_REG_HPL_VOL 0x25
#define DA732X_REG_HPR_DAC_OFFSET 0x26
#define DA732X_REG_HPR_DAC_OFF_CNTL 0x27
#define DA732X_REG_HPR_OUT_OFFSET 0x28
#define DA732X_REG_HPR 0x29
#define DA732X_REG_HPR_VOL 0x2A
#define DA732X_REG_LIN2 0x2B
#define DA732X_REG_LIN3 0x2C
#define DA732X_REG_LIN4 0x2D
#define DA732X_REG_OUT_ZC_EN 0x2E
#define DA732X_REG_HP_LIN1_GNDSEL 0x37
#define DA732X_REG_CP_HP1 0x3A
#define DA732X_REG_CP_HP2 0x3B
#define DA732X_REG_CP_CTRL1 0x40
#define DA732X_REG_CP_CTRL2 0x41
#define DA732X_REG_CP_CTRL3 0x42
#define DA732X_REG_CP_LEVEL_MASK 0x43
#define DA732X_REG_CP_DET 0x44
#define DA732X_REG_CP_STATUS 0x45
#define DA732X_REG_CP_THRESH1 0x46
#define DA732X_REG_CP_THRESH2 0x47
#define DA732X_REG_CP_THRESH3 0x48
#define DA732X_REG_CP_THRESH4 0x49
#define DA732X_REG_CP_THRESH5 0x4A
#define DA732X_REG_CP_THRESH6 0x4B
#define DA732X_REG_CP_THRESH7 0x4C
#define DA732X_REG_CP_THRESH8 0x4D
#define DA732X_REG_PLL_DIV_LO 0x50
#define DA732X_REG_PLL_DIV_MID 0x51
#define DA732X_REG_PLL_DIV_HI 0x52
#define DA732X_REG_PLL_CTRL 0x53
#define DA732X_REG_CLK_CTRL 0x54
#define DA732X_REG_CLK_DSP 0x5A
#define DA732X_REG_CLK_EN1 0x5B
#define DA732X_REG_CLK_EN2 0x5C
#define DA732X_REG_CLK_EN3 0x5D
#define DA732X_REG_CLK_EN4 0x5E
#define DA732X_REG_CLK_EN5 0x5F
#define DA732X_REG_AIF_MCLK 0x60
#define DA732X_REG_AIFA1 0x61
#define DA732X_REG_AIFA2 0x62
#define DA732X_REG_AIFA3 0x63
#define DA732X_REG_AIFB1 0x64
#define DA732X_REG_AIFB2 0x65
#define DA732X_REG_AIFB3 0x66
#define DA732X_REG_PC_CTRL 0x6A
#define DA732X_REG_DATA_ROUTE 0x70
#define DA732X_REG_DSP_CTRL 0x71
#define DA732X_REG_CIF_CTRL2 0x74
#define DA732X_REG_HANDSHAKE 0x75
#define DA732X_REG_MBOX0 0x76
#define DA732X_REG_MBOX1 0x77
#define DA732X_REG_MBOX2 0x78
#define DA732X_REG_MBOX_STATUS 0x79
#define DA732X_REG_SPARE1_OUT 0x7D
#define DA732X_REG_SPARE2_OUT 0x7E
#define DA732X_REG_SPARE1_IN 0x7F
#define DA732X_REG_ID 0x81
#define DA732X_REG_ADC1_PD 0x90
#define DA732X_REG_ADC1_HPF 0x93
#define DA732X_REG_ADC1_SEL 0x94
#define DA732X_REG_ADC1_EQ12 0x95
#define DA732X_REG_ADC1_EQ34 0x96
#define DA732X_REG_ADC1_EQ5 0x97
#define DA732X_REG_ADC2_PD 0x98
#define DA732X_REG_ADC2_HPF 0x9B
#define DA732X_REG_ADC2_SEL 0x9C
#define DA732X_REG_ADC2_EQ12 0x9D
#define DA732X_REG_ADC2_EQ34 0x9E
#define DA732X_REG_ADC2_EQ5 0x9F
#define DA732X_REG_DAC1_HPF 0xA0
#define DA732X_REG_DAC1_L_VOL 0xA1
#define DA732X_REG_DAC1_R_VOL 0xA2
#define DA732X_REG_DAC1_SEL 0xA3
#define DA732X_REG_DAC1_SOFTMUTE 0xA4
#define DA732X_REG_DAC1_EQ12 0xA5
#define DA732X_REG_DAC1_EQ34 0xA6
#define DA732X_REG_DAC1_EQ5 0xA7
#define DA732X_REG_DAC2_HPF 0xB0
#define DA732X_REG_DAC2_L_VOL 0xB1
#define DA732X_REG_DAC2_R_VOL 0xB2
#define DA732X_REG_DAC2_SEL 0xB3
#define DA732X_REG_DAC2_SOFTMUTE 0xB4
#define DA732X_REG_DAC2_EQ12 0xB5
#define DA732X_REG_DAC2_EQ34 0xB6
#define DA732X_REG_DAC2_EQ5 0xB7
#define DA732X_REG_DAC3_HPF 0xC0
#define DA732X_REG_DAC3_VOL 0xC1
#define DA732X_REG_DAC3_SEL 0xC3
#define DA732X_REG_DAC3_SOFTMUTE 0xC4
#define DA732X_REG_DAC3_EQ12 0xC5
#define DA732X_REG_DAC3_EQ34 0xC6
#define DA732X_REG_DAC3_EQ5 0xC7
#define DA732X_REG_BIQ_BYP 0xD2
#define DA732X_REG_DMA_CMD 0xD3
#define DA732X_REG_DMA_ADDR0 0xD4
#define DA732X_REG_DMA_ADDR1 0xD5
#define DA732X_REG_DMA_DATA0 0xD6
#define DA732X_REG_DMA_DATA1 0xD7
#define DA732X_REG_DMA_DATA2 0xD8
#define DA732X_REG_DMA_DATA3 0xD9
#define DA732X_REG_DMA_STATUS 0xDA
#define DA732X_REG_BROWNOUT 0xDF
#define DA732X_REG_UNLOCK 0xE0
#define DA732X_MAX_REG DA732X_REG_UNLOCK
/*
* Bits
*/
/* DA732X_REG_STATUS_EXT (addr=0x00) */
#define DA732X_STATUS_EXT_DSP (1 << 4)
#define DA732X_STATUS_EXT_CLEAR (0 << 0)
/* DA732X_REG_STATUS (addr=0x01) */
#define DA732X_STATUS_PLL_LOCK (1 << 0)
#define DA732X_STATUS_PLL_MCLK_DET (1 << 1)
#define DA732X_STATUS_HPDET_OUT (1 << 2)
#define DA732X_STATUS_INP_MIXDET_1 (1 << 3)
#define DA732X_STATUS_INP_MIXDET_2 (1 << 4)
#define DA732X_STATUS_BO_STATUS (1 << 5)
/* DA732X_REG_REF1 (addr=0x02) */
#define DA732X_VMID_FASTCHG (1 << 1)
#define DA732X_VMID_FASTDISCHG (1 << 2)
#define DA732X_REFBUFX2_EN (1 << 6)
#define DA732X_REFBUFX2_DIS (0 << 6)
/* DA732X_REG_BIAS_EN (addr=0x03) */
#define DA732X_BIAS_BOOST_MASK (3 << 0)
#define DA732X_BIAS_BOOST_100PC (0 << 0)
#define DA732X_BIAS_BOOST_133PC (1 << 0)
#define DA732X_BIAS_BOOST_88PC (2 << 0)
#define DA732X_BIAS_BOOST_50PC (3 << 0)
#define DA732X_BIAS_EN (1 << 7)
#define DA732X_BIAS_DIS (0 << 7)
/* DA732X_REG_BIAS1 (addr=0x04) */
#define DA732X_BIAS1_HP_DAC_BIAS_MASK (3 << 0)
#define DA732X_BIAS1_HP_DAC_BIAS_100PC (0 << 0)
#define DA732X_BIAS1_HP_DAC_BIAS_150PC (1 << 0)
#define DA732X_BIAS1_HP_DAC_BIAS_50PC (2 << 0)
#define DA732X_BIAS1_HP_DAC_BIAS_75PC (3 << 0)
#define DA732X_BIAS1_HP_OUT_BIAS_MASK (7 << 4)
#define DA732X_BIAS1_HP_OUT_BIAS_100PC (0 << 4)
#define DA732X_BIAS1_HP_OUT_BIAS_125PC (1 << 4)
#define DA732X_BIAS1_HP_OUT_BIAS_150PC (2 << 4)
#define DA732X_BIAS1_HP_OUT_BIAS_175PC (3 << 4)
#define DA732X_BIAS1_HP_OUT_BIAS_200PC (4 << 4)
#define DA732X_BIAS1_HP_OUT_BIAS_250PC (5 << 4)
#define DA732X_BIAS1_HP_OUT_BIAS_300PC (6 << 4)
#define DA732X_BIAS1_HP_OUT_BIAS_350PC (7 << 4)
/* DA732X_REG_BIAS2 (addr=0x05) */
#define DA732X_BIAS2_LINE2_DAC_BIAS_MASK (3 << 0)
#define DA732X_BIAS2_LINE2_DAC_BIAS_100PC (0 << 0)
#define DA732X_BIAS2_LINE2_DAC_BIAS_150PC (1 << 0)
#define DA732X_BIAS2_LINE2_DAC_BIAS_50PC (2 << 0)
#define DA732X_BIAS2_LINE2_DAC_BIAS_75PC (3 << 0)
#define DA732X_BIAS2_LINE2_OUT_BIAS_MASK (7 << 4)
#define DA732X_BIAS2_LINE2_OUT_BIAS_100PC (0 << 4)
#define DA732X_BIAS2_LINE2_OUT_BIAS_125PC (1 << 4)
#define DA732X_BIAS2_LINE2_OUT_BIAS_150PC (2 << 4)
#define DA732X_BIAS2_LINE2_OUT_BIAS_175PC (3 << 4)
#define DA732X_BIAS2_LINE2_OUT_BIAS_200PC (4 << 4)
#define DA732X_BIAS2_LINE2_OUT_BIAS_250PC (5 << 4)
#define DA732X_BIAS2_LINE2_OUT_BIAS_300PC (6 << 4)
#define DA732X_BIAS2_LINE2_OUT_BIAS_350PC (7 << 4)
/* DA732X_REG_BIAS3 (addr=0x06) */
#define DA732X_BIAS3_LINE3_DAC_BIAS_MASK (3 << 0)
#define DA732X_BIAS3_LINE3_DAC_BIAS_100PC (0 << 0)
#define DA732X_BIAS3_LINE3_DAC_BIAS_150PC (1 << 0)
#define DA732X_BIAS3_LINE3_DAC_BIAS_50PC (2 << 0)
#define DA732X_BIAS3_LINE3_DAC_BIAS_75PC (3 << 0)
#define DA732X_BIAS3_LINE3_OUT_BIAS_MASK (7 << 4)
#define DA732X_BIAS3_LINE3_OUT_BIAS_100PC (0 << 4)
#define DA732X_BIAS3_LINE3_OUT_BIAS_125PC (1 << 4)
#define DA732X_BIAS3_LINE3_OUT_BIAS_150PC (2 << 4)
#define DA732X_BIAS3_LINE3_OUT_BIAS_175PC (3 << 4)
#define DA732X_BIAS3_LINE3_OUT_BIAS_200PC (4 << 4)
#define DA732X_BIAS3_LINE3_OUT_BIAS_250PC (5 << 4)
#define DA732X_BIAS3_LINE3_OUT_BIAS_300PC (6 << 4)
#define DA732X_BIAS3_LINE3_OUT_BIAS_350PC (7 << 4)
/* DA732X_REG_BIAS4 (addr=0x07) */
#define DA732X_BIAS4_LINE4_DAC_BIAS_MASK (3 << 0)
#define DA732X_BIAS4_LINE4_DAC_BIAS_100PC (0 << 0)
#define DA732X_BIAS4_LINE4_DAC_BIAS_150PC (1 << 0)
#define DA732X_BIAS4_LINE4_DAC_BIAS_50PC (2 << 0)
#define DA732X_BIAS4_LINE4_DAC_BIAS_75PC (3 << 0)
#define DA732X_BIAS4_LINE4_OUT_BIAS_MASK (7 << 4)
#define DA732X_BIAS4_LINE4_OUT_BIAS_100PC (0 << 4)
#define DA732X_BIAS4_LINE4_OUT_BIAS_125PC (1 << 4)
#define DA732X_BIAS4_LINE4_OUT_BIAS_150PC (2 << 4)
#define DA732X_BIAS4_LINE4_OUT_BIAS_175PC (3 << 4)
#define DA732X_BIAS4_LINE4_OUT_BIAS_200PC (4 << 4)
#define DA732X_BIAS4_LINE4_OUT_BIAS_250PC (5 << 4)
#define DA732X_BIAS4_LINE4_OUT_BIAS_300PC (6 << 4)
#define DA732X_BIAS4_LINE4_OUT_BIAS_350PC (7 << 4)
/* DA732X_REG_SIF_VDD_SEL (addr=0x08) */
#define DA732X_SIF_VDD_SEL_AIFA_VDD2 (1 << 0)
#define DA732X_SIF_VDD_SEL_AIFB_VDD2 (1 << 1)
#define DA732X_SIF_VDD_SEL_CIFA_VDD2 (1 << 4)
/* DA732X_REG_MICBIAS2/1 (addr=0x0F/0x10) */
#define DA732X_MICBIAS_VOLTAGE_MASK (0x0F << 0)
#define DA732X_MICBIAS_VOLTAGE_2V (0x00 << 0)
#define DA732X_MICBIAS_VOLTAGE_2V05 (0x01 << 0)
#define DA732X_MICBIAS_VOLTAGE_2V1 (0x02 << 0)
#define DA732X_MICBIAS_VOLTAGE_2V15 (0x03 << 0)
#define DA732X_MICBIAS_VOLTAGE_2V2 (0x04 << 0)
#define DA732X_MICBIAS_VOLTAGE_2V25 (0x05 << 0)
#define DA732X_MICBIAS_VOLTAGE_2V3 (0x06 << 0)
#define DA732X_MICBIAS_VOLTAGE_2V35 (0x07 << 0)
#define DA732X_MICBIAS_VOLTAGE_2V4 (0x08 << 0)
#define DA732X_MICBIAS_VOLTAGE_2V45 (0x09 << 0)
#define DA732X_MICBIAS_VOLTAGE_2V5 (0x0A << 0)
#define DA732X_MICBIAS_EN (1 << 7)
#define DA732X_MICBIAS_EN_SHIFT 7
#define DA732X_MICBIAS_VOLTAGE_SHIFT 0
#define DA732X_MICBIAS_VOLTAGE_MAX 0x0B
/* DA732X_REG_MICDET (addr=0x11) */
#define DA732X_MICDET_INP_MICRES (1 << 0)
#define DA732X_MICDET_INP_MICHOOK (1 << 1)
#define DA732X_MICDET_INP_DEBOUNCE_PRD_8MS (0 << 0)
#define DA732X_MICDET_INP_DEBOUNCE_PRD_16MS (1 << 0)
#define DA732X_MICDET_INP_DEBOUNCE_PRD_32MS (2 << 0)
#define DA732X_MICDET_INP_DEBOUNCE_PRD_64MS (3 << 0)
#define DA732X_MICDET_INP_MICDET_EN (1 << 7)
/* DA732X_REG_MIC1/2/3_PRE (addr=0x11/0x14/0x18) */
#define DA732X_MICBOOST_MASK 0x7
#define DA732X_MICBOOST_SHIFT 0
#define DA732X_MICBOOST_MIN 0x1
#define DA732X_MICBOOST_MAX DA732X_MICBOOST_MASK
/* DA732X_REG_MIC1/2/3 (addr=0x13/0x15/0x19) */
#define DA732X_MIC_VOL_SHIFT 0
#define DA732X_MIC_VOL_VAL_MASK 0x1F
#define DA732X_MIC_MUTE_SHIFT 6
#define DA732X_MIC_EN_SHIFT 7
#define DA732X_MIC_VOL_VAL_MIN 0x7
#define DA732X_MIC_VOL_VAL_MAX DA732X_MIC_VOL_VAL_MASK
/* DA732X_REG_AUX1L/R (addr=0x16/0x17) */
#define DA732X_AUX_VOL_SHIFT 0
#define DA732X_AUX_VOL_MASK 0x7
#define DA732X_AUX_MUTE_SHIFT 6
#define DA732X_AUX_EN_SHIFT 7
#define DA732X_AUX_VOL_VAL_MAX DA732X_AUX_VOL_MASK
/* DA732X_REG_INP_PINBIAS (addr=0x1A) */
#define DA732X_INP_MICL_PINBIAS_EN (1 << 0)
#define DA732X_INP_MICR_PINBIAS_EN (1 << 1)
#define DA732X_INP_AUX1L_PINBIAS_EN (1 << 2)
#define DA732X_INP_AUX1R_PINBIAS_EN (1 << 3)
#define DA732X_INP_AUX2_PINBIAS_EN (1 << 4)
/* DA732X_REG_INP_ZC_EN (addr=0x1B) */
#define DA732X_MIC1_PRE_ZC_EN (1 << 0)
#define DA732X_MIC1_ZC_EN (1 << 1)
#define DA732X_MIC2_PRE_ZC_EN (1 << 2)
#define DA732X_MIC2_ZC_EN (1 << 3)
#define DA732X_AUXL_ZC_EN (1 << 4)
#define DA732X_AUXR_ZC_EN (1 << 5)
#define DA732X_MIC3_PRE_ZC_EN (1 << 6)
#define DA732X_MIC3_ZC_EN (1 << 7)
/* DA732X_REG_INP_MUX (addr=0x1D) */
#define DA732X_INP_ADC1L_MUX_SEL_AUX1L (0 << 0)
#define DA732X_INP_ADC1L_MUX_SEL_MIC1 (1 << 0)
#define DA732X_INP_ADC1R_MUX_SEL_MASK (3 << 2)
#define DA732X_INP_ADC1R_MUX_SEL_AUX1R (0 << 2)
#define DA732X_INP_ADC1R_MUX_SEL_MIC2 (1 << 2)
#define DA732X_INP_ADC1R_MUX_SEL_MIC3 (2 << 2)
#define DA732X_INP_ADC2L_MUX_SEL_AUX1L (0 << 4)
#define DA732X_INP_ADC2L_MUX_SEL_MICL (1 << 4)
#define DA732X_INP_ADC2R_MUX_SEL_MASK (3 << 6)
#define DA732X_INP_ADC2R_MUX_SEL_AUX1R (0 << 6)
#define DA732X_INP_ADC2R_MUX_SEL_MICR (1 << 6)
#define DA732X_INP_ADC2R_MUX_SEL_AUX2 (2 << 6)
#define DA732X_ADC1L_MUX_SEL_SHIFT 0
#define DA732X_ADC1R_MUX_SEL_SHIFT 2
#define DA732X_ADC2L_MUX_SEL_SHIFT 4
#define DA732X_ADC2R_MUX_SEL_SHIFT 6
/* DA732X_REG_HP_DET (addr=0x20) */
#define DA732X_HP_DET_AZ (1 << 0)
#define DA732X_HP_DET_SEL1 (1 << 1)
#define DA732X_HP_DET_IS_MASK (3 << 2)
#define DA732X_HP_DET_IS_0_5UA (0 << 2)
#define DA732X_HP_DET_IS_1UA (1 << 2)
#define DA732X_HP_DET_IS_2UA (2 << 2)
#define DA732X_HP_DET_IS_4UA (3 << 2)
#define DA732X_HP_DET_RS_MASK (3 << 4)
#define DA732X_HP_DET_RS_INFINITE (0 << 4)
#define DA732X_HP_DET_RS_100KOHM (1 << 4)
#define DA732X_HP_DET_RS_10KOHM (2 << 4)
#define DA732X_HP_DET_RS_1KOHM (3 << 4)
#define DA732X_HP_DET_EN (1 << 7)
/* DA732X_REG_HPL_DAC_OFFSET (addr=0x21/0x26) */
#define DA732X_HP_DAC_OFFSET_TRIM_MASK (0x3F << 0)
#define DA732X_HP_DAC_OFFSET_DAC_SIGN (1 << 6)
/* DA732X_REG_HPL_DAC_OFF_CNTL (addr=0x22/0x27) */
#define DA732X_HP_DAC_OFF_CNTL_CONT_MASK (7 << 0)
#define DA732X_HP_DAC_OFF_CNTL_COMPO (1 << 3)
#define DA732X_HP_DAC_OFF_CALIBRATION (1 << 0)
#define DA732X_HP_DAC_OFF_SCALE_STEPS (1 << 1)
#define DA732X_HP_DAC_OFF_MASK 0x7F
#define DA732X_HP_DAC_COMPO_SHIFT 3
/* DA732X_REG_HPL_OUT_OFFSET (addr=0x23/0x28) */
#define DA732X_HP_OUT_OFFSET_MASK (0xFF << 0)
#define DA732X_HP_DAC_OFFSET_TRIM_VAL 0x7F
/* DA732X_REG_HPL/R (addr=0x24/0x29) */
#define DA732X_HP_OUT_SIGN (1 << 0)
#define DA732X_HP_OUT_COMP (1 << 1)
#define DA732X_HP_OUT_RESERVED (1 << 2)
#define DA732X_HP_OUT_COMPO (1 << 3)
#define DA732X_HP_OUT_DAC_EN (1 << 4)
#define DA732X_HP_OUT_HIZ_EN (1 << 5)
#define DA732X_HP_OUT_HIZ_DIS (0 << 5)
#define DA732X_HP_OUT_MUTE (1 << 6)
#define DA732X_HP_OUT_EN (1 << 7)
#define DA732X_HP_OUT_COMPO_SHIFT 3
#define DA732X_HP_OUT_DAC_EN_SHIFT 4
#define DA732X_HP_HIZ_SHIFT 5
#define DA732X_HP_MUTE_SHIFT 6
#define DA732X_HP_OUT_EN_SHIFT 7
#define DA732X_OUT_HIZ_EN (1 << 5)
#define DA732X_OUT_HIZ_DIS (0 << 5)
/* DA732X_REG_HPL/R_VOL (addr=0x25/0x2A) */
#define DA732X_HP_VOL_VAL_MASK 0xF
#define DA732X_HP_VOL_SHIFT 0
#define DA732X_HP_VOL_VAL_MAX DA732X_HP_VOL_VAL_MASK
/* DA732X_REG_LIN2/3/4 (addr=0x2B/0x2C/0x2D) */
#define DA732X_LOUT_VOL_SHIFT 0
#define DA732X_LOUT_VOL_MASK 0x0F
#define DA732X_LOUT_DAC_OFF (0 << 4)
#define DA732X_LOUT_DAC_EN (1 << 4)
#define DA732X_LOUT_HIZ_N_DIS (0 << 5)
#define DA732X_LOUT_HIZ_N_EN (1 << 5)
#define DA732X_LOUT_UNMUTED (0 << 6)
#define DA732X_LOUT_MUTED (1 << 6)
#define DA732X_LOUT_EN (0 << 7)
#define DA732X_LOUT_DIS (1 << 7)
#define DA732X_LOUT_DAC_EN_SHIFT 4
#define DA732X_LOUT_MUTE_SHIFT 6
#define DA732X_LIN_OUT_EN_SHIFT 7
#define DA732X_LOUT_VOL_VAL_MAX DA732X_LOUT_VOL_MASK
/* DA732X_REG_OUT_ZC_EN (addr=0x2E) */
#define DA732X_HPL_ZC_EN_SHIFT 0
#define DA732X_HPR_ZC_EN_SHIFT 1
#define DA732X_HPL_ZC_EN (1 << 0)
#define DA732X_HPL_ZC_DIS (0 << 0)
#define DA732X_HPR_ZC_EN (1 << 1)
#define DA732X_HPR_ZC_DIS (0 << 1)
#define DA732X_LIN2_ZC_EN (1 << 2)
#define DA732X_LIN2_ZC_DIS (0 << 2)
#define DA732X_LIN3_ZC_EN (1 << 3)
#define DA732X_LIN3_ZC_DIS (0 << 3)
#define DA732X_LIN4_ZC_EN (1 << 4)
#define DA732X_LIN4_ZC_DIS (0 << 4)
/* DA732X_REG_HP_LIN1_GNDSEL (addr=0x37) */
#define DA732X_HP_OUT_GNDSEL (1 << 0)
/* DA732X_REG_CP_HP2 (addr=0x3a) */
#define DA732X_HP_CP_PULSESKIP (1 << 0)
#define DA732X_HP_CP_REG (1 << 1)
#define DA732X_HP_CP_EN (1 << 3)
#define DA732X_HP_CP_DIS (0 << 3)
/* DA732X_REG_CP_CTRL1 (addr=0x40) */
#define DA732X_CP_MODE_MASK (7 << 1)
#define DA732X_CP_CTRL_STANDBY (0 << 1)
#define DA732X_CP_CTRL_CPVDD6 (2 << 1)
#define DA732X_CP_CTRL_CPVDD5 (3 << 1)
#define DA732X_CP_CTRL_CPVDD4 (4 << 1)
#define DA732X_CP_CTRL_CPVDD3 (5 << 1)
#define DA732X_CP_CTRL_CPVDD2 (6 << 1)
#define DA732X_CP_CTRL_CPVDD1 (7 << 1)
#define DA723X_CP_DIS (0 << 7)
#define DA732X_CP_EN (1 << 7)
/* DA732X_REG_CP_CTRL2 (addr=0x41) */
#define DA732X_CP_BOOST (1 << 0)
#define DA732X_CP_MANAGE_MAGNITUDE (2 << 2)
/* DA732X_REG_CP_CTRL3 (addr=0x42) */
#define DA732X_CP_1MHZ (0 << 0)
#define DA732X_CP_500KHZ (1 << 0)
#define DA732X_CP_250KHZ (2 << 0)
#define DA732X_CP_125KHZ (3 << 0)
#define DA732X_CP_63KHZ (4 << 0)
#define DA732X_CP_0KHZ (5 << 0)
/* DA732X_REG_PLL_CTRL (addr=0x53) */
#define DA732X_PLL_INDIV_MASK (3 << 0)
#define DA732X_PLL_SRM_EN (1 << 2)
#define DA732X_PLL_EN (1 << 7)
#define DA732X_PLL_BYPASS (0 << 0)
/* DA732X_REG_CLK_CTRL (addr=0x54) */
#define DA732X_SR1_MASK (0xF)
#define DA732X_SR2_MASK (0xF0)
/* DA732X_REG_CLK_DSP (addr=0x5A) */
#define DA732X_DSP_FREQ_MASK (7 << 0)
#define DA732X_DSP_FREQ_12MHZ (0 << 0)
#define DA732X_DSP_FREQ_24MHZ (1 << 0)
#define DA732X_DSP_FREQ_36MHZ (2 << 0)
#define DA732X_DSP_FREQ_48MHZ (3 << 0)
#define DA732X_DSP_FREQ_60MHZ (4 << 0)
#define DA732X_DSP_FREQ_72MHZ (5 << 0)
#define DA732X_DSP_FREQ_84MHZ (6 << 0)
#define DA732X_DSP_FREQ_96MHZ (7 << 0)
/* DA732X_REG_CLK_EN1 (addr=0x5B) */
#define DA732X_DSP_CLK_EN (1 << 0)
#define DA732X_SYS3_CLK_EN (1 << 1)
#define DA732X_DSP12_CLK_EN (1 << 2)
#define DA732X_PC_CLK_EN (1 << 3)
#define DA732X_MCLK_SQR_EN (1 << 7)
/* DA732X_REG_CLK_EN2 (addr=0x5C) */
#define DA732X_UART_CLK_EN (1 << 1)
#define DA732X_CP_CLK_EN (1 << 2)
#define DA732X_CP_CLK_DIS (0 << 2)
/* DA732X_REG_CLK_EN3 (addr=0x5D) */
#define DA732X_ADCA_BB_CLK_EN (1 << 0)
#define DA732X_ADCC_BB_CLK_EN (1 << 4)
/* DA732X_REG_CLK_EN4 (addr=0x5E) */
#define DA732X_DACA_BB_CLK_EN (1 << 0)
#define DA732X_DACC_BB_CLK_EN (1 << 4)
#define DA732X_DACA_BB_CLK_SHIFT 0
#define DA732X_DACC_BB_CLK_SHIFT 4
/* DA732X_REG_CLK_EN5 (addr=0x5F) */
#define DA732X_DACE_BB_CLK_EN (1 << 0)
#define DA732X_DACE_BB_CLK_SHIFT 0
/* DA732X_REG_AIF_MCLK (addr=0x60) */
#define DA732X_AIFM_FRAME_64 (1 << 2)
#define DA732X_AIFM_SRC_SEL_AIFA (1 << 6)
#define DA732X_CLK_GENERATION_AIF_A (1 << 4)
#define DA732X_NO_CLK_GENERATION 0x0
/* DA732X_REG_AIFA1 (addr=0x61) */
#define DA732X_AIF_WORD_MASK (0x3 << 0)
#define DA732X_AIF_WORD_16 (0 << 0)
#define DA732X_AIF_WORD_20 (1 << 0)
#define DA732X_AIF_WORD_24 (2 << 0)
#define DA732X_AIF_WORD_32 (3 << 0)
#define DA732X_AIF_TDM_MONO_SHIFT (1 << 6)
#define DA732X_AIF1_CLK_MASK (1 << 7)
#define DA732X_AIF_SLAVE (0 << 7)
#define DA732X_AIF_CLK_FROM_SRC (1 << 7)
/* DA732X_REG_AIFA3 (addr=0x63) */
#define DA732X_AIF_MODE_SHIFT 0
#define DA732X_AIF_MODE_MASK 0x3
#define DA732X_AIF_I2S_MODE (0 << 0)
#define DA732X_AIF_LEFT_J_MODE (1 << 0)
#define DA732X_AIF_RIGHT_J_MODE (2 << 0)
#define DA732X_AIF_DSP_MODE (3 << 0)
#define DA732X_AIF_WCLK_INV (1 << 4)
#define DA732X_AIF_BCLK_INV (1 << 5)
#define DA732X_AIF_EN (1 << 7)
#define DA732X_AIF_EN_SHIFT 7
/* DA732X_REG_PC_CTRL (addr=0x6a) */
#define DA732X_PC_PULSE_AIFA (0 << 0)
#define DA732X_PC_PULSE_AIFB (1 << 0)
#define DA732X_PC_RESYNC_AUT (1 << 6)
#define DA732X_PC_RESYNC_NOT_AUT (0 << 6)
#define DA732X_PC_SAME (1 << 7)
/* DA732X_REG_DATA_ROUTE (addr=0x70) */
#define DA732X_ADC1_TO_AIFA (0 << 0)
#define DA732X_DSP_TO_AIFA (1 << 0)
#define DA732X_ADC2_TO_AIFB (0 << 1)
#define DA732X_DSP_TO_AIFB (1 << 1)
#define DA732X_AIFA_TO_DAC1L (0 << 2)
#define DA732X_DSP_TO_DAC1L (1 << 2)
#define DA732X_AIFA_TO_DAC1R (0 << 3)
#define DA732X_DSP_TO_DAC1R (1 << 3)
#define DA732X_AIFB_TO_DAC2L (0 << 4)
#define DA732X_DSP_TO_DAC2L (1 << 4)
#define DA732X_AIFB_TO_DAC2R (0 << 5)
#define DA732X_DSP_TO_DAC2R (1 << 5)
#define DA732X_AIFB_TO_DAC3 (0 << 6)
#define DA732X_DSP_TO_DAC3 (1 << 6)
#define DA732X_BYPASS_DSP (0 << 0)
#define DA732X_ALL_TO_DSP (0x7F << 0)
/* DA732X_REG_DSP_CTRL (addr=0x71) */
#define DA732X_DIGITAL_EN (1 << 0)
#define DA732X_DIGITAL_RESET (0 << 0)
#define DA732X_DSP_CORE_EN (1 << 1)
#define DA732X_DSP_CORE_RESET (0 << 1)
/* DA732X_REG_SPARE1_OUT (addr=0x7D)*/
#define DA732X_HP_DRIVER_EN (1 << 0)
#define DA732X_HP_GATE_LOW (1 << 2)
#define DA732X_HP_LOOP_GAIN_CTRL (1 << 3)
/* DA732X_REG_ID (addr=0x81)*/
#define DA732X_ID_MINOR_MASK (0xF << 0)
#define DA732X_ID_MAJOR_MASK (0xF << 4)
/* DA732X_REG_ADC1/2_PD (addr=0x90/0x98) */
#define DA732X_ADC_RST_MASK (0x3 << 0)
#define DA732X_ADC_PD_MASK (0x3 << 2)
#define DA732X_ADC_SET_ACT (0x3 << 0)
#define DA732X_ADC_SET_RST (0x0 << 0)
#define DA732X_ADC_ON (0x3 << 2)
#define DA732X_ADC_OFF (0x0 << 2)
/* DA732X_REG_ADC1/2_SEL (addr=0x94/0x9C) */
#define DA732X_ADC_VOL_VAL_MASK 0x7
#define DA732X_ADCL_VOL_SHIFT 0
#define DA732X_ADCR_VOL_SHIFT 4
#define DA732X_ADCL_EN_SHIFT 2
#define DA732X_ADCR_EN_SHIFT 3
#define DA732X_ADCL_EN (1 << 2)
#define DA732X_ADCR_EN (1 << 3)
#define DA732X_ADC_VOL_VAL_MAX DA732X_ADC_VOL_VAL_MASK
/*
* DA732X_REG_ADC1/2_HPF (addr=0x93/0x9b)
* DA732x_REG_DAC1/2/3_HPG (addr=0xA5/0xB5/0xC5)
*/
#define DA732X_HPF_MUSIC_EN (1 << 3)
#define DA732X_HPF_VOICE_EN ((1 << 3) | (1 << 7))
#define DA732X_HPF_MASK ((1 << 3) | (1 << 7))
#define DA732X_HPF_DIS ((0 << 3) | (0 << 7))
/* DA732X_REG_DAC1/2/3_VOL */
#define DA732X_DAC_VOL_VAL_MASK 0x7F
#define DA732X_DAC_VOL_SHIFT 0
#define DA732X_DAC_VOL_VAL_MAX DA732X_DAC_VOL_VAL_MASK
/* DA732X_REG_DAC1/2/3_SEL (addr=0xA3/0xB3/0xC3) */
#define DA732X_DACL_EN_SHIFT 3
#define DA732X_DACR_EN_SHIFT 7
#define DA732X_DACL_MUTE_SHIFT 2
#define DA732X_DACR_MUTE_SHIFT 6
#define DA732X_DACL_EN (1 << 3)
#define DA732X_DACR_EN (1 << 7)
#define DA732X_DACL_SDM (1 << 0)
#define DA732X_DACR_SDM (1 << 4)
#define DA732X_DACL_MUTE (1 << 2)
#define DA732X_DACR_MUTE (1 << 6)
/* DA732X_REG_DAC_SOFTMUTE (addr=0xA4/0xB4/0xC4) */
#define DA732X_SOFTMUTE_EN (1 << 7)
#define DA732X_GAIN_RAMPED (1 << 6)
#define DA732X_16_SAMPLES (4 << 0)
#define DA732X_SOFTMUTE_MASK (1 << 7)
#define DA732X_SOFTMUTE_SHIFT 7
/*
* DA732x_REG_ADC1/2_EQ12 (addr=0x95/0x9D)
* DA732x_REG_ADC1/2_EQ34 (addr=0x96/0x9E)
* DA732x_REG_ADC1/2_EQ5 (addr=0x97/0x9F)
* DA732x_REG_DAC1/2/3_EQ12 (addr=0xA5/0xB5/0xC5)
* DA732x_REG_DAC1/2/3_EQ34 (addr=0xA6/0xB6/0xC6)
* DA732x_REG_DAC1/2/3_EQ5 (addr=0xA7/0xB7/0xB7)
*/
#define DA732X_EQ_VOL_VAL_MASK 0xF
#define DA732X_EQ_BAND1_SHIFT 0
#define DA732X_EQ_BAND2_SHIFT 4
#define DA732X_EQ_BAND3_SHIFT 0
#define DA732X_EQ_BAND4_SHIFT 4
#define DA732X_EQ_BAND5_SHIFT 0
#define DA732X_EQ_OVERALL_SHIFT 4
#define DA732X_EQ_OVERALL_VOL_VAL_MASK 0x3
#define DA732X_EQ_DIS (0 << 7)
#define DA732X_EQ_EN (1 << 7)
#define DA732X_EQ_EN_SHIFT 7
#define DA732X_EQ_VOL_VAL_MAX DA732X_EQ_VOL_VAL_MASK
#define DA732X_EQ_OVERALL_VOL_VAL_MAX DA732X_EQ_OVERALL_VOL_VAL_MASK
/* DA732X_REG_DMA_CMD (addr=0xD3) */
#define DA732X_SEL_DSP_DMA_MASK (3 << 0)
#define DA732X_SEL_DSP_DMA_DIS (0 << 0)
#define DA732X_SEL_DSP_DMA_PMEM (1 << 0)
#define DA732X_SEL_DSP_DMA_XMEM (2 << 0)
#define DA732X_SEL_DSP_DMA_YMEM (3 << 0)
#define DA732X_DSP_RW_MASK (1 << 4)
#define DA732X_DSP_DMA_WRITE (0 << 4)
#define DA732X_DSP_DMA_READ (1 << 4)
/* DA732X_REG_DMA_STATUS (addr=0xDA) */
#define DA732X_DSP_DMA_FREE (0 << 0)
#define DA732X_DSP_DMA_BUSY (1 << 0)
#endif /* __DA732X_REG_H_ */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7