Commit 48f92845 authored by David Howells's avatar David Howells Committed by Linus Torvalds

[PATCH] frv: accidental TLB entry write-protect fix

The attached patch stops the FRV kernel-instruction-TLB-miss handler from
setting the write-protect bit on a mapping entry when punting an entry from
the mapping fast cache registers (DAMR1/IAMR1) to the TLB.

This patch derives the WP value from the DAMPR1 register (which actually has
a WP bit) rather than the IAMPR1 register (which does not).
Signed-Off-By: default avatarDavid Howells <dhowells@redhat.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent bbf154cc
...@@ -184,8 +184,8 @@ __itlb_k_PTD_mapped: ...@@ -184,8 +184,8 @@ __itlb_k_PTD_mapped:
movgs gr31,tplr /* set TPLR.CXN */ movgs gr31,tplr /* set TPLR.CXN */
tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */ tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
movsg iampr1,gr31 movsg dampr1,gr31
ori gr31,#xAMPRx_V|DAMPRx_WP,gr31 /* entry was invalidated by tlbpr #4 */ ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
movgs gr31,tppr movgs gr31,tppr
movsg iamlr1,gr31 /* set TPLR.CXN */ movsg iamlr1,gr31 /* set TPLR.CXN */
movgs gr31,tplr movgs gr31,tplr
......
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