Commit 490ddccb authored by Saaem Rizvi's avatar Saaem Rizvi Committed by Alex Deucher

drm/amd/display: Wrong index type for pipe iterator

[Why and How]
Type mismatch in index and pipe count might cause an infinite loop. code
Change should resolve this issue.
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarSaaem Rizvi <syedsaaem.rizvi@amd.com>
Reviewed-by: default avatarJosip Pavic <Josip.Pavic@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0baae624
...@@ -392,7 +392,7 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) ...@@ -392,7 +392,7 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context) void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
{ {
uint8_t i; unsigned int i;
struct pipe_ctx *pipe = NULL; struct pipe_ctx *pipe = NULL;
bool otg_disabled[MAX_PIPES] = {false}; bool otg_disabled[MAX_PIPES] = {false};
......
...@@ -1201,7 +1201,7 @@ void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) ...@@ -1201,7 +1201,7 @@ void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context) void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
{ {
uint8_t i; unsigned int i;
struct pipe_ctx *pipe = NULL; struct pipe_ctx *pipe = NULL;
bool otg_disabled[MAX_PIPES] = {false}; bool otg_disabled[MAX_PIPES] = {false};
......
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