Commit 490f50c1 authored by Neil Armstrong's avatar Neil Armstrong

drm/meson: Add G12A support for OSD1 Plane

Amlogic G12A SoC supports now up to 3 OSD planes (1 more than the
previous SoCs) and a brand new OSD plane blender module.

This patch uses the same OSD1 plane for G12A, using the exact same scaler
and OSD1 setup registers, except using the new blender register to
disable the plane.
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
[narmstrong: fixed typo in commit log]
Tested-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-6-narmstrong@baylibre.com
parent 72888394
...@@ -294,6 +294,13 @@ static void meson_plane_atomic_update(struct drm_plane *plane, ...@@ -294,6 +294,13 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1; priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1; priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1;
priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1;
priv->viu.osb_blend0_size = dst_h << 16 | dst_w;
priv->viu.osb_blend1_size = dst_h << 16 | dst_w;
}
/* Update Canvas with buffer address */ /* Update Canvas with buffer address */
gem = drm_fb_cma_get_gem_obj(fb, 0); gem = drm_fb_cma_get_gem_obj(fb, 0);
...@@ -320,8 +327,12 @@ static void meson_plane_atomic_disable(struct drm_plane *plane, ...@@ -320,8 +327,12 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,
struct meson_drm *priv = meson_plane->priv; struct meson_drm *priv = meson_plane->priv;
/* Disable OSD1 */ /* Disable OSD1 */
writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0, if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
priv->io_base + _REG(VPP_MISC)); writel_bits_relaxed(BIT(0) | BIT(21), 0,
priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
else
writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
priv->io_base + _REG(VPP_MISC));
meson_plane->enabled = false; meson_plane->enabled = false;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment