Commit 4a33bea0 authored by Anurag Kumar Vulisha's avatar Anurag Kumar Vulisha Committed by Vinod Koul

phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver

Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the
high speed peripherals such as USB, SATA, PCIE, Display Port and
Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This
patch adds driver for that ZynqMP GT core.
Signed-off-by: default avatarAnurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.comSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent cea0f76a
...@@ -18852,6 +18852,15 @@ F: Documentation/devicetree/bindings/media/xilinx/ ...@@ -18852,6 +18852,15 @@ F: Documentation/devicetree/bindings/media/xilinx/
F: drivers/media/platform/xilinx/ F: drivers/media/platform/xilinx/
F: include/uapi/linux/xilinx-v4l2-controls.h F: include/uapi/linux/xilinx-v4l2-controls.h
XILINX ZYNQMP PSGTR PHY DRIVER
M: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
L: linux-kernel@vger.kernel.org
S: Supported
T: git https://github.com/Xilinx/linux-xlnx.git
F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
F: drivers/phy/xilinx/phy-zynqmp.c
XILLYBUS DRIVER XILLYBUS DRIVER
M: Eli Billauer <eli.billauer@gmail.com> M: Eli Billauer <eli.billauer@gmail.com>
L: linux-kernel@vger.kernel.org L: linux-kernel@vger.kernel.org
......
...@@ -70,5 +70,6 @@ source "drivers/phy/st/Kconfig" ...@@ -70,5 +70,6 @@ source "drivers/phy/st/Kconfig"
source "drivers/phy/tegra/Kconfig" source "drivers/phy/tegra/Kconfig"
source "drivers/phy/ti/Kconfig" source "drivers/phy/ti/Kconfig"
source "drivers/phy/intel/Kconfig" source "drivers/phy/intel/Kconfig"
source "drivers/phy/xilinx/Kconfig"
endmenu endmenu
...@@ -28,4 +28,5 @@ obj-y += allwinner/ \ ...@@ -28,4 +28,5 @@ obj-y += allwinner/ \
socionext/ \ socionext/ \
st/ \ st/ \
tegra/ \ tegra/ \
ti/ ti/ \
xilinx/
# SPDX-License-Identifier: GPL-2.0-only
#
# PHY drivers for Xilinx platforms
#
config PHY_XILINX_ZYNQMP
tristate "Xilinx ZynqMP PHY driver"
depends on ARCH_ZYNQMP || COMPILE_TEST
select GENERIC_PHY
help
Enable this to support ZynqMP High Speed Gigabit Transceiver
that is part of ZynqMP SoC.
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
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