Commit 4a3da990 authored by Piotr Haber's avatar Piotr Haber Committed by John W. Linville

brcmfmac: support save&restore firmware feature

Save & restore is an advanced power saving feature,
supported only on selected devices.
SR operation is almost completely transparent to the driver.
Support for it is hardware and firmware dependent.
Reviewed-by: default avatarHante Meuleman <meuleman@broadcom.com>
Reviewed-by: default avatarArend van Spriel <arend@broadcom.com>
Reviewed-by: default avatarPieter-Paul Giesberts <pieterpg@broadcom.com>
Reviewed-by: default avatarFranky (Zhenhui) Lin <frankyl@broadcom.com>
Signed-off-by: default avatarPiotr Haber <phaber@broadcom.com>
Signed-off-by: default avatarArend van Spriel <arend@broadcom.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent fe29f54c
...@@ -48,7 +48,11 @@ ...@@ -48,7 +48,11 @@
#define SBSDIO_NUM_FUNCTION 3 #define SBSDIO_NUM_FUNCTION 3
/* function 0 vendor specific CCCR registers */ /* function 0 vendor specific CCCR registers */
#define SDIO_CCCR_BRCM_SEPINT 0xf2 #define SDIO_CCCR_BRCM_CARDCAP 0xf0
#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08
#define SDIO_CCCR_BRCM_SEPINT 0xf2
#define SDIO_SEPINT_MASK 0x01 #define SDIO_SEPINT_MASK 0x01
#define SDIO_SEPINT_OE 0x02 #define SDIO_SEPINT_OE 0x02
...@@ -97,9 +101,23 @@ ...@@ -97,9 +101,23 @@
#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B #define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
/* Read Frame Byte Count High */ /* Read Frame Byte Count High */
#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C #define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
/* MesBusyCtl (rev 11) */
#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
/* Sdio Core Rev 12 */
#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
#define SBSDIO_FUNC1_SLEEPCSR 0x1001F
#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */ #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
/* function 1 OCP space */ /* function 1 OCP space */
......
...@@ -205,7 +205,7 @@ struct chipcregs { ...@@ -205,7 +205,7 @@ struct chipcregs {
u32 res_req_timer_sel; u32 res_req_timer_sel;
u32 res_req_timer; u32 res_req_timer;
u32 res_req_mask; u32 res_req_mask;
u32 PAD; u32 pmucapabilities_ext; /* 0x64c, pmurev >=15 */
u32 chipcontrol_addr; /* 0x650 */ u32 chipcontrol_addr; /* 0x650 */
u32 chipcontrol_data; /* 0x654 */ u32 chipcontrol_data; /* 0x654 */
u32 regcontrol_addr; u32 regcontrol_addr;
...@@ -214,7 +214,11 @@ struct chipcregs { ...@@ -214,7 +214,11 @@ struct chipcregs {
u32 pllcontrol_data; u32 pllcontrol_data;
u32 pmustrapopt; /* 0x668, corerev >= 28 */ u32 pmustrapopt; /* 0x668, corerev >= 28 */
u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
u32 PAD[100]; u32 retention_ctl; /* 0x670, pmurev >= 15 */
u32 PAD[3];
u32 retention_grpidx; /* 0x680 */
u32 retention_grpctl; /* 0x684 */
u32 PAD[94];
u16 sromotp[768]; u16 sromotp[768];
}; };
...@@ -276,6 +280,12 @@ struct chipcregs { ...@@ -276,6 +280,12 @@ struct chipcregs {
#define PCAP5_VC_SHIFT 22 #define PCAP5_VC_SHIFT 22
#define PCAP5_CC_MASK 0xf8000000 #define PCAP5_CC_MASK 0xf8000000
#define PCAP5_CC_SHIFT 27 #define PCAP5_CC_SHIFT 27
/* pmucapabilites_ext PMU rev >= 15 */
#define PCAPEXT_SR_SUPPORTED_MASK (1 << 1)
/* retention_ctl PMU rev >= 15 */
#define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26)
#define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27)
/* /*
* Maximum delay for the PMU state transition in us. * Maximum delay for the PMU state transition in us.
......
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