Commit 4aa3bb0c authored by Ian Minett's avatar Ian Minett Committed by Takashi Iwai

ALSA: hda - Add DSP firmware enums and defs to CA0132 codec

Signed-off-by: default avatarIan Minett <ian_minett@creativelabs.com>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent bcd109c0
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/mutex.h> #include <linux/mutex.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/firmware.h>
#include <sound/core.h> #include <sound/core.h>
#include "hda_codec.h" #include "hda_codec.h"
#include "hda_local.h" #include "hda_local.h"
...@@ -34,12 +35,33 @@ ...@@ -34,12 +35,33 @@
#include "ca0132_regs.h" #include "ca0132_regs.h"
#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
#define MASTERCONTROL 0x80
#define MASTERCONTROL_ALLOC_DMA_CHAN 9
#define WIDGET_CHIP_CTRL 0x15 #define WIDGET_CHIP_CTRL 0x15
#define WIDGET_DSP_CTRL 0x16 #define WIDGET_DSP_CTRL 0x16
#define WUH_MEM_CONNID 10 #define WUH_MEM_CONNID 10
#define DSP_MEM_CONNID 16 #define DSP_MEM_CONNID 16
#define MEM_CONNID_MICIN1 3
#define MEM_CONNID_MICIN2 5
#define MEM_CONNID_MICOUT1 12
#define MEM_CONNID_MICOUT2 14
#define MEM_CONNID_WUH 10
#define MEM_CONNID_DSP 16
#define MEM_CONNID_DMIC 100
#define SCP_SET 0
#define SCP_GET 1
enum hda_cmd_vendor_io { enum hda_cmd_vendor_io {
/* for DspIO node */ /* for DspIO node */
VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
...@@ -64,7 +86,11 @@ enum hda_cmd_vendor_io { ...@@ -64,7 +86,11 @@ enum hda_cmd_vendor_io {
VENDOR_CHIPIO_HIC_POST_READ = 0x702, VENDOR_CHIPIO_HIC_POST_READ = 0x702,
VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
...@@ -72,18 +98,27 @@ enum hda_cmd_vendor_io { ...@@ -72,18 +98,27 @@ enum hda_cmd_vendor_io {
VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
VENDOR_CHIPIO_FLAG_SET = 0x70F, VENDOR_CHIPIO_FLAG_SET = 0x70F,
VENDOR_CHIPIO_FLAGS_GET = 0xF0F, VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
VENDOR_CHIPIO_PARAMETER_SET = 0x710, VENDOR_CHIPIO_PARAM_SET = 0x710,
VENDOR_CHIPIO_PARAMETER_GET = 0xF10, VENDOR_CHIPIO_PARAM_GET = 0xF10,
VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
VENDOR_CHIPIO_PORT_FREE_SET = 0x713, VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
VENDOR_CHIPIO_PARAMETER_EX_ID_GET = 0xF17, VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
VENDOR_CHIPIO_PARAMETER_EX_ID_SET = 0x717, VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
VENDOR_CHIPIO_PARAMETER_EX_VALUE_GET = 0xF18, VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
VENDOR_CHIPIO_PARAMETER_EX_VALUE_SET = 0x718 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
}; };
/* /*
...@@ -133,7 +168,7 @@ enum control_flag_id { ...@@ -133,7 +168,7 @@ enum control_flag_id {
/* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
/* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
CONTROL_FLAG_PORT_D_10K0HM_LOAD = 21, CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
/* ASI rate is 48kHz/96kHz */ /* ASI rate is 48kHz/96kHz */
CONTROL_FLAG_ASI_96KHZ = 22, CONTROL_FLAG_ASI_96KHZ = 22,
/* DAC power settings able to control attached ports no/yes */ /* DAC power settings able to control attached ports no/yes */
...@@ -147,7 +182,7 @@ enum control_flag_id { ...@@ -147,7 +182,7 @@ enum control_flag_id {
/* /*
* Control parameter IDs * Control parameter IDs
*/ */
enum control_parameter_id { enum control_param_id {
/* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
CONTROL_PARAM_SPDIF1_SOURCE = 2, CONTROL_PARAM_SPDIF1_SOURCE = 2,
......
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