Commit 4aace4ce authored by Mark Brown's avatar Mark Brown

Merge remote-tracking branches 'asoc/topic/fsl-asrc' and 'asoc/topic/fsl-ssi' into asoc-next

...@@ -996,6 +996,9 @@ static int fsl_asrc_suspend(struct device *dev) ...@@ -996,6 +996,9 @@ static int fsl_asrc_suspend(struct device *dev)
{ {
struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
regmap_read(asrc_priv->regmap, REG_ASRCFG,
&asrc_priv->regcache_cfg);
regcache_cache_only(asrc_priv->regmap, true); regcache_cache_only(asrc_priv->regmap, true);
regcache_mark_dirty(asrc_priv->regmap); regcache_mark_dirty(asrc_priv->regmap);
...@@ -1016,6 +1019,10 @@ static int fsl_asrc_resume(struct device *dev) ...@@ -1016,6 +1019,10 @@ static int fsl_asrc_resume(struct device *dev)
regcache_cache_only(asrc_priv->regmap, false); regcache_cache_only(asrc_priv->regmap, false);
regcache_sync(asrc_priv->regmap); regcache_sync(asrc_priv->regmap);
regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
/* Restart enabled pairs */ /* Restart enabled pairs */
regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
ASRCTR_ASRCEi_ALL_MASK, asrctr); ASRCTR_ASRCEi_ALL_MASK, asrctr);
......
...@@ -132,10 +132,13 @@ ...@@ -132,10 +132,13 @@
#define ASRCFG_INIRQi (1 << ASRCFG_INIRQi_SHIFT(i)) #define ASRCFG_INIRQi (1 << ASRCFG_INIRQi_SHIFT(i))
#define ASRCFG_NDPRi_SHIFT(i) (18 + i) #define ASRCFG_NDPRi_SHIFT(i) (18 + i)
#define ASRCFG_NDPRi_MASK(i) (1 << ASRCFG_NDPRi_SHIFT(i)) #define ASRCFG_NDPRi_MASK(i) (1 << ASRCFG_NDPRi_SHIFT(i))
#define ASRCFG_NDPRi_ALL_SHIFT 18
#define ASRCFG_NDPRi_ALL_MASK (7 << ASRCFG_NDPRi_ALL_SHIFT)
#define ASRCFG_NDPRi (1 << ASRCFG_NDPRi_SHIFT(i)) #define ASRCFG_NDPRi (1 << ASRCFG_NDPRi_SHIFT(i))
#define ASRCFG_POSTMODi_SHIFT(i) (8 + (i << 2)) #define ASRCFG_POSTMODi_SHIFT(i) (8 + (i << 2))
#define ASRCFG_POSTMODi_WIDTH 2 #define ASRCFG_POSTMODi_WIDTH 2
#define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i)) #define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
#define ASRCFG_POSTMODi_ALL_MASK (ASRCFG_POSTMODi_MASK(0) | ASRCFG_POSTMODi_MASK(1) | ASRCFG_POSTMODi_MASK(2))
#define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i)) #define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i))
#define ASRCFG_POSTMODi_UP(i) (0 << ASRCFG_POSTMODi_SHIFT(i)) #define ASRCFG_POSTMODi_UP(i) (0 << ASRCFG_POSTMODi_SHIFT(i))
#define ASRCFG_POSTMODi_DCON(i) (1 << ASRCFG_POSTMODi_SHIFT(i)) #define ASRCFG_POSTMODi_DCON(i) (1 << ASRCFG_POSTMODi_SHIFT(i))
...@@ -143,6 +146,7 @@ ...@@ -143,6 +146,7 @@
#define ASRCFG_PREMODi_SHIFT(i) (6 + (i << 2)) #define ASRCFG_PREMODi_SHIFT(i) (6 + (i << 2))
#define ASRCFG_PREMODi_WIDTH 2 #define ASRCFG_PREMODi_WIDTH 2
#define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i)) #define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
#define ASRCFG_PREMODi_ALL_MASK (ASRCFG_PREMODi_MASK(0) | ASRCFG_PREMODi_MASK(1) | ASRCFG_PREMODi_MASK(2))
#define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i)) #define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i))
#define ASRCFG_PREMODi_UP(i) (0 << ASRCFG_PREMODi_SHIFT(i)) #define ASRCFG_PREMODi_UP(i) (0 << ASRCFG_PREMODi_SHIFT(i))
#define ASRCFG_PREMODi_DCON(i) (1 << ASRCFG_PREMODi_SHIFT(i)) #define ASRCFG_PREMODi_DCON(i) (1 << ASRCFG_PREMODi_SHIFT(i))
...@@ -434,6 +438,7 @@ struct fsl_asrc_pair { ...@@ -434,6 +438,7 @@ struct fsl_asrc_pair {
* @channel_avail: non-occupied channel numbers * @channel_avail: non-occupied channel numbers
* @asrc_rate: default sample rate for ASoC Back-Ends * @asrc_rate: default sample rate for ASoC Back-Ends
* @asrc_width: default sample width for ASoC Back-Ends * @asrc_width: default sample width for ASoC Back-Ends
* @regcache_cfg: store register value of REG_ASRCFG
*/ */
struct fsl_asrc { struct fsl_asrc {
struct snd_dmaengine_dai_dma_data dma_params_rx; struct snd_dmaengine_dai_dma_data dma_params_rx;
...@@ -453,6 +458,8 @@ struct fsl_asrc { ...@@ -453,6 +458,8 @@ struct fsl_asrc {
int asrc_rate; int asrc_rate;
int asrc_width; int asrc_width;
u32 regcache_cfg;
}; };
extern struct snd_soc_platform_driver fsl_asrc_platform; extern struct snd_soc_platform_driver fsl_asrc_platform;
......
...@@ -146,6 +146,7 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) ...@@ -146,6 +146,7 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
case CCSR_SSI_SRX1: case CCSR_SSI_SRX1:
case CCSR_SSI_SISR: case CCSR_SSI_SISR:
case CCSR_SSI_SFCSR: case CCSR_SSI_SFCSR:
case CCSR_SSI_SACNT:
case CCSR_SSI_SACADD: case CCSR_SSI_SACADD:
case CCSR_SSI_SACDAT: case CCSR_SSI_SACDAT:
case CCSR_SSI_SATAG: case CCSR_SSI_SATAG:
...@@ -156,6 +157,21 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) ...@@ -156,6 +157,21 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
} }
} }
static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CCSR_SSI_SRX0:
case CCSR_SSI_SRX1:
case CCSR_SSI_SISR:
case CCSR_SSI_SACADD:
case CCSR_SSI_SACDAT:
case CCSR_SSI_SATAG:
return true;
default:
return false;
}
}
static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
{ {
switch (reg) { switch (reg) {
...@@ -178,6 +194,7 @@ static const struct regmap_config fsl_ssi_regconfig = { ...@@ -178,6 +194,7 @@ static const struct regmap_config fsl_ssi_regconfig = {
.num_reg_defaults = ARRAY_SIZE(fsl_ssi_reg_defaults), .num_reg_defaults = ARRAY_SIZE(fsl_ssi_reg_defaults),
.readable_reg = fsl_ssi_readable_reg, .readable_reg = fsl_ssi_readable_reg,
.volatile_reg = fsl_ssi_volatile_reg, .volatile_reg = fsl_ssi_volatile_reg,
.precious_reg = fsl_ssi_precious_reg,
.writeable_reg = fsl_ssi_writeable_reg, .writeable_reg = fsl_ssi_writeable_reg,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_RBTREE,
}; };
...@@ -239,8 +256,9 @@ struct fsl_ssi_private { ...@@ -239,8 +256,9 @@ struct fsl_ssi_private {
unsigned int baudclk_streams; unsigned int baudclk_streams;
unsigned int bitclk_freq; unsigned int bitclk_freq;
/*regcache for SFCSR*/ /* regcache for volatile regs */
u32 regcache_sfcsr; u32 regcache_sfcsr;
u32 regcache_sacnt;
/* DMA params */ /* DMA params */
struct snd_dmaengine_dai_dma_data dma_params_tx; struct snd_dmaengine_dai_dma_data dma_params_tx;
...@@ -1587,6 +1605,8 @@ static int fsl_ssi_suspend(struct device *dev) ...@@ -1587,6 +1605,8 @@ static int fsl_ssi_suspend(struct device *dev)
regmap_read(regs, CCSR_SSI_SFCSR, regmap_read(regs, CCSR_SSI_SFCSR,
&ssi_private->regcache_sfcsr); &ssi_private->regcache_sfcsr);
regmap_read(regs, CCSR_SSI_SACNT,
&ssi_private->regcache_sacnt);
regcache_cache_only(regs, true); regcache_cache_only(regs, true);
regcache_mark_dirty(regs); regcache_mark_dirty(regs);
...@@ -1605,6 +1625,8 @@ static int fsl_ssi_resume(struct device *dev) ...@@ -1605,6 +1625,8 @@ static int fsl_ssi_resume(struct device *dev)
CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK | CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK, CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
ssi_private->regcache_sfcsr); ssi_private->regcache_sfcsr);
regmap_write(regs, CCSR_SSI_SACNT,
ssi_private->regcache_sacnt);
return regcache_sync(regs); return regcache_sync(regs);
} }
......
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