Skip to content

L
linux
Commit 4c10b96f authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files
Options

perf vendor events: Add/update skylakex events/metrics 

Update events from v1.33 to v1.35.
Update TMA metrics from v4.7 to v4.8.

Bring in the event updates v1.35:
https://github.com/intel/perfmon/commit/c99b60c147b96f40f96dd961abfae54909f47e5f

The TMA 4.8 information was added in:
https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9a5736

Add counter information. The most recent RFC patch set using this
information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/

Adds the event SW_PREFETCH_ACCESS.ANY.
Co-authored-by: default avatarWeilin Wang <weilin.wang@intel.com>
Co-authored-by: default avatarCaleb Biggers <caleb.biggers@intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-33-irogers@google.com
parent e2641db8
Show whitespace changes
Inline Side-by-side
Showing with 7019 additions and 189 deletions
tools/perf/pmu-events/arch/x86/mapfile.csv
View file @ 4c10b96f
...@@ -30,7 +30,7 @@ GenuineIntel-6-8F,v1.23,sapphirerapids,core ...@@ -30,7 +30,7 @@ GenuineIntel-6-8F,v1.23,sapphirerapids,core
GenuineIntel-6-AF,v1.04,sierraforest,core GenuineIntel-6-AF,v1.04,sierraforest,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core
GenuineIntel-6-55-[01234],v1.33,skylakex,core GenuineIntel-6-55-[01234],v1.35,skylakex,core
GenuineIntel-6-86,v1.22,snowridgex,core GenuineIntel-6-86,v1.22,snowridgex,core
GenuineIntel-6-8[CD],v1.15,tigerlake,core GenuineIntel-6-8[CD],v1.15,tigerlake,core
GenuineIntel-6-2C,v5,westmereep-dp,core GenuineIntel-6-2C,v5,westmereep-dp,core
......
tools/perf/pmu-events/arch/x86/skylakex/cache.json
View file @ 4c10b96f
[ [
{ {
"BriefDescription": "L1D data line replacements", "BriefDescription": "L1D data line replacements",
"Counter": "0,1,2,3",
"EventCode": "0x51", "EventCode": "0x51",
"EventName": "L1D.REPLACEMENT", "EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
...@@ -9,6 +10,7 @@ ...@@ -9,6 +10,7 @@
}, },
{ {
"BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.", "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
"Counter": "0,1,2,3",
"EventCode": "0x48", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL", "EventName": "L1D_PEND_MISS.FB_FULL",
"PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.", "PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
...@@ -17,6 +19,7 @@ ...@@ -17,6 +19,7 @@
}, },
{ {
"BriefDescription": "L1D miss outstandings duration in cycles", "BriefDescription": "L1D miss outstandings duration in cycles",
"Counter": "0,1,2,3",
"EventCode": "0x48", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING", "EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", "PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
...@@ -25,6 +28,7 @@ ...@@ -25,6 +28,7 @@
}, },
{ {
"BriefDescription": "Cycles with L1D load Misses outstanding.", "BriefDescription": "Cycles with L1D load Misses outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x48", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES", "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
...@@ -35,6 +39,7 @@ ...@@ -35,6 +39,7 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x48", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
...@@ -43,6 +48,7 @@ ...@@ -43,6 +48,7 @@
}, },
{ {
"BriefDescription": "L2 cache lines filling L2", "BriefDescription": "L2 cache lines filling L2",
"Counter": "0,1,2,3",
"EventCode": "0xF1", "EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL", "EventName": "L2_LINES_IN.ALL",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
...@@ -51,6 +57,7 @@ ...@@ -51,6 +57,7 @@
}, },
{ {
"BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped", "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped",
"Counter": "0,1,2,3",
"EventCode": "0xF2", "EventCode": "0xF2",
"EventName": "L2_LINES_OUT.NON_SILENT", "EventName": "L2_LINES_OUT.NON_SILENT",
"PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped.", "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped.",
...@@ -59,6 +66,7 @@ ...@@ -59,6 +66,7 @@
}, },
{ {
"BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.", "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
"Counter": "0,1,2,3",
"EventCode": "0xF2", "EventCode": "0xF2",
"EventName": "L2_LINES_OUT.SILENT", "EventName": "L2_LINES_OUT.SILENT",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
...@@ -66,6 +74,7 @@ ...@@ -66,6 +74,7 @@
}, },
{ {
"BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache", "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0xF2", "EventCode": "0xF2",
"EventName": "L2_LINES_OUT.USELESS_HWPF", "EventName": "L2_LINES_OUT.USELESS_HWPF",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
...@@ -73,6 +82,7 @@ ...@@ -73,6 +82,7 @@
}, },
{ {
"BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
"Counter": "0,1,2,3",
"Deprecated": "1", "Deprecated": "1",
"EventCode": "0xF2", "EventCode": "0xF2",
"EventName": "L2_LINES_OUT.USELESS_PREF", "EventName": "L2_LINES_OUT.USELESS_PREF",
...@@ -81,6 +91,7 @@ ...@@ -81,6 +91,7 @@
}, },
{ {
"BriefDescription": "L2 code requests", "BriefDescription": "L2 code requests",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD", "EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts the total number of L2 code requests.", "PublicDescription": "Counts the total number of L2 code requests.",
...@@ -89,6 +100,7 @@ ...@@ -89,6 +100,7 @@
}, },
{ {
"BriefDescription": "Demand Data Read requests", "BriefDescription": "Demand Data Read requests",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
...@@ -97,6 +109,7 @@ ...@@ -97,6 +109,7 @@
}, },
{ {
"BriefDescription": "Demand requests that miss L2 cache", "BriefDescription": "Demand requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS", "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"PublicDescription": "Demand requests that miss L2 cache.", "PublicDescription": "Demand requests that miss L2 cache.",
...@@ -105,6 +118,7 @@ ...@@ -105,6 +118,7 @@
}, },
{ {
"BriefDescription": "Demand requests to L2 cache", "BriefDescription": "Demand requests to L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"PublicDescription": "Demand requests to L2 cache.", "PublicDescription": "Demand requests to L2 cache.",
...@@ -113,6 +127,7 @@ ...@@ -113,6 +127,7 @@
}, },
{ {
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches", "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF", "EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.", "PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
...@@ -121,6 +136,7 @@ ...@@ -121,6 +136,7 @@
}, },
{ {
"BriefDescription": "RFO requests to L2 cache", "BriefDescription": "RFO requests to L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO", "EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
...@@ -129,6 +145,7 @@ ...@@ -129,6 +145,7 @@
}, },
{ {
"BriefDescription": "L2 cache hits when fetching instructions, code reads.", "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT", "EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
...@@ -137,6 +154,7 @@ ...@@ -137,6 +154,7 @@
}, },
{ {
"BriefDescription": "L2 cache misses when fetching instructions", "BriefDescription": "L2 cache misses when fetching instructions",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS", "EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Counts L2 cache misses when fetching instructions.", "PublicDescription": "Counts L2 cache misses when fetching instructions.",
...@@ -145,6 +163,7 @@ ...@@ -145,6 +163,7 @@
}, },
{ {
"BriefDescription": "Demand Data Read requests that hit L2 cache", "BriefDescription": "Demand Data Read requests that hit L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
...@@ -153,6 +172,7 @@ ...@@ -153,6 +172,7 @@
}, },
{ {
"BriefDescription": "Demand Data Read miss L2, no rejects", "BriefDescription": "Demand Data Read miss L2, no rejects",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
...@@ -161,6 +181,7 @@ ...@@ -161,6 +181,7 @@
}, },
{ {
"BriefDescription": "All requests that miss L2 cache", "BriefDescription": "All requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.MISS", "EventName": "L2_RQSTS.MISS",
"PublicDescription": "All requests that miss L2 cache.", "PublicDescription": "All requests that miss L2 cache.",
...@@ -169,6 +190,7 @@ ...@@ -169,6 +190,7 @@
}, },
{ {
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache", "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT", "EventName": "L2_RQSTS.PF_HIT",
"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.", "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
...@@ -177,6 +199,7 @@ ...@@ -177,6 +199,7 @@
}, },
{ {
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache", "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS", "EventName": "L2_RQSTS.PF_MISS",
"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.", "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
...@@ -185,6 +208,7 @@ ...@@ -185,6 +208,7 @@
}, },
{ {
"BriefDescription": "All L2 requests", "BriefDescription": "All L2 requests",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES", "EventName": "L2_RQSTS.REFERENCES",
"PublicDescription": "All L2 requests.", "PublicDescription": "All L2 requests.",
...@@ -193,6 +217,7 @@ ...@@ -193,6 +217,7 @@
}, },
{ {
"BriefDescription": "RFO requests that hit L2 cache", "BriefDescription": "RFO requests that hit L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT", "EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
...@@ -201,6 +226,7 @@ ...@@ -201,6 +226,7 @@
}, },
{ {
"BriefDescription": "RFO requests that miss L2 cache", "BriefDescription": "RFO requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS", "EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
...@@ -209,6 +235,7 @@ ...@@ -209,6 +235,7 @@
}, },
{ {
"BriefDescription": "L2 writebacks that access L2 cache", "BriefDescription": "L2 writebacks that access L2 cache",
"Counter": "0,1,2,3",
"EventCode": "0xF0", "EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB", "EventName": "L2_TRANS.L2_WB",
"PublicDescription": "Counts L2 writebacks that access L2 cache.", "PublicDescription": "Counts L2 writebacks that access L2 cache.",
...@@ -217,6 +244,7 @@ ...@@ -217,6 +244,7 @@
}, },
{ {
"BriefDescription": "Core-originated cacheable demand requests missed L3", "BriefDescription": "Core-originated cacheable demand requests missed L3",
"Counter": "0,1,2,3",
"Errata": "SKL057", "Errata": "SKL057",
"EventCode": "0x2E", "EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS", "EventName": "LONGEST_LAT_CACHE.MISS",
...@@ -226,6 +254,7 @@ ...@@ -226,6 +254,7 @@
}, },
{ {
"BriefDescription": "Core-originated cacheable demand requests that refer to L3", "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
"Counter": "0,1,2,3",
"Errata": "SKL057", "Errata": "SKL057",
"EventCode": "0x2E", "EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE", "EventName": "LONGEST_LAT_CACHE.REFERENCE",
...@@ -235,6 +264,7 @@ ...@@ -235,6 +264,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions.", "BriefDescription": "Retired load instructions.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0", "EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS", "EventName": "MEM_INST_RETIRED.ALL_LOADS",
...@@ -245,6 +275,7 @@ ...@@ -245,6 +275,7 @@
}, },
{ {
"BriefDescription": "Retired store instructions.", "BriefDescription": "Retired store instructions.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0", "EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ALL_STORES", "EventName": "MEM_INST_RETIRED.ALL_STORES",
...@@ -255,6 +286,7 @@ ...@@ -255,6 +286,7 @@
}, },
{ {
"BriefDescription": "All retired memory instructions.", "BriefDescription": "All retired memory instructions.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0", "EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ANY", "EventName": "MEM_INST_RETIRED.ANY",
...@@ -265,6 +297,7 @@ ...@@ -265,6 +297,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions with locked access.", "BriefDescription": "Retired load instructions with locked access.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0", "EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS", "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
...@@ -274,6 +307,7 @@ ...@@ -274,6 +307,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions that split across a cacheline boundary.", "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0", "EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
...@@ -284,6 +318,7 @@ ...@@ -284,6 +318,7 @@
}, },
{ {
"BriefDescription": "Retired store instructions that split across a cacheline boundary.", "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0", "EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES", "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
...@@ -294,6 +329,7 @@ ...@@ -294,6 +329,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions that miss the STLB.", "BriefDescription": "Retired load instructions that miss the STLB.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0", "EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
...@@ -304,6 +340,7 @@ ...@@ -304,6 +340,7 @@
}, },
{ {
"BriefDescription": "Retired store instructions that miss the STLB.", "BriefDescription": "Retired store instructions that miss the STLB.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0", "EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
...@@ -314,6 +351,7 @@ ...@@ -314,6 +351,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache", "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD2", "EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
...@@ -324,6 +362,7 @@ ...@@ -324,6 +362,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3", "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD2", "EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
...@@ -334,6 +373,7 @@ ...@@ -334,6 +373,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD2", "EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
...@@ -343,6 +383,7 @@ ...@@ -343,6 +383,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required", "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD2", "EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
...@@ -353,6 +394,7 @@ ...@@ -353,6 +394,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD3", "EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
...@@ -363,6 +405,7 @@ ...@@ -363,6 +405,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram", "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD3", "EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
...@@ -372,6 +415,7 @@ ...@@ -372,6 +415,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache", "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD3", "EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
...@@ -382,6 +426,7 @@ ...@@ -382,6 +426,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions whose data sources was remote HITM", "BriefDescription": "Retired load instructions whose data sources was remote HITM",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD3", "EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
...@@ -392,6 +437,7 @@ ...@@ -392,6 +437,7 @@
}, },
{ {
"BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD4", "EventCode": "0xD4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC", "EventName": "MEM_LOAD_MISC_RETIRED.UC",
...@@ -401,6 +447,7 @@ ...@@ -401,6 +447,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready", "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1", "EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT", "EventName": "MEM_LOAD_RETIRED.FB_HIT",
...@@ -411,6 +458,7 @@ ...@@ -411,6 +458,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions with L1 cache hits as data sources", "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1", "EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT", "EventName": "MEM_LOAD_RETIRED.L1_HIT",
...@@ -421,6 +469,7 @@ ...@@ -421,6 +469,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions missed L1 cache as data sources", "BriefDescription": "Retired load instructions missed L1 cache as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1", "EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS", "EventName": "MEM_LOAD_RETIRED.L1_MISS",
...@@ -431,6 +480,7 @@ ...@@ -431,6 +480,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions with L2 cache hits as data sources", "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1", "EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT", "EventName": "MEM_LOAD_RETIRED.L2_HIT",
...@@ -441,6 +491,7 @@ ...@@ -441,6 +491,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions missed L2 cache as data sources", "BriefDescription": "Retired load instructions missed L2 cache as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1", "EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS", "EventName": "MEM_LOAD_RETIRED.L2_MISS",
...@@ -451,6 +502,7 @@ ...@@ -451,6 +502,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions with L3 cache hits as data sources", "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1", "EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT", "EventName": "MEM_LOAD_RETIRED.L3_HIT",
...@@ -461,6 +513,7 @@ ...@@ -461,6 +513,7 @@
}, },
{ {
"BriefDescription": "Retired load instructions missed L3 cache as data sources", "BriefDescription": "Retired load instructions missed L3 cache as data sources",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1", "EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS", "EventName": "MEM_LOAD_RETIRED.L3_MISS",
...@@ -471,6 +524,7 @@ ...@@ -471,6 +524,7 @@
}, },
{ {
"BriefDescription": "Demand and prefetch data reads", "BriefDescription": "Demand and prefetch data reads",
"Counter": "0,1,2,3",
"EventCode": "0xB0", "EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
...@@ -479,6 +533,7 @@ ...@@ -479,6 +533,7 @@
}, },
{ {
"BriefDescription": "Any memory transaction that reached the SQ.", "BriefDescription": "Any memory transaction that reached the SQ.",
"Counter": "0,1,2,3",
"EventCode": "0xB0", "EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..", "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
...@@ -487,6 +542,7 @@ ...@@ -487,6 +542,7 @@
}, },
{ {
"BriefDescription": "Cacheable and non-cacheable code read requests", "BriefDescription": "Cacheable and non-cacheable code read requests",
"Counter": "0,1,2,3",
"EventCode": "0xB0", "EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Counts both cacheable and non-cacheable code read requests.", "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
...@@ -495,6 +551,7 @@ ...@@ -495,6 +551,7 @@
}, },
{ {
"BriefDescription": "Demand Data Read requests sent to uncore", "BriefDescription": "Demand Data Read requests sent to uncore",
"Counter": "0,1,2,3",
"EventCode": "0xB0", "EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
...@@ -503,6 +560,7 @@ ...@@ -503,6 +560,7 @@
}, },
{ {
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
"Counter": "0,1,2,3",
"EventCode": "0xB0", "EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
...@@ -511,6 +569,7 @@ ...@@ -511,6 +569,7 @@
}, },
{ {
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
"Counter": "0,1,2,3",
"EventCode": "0xB2", "EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.", "PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
...@@ -519,6 +578,7 @@ ...@@ -519,6 +578,7 @@
}, },
{ {
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
...@@ -527,6 +587,7 @@ ...@@ -527,6 +587,7 @@
}, },
{ {
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
...@@ -536,6 +597,7 @@ ...@@ -536,6 +597,7 @@
}, },
{ {
"BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.", "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
...@@ -545,6 +607,7 @@ ...@@ -545,6 +607,7 @@
}, },
{ {
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
...@@ -554,6 +617,7 @@ ...@@ -554,6 +617,7 @@
}, },
{ {
"BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.", "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
...@@ -563,6 +627,7 @@ ...@@ -563,6 +627,7 @@
}, },
{ {
"BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.", "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
"Counter": "0,1,2,3",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
...@@ -571,6 +636,7 @@ ...@@ -571,6 +636,7 @@
}, },
{ {
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.", "PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
...@@ -579,6 +645,7 @@ ...@@ -579,6 +645,7 @@
}, },
{ {
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"CounterMask": "6", "CounterMask": "6",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
...@@ -587,6 +654,7 @@ ...@@ -587,6 +654,7 @@
}, },
{ {
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"Counter": "0,1,2,3",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", "PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
...@@ -595,6 +663,7 @@ ...@@ -595,6 +663,7 @@
}, },
{ {
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction", "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE", "EventName": "OFFCORE_RESPONSE",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
...@@ -603,6 +672,7 @@ ...@@ -603,6 +672,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that have any response type.", "BriefDescription": "Counts all demand & prefetch data reads that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -612,6 +682,7 @@ ...@@ -612,6 +682,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that hit in the L3.", "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -621,6 +692,7 @@ ...@@ -621,6 +692,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -630,6 +702,7 @@ ...@@ -630,6 +702,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -639,6 +712,7 @@ ...@@ -639,6 +712,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -648,6 +722,7 @@ ...@@ -648,6 +722,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -657,6 +732,7 @@ ...@@ -657,6 +732,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that have any response type.", "BriefDescription": "Counts all prefetch data reads that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -666,6 +742,7 @@ ...@@ -666,6 +742,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that hit in the L3.", "BriefDescription": "Counts all prefetch data reads that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -675,6 +752,7 @@ ...@@ -675,6 +752,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -684,6 +762,7 @@ ...@@ -684,6 +762,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -693,6 +772,7 @@ ...@@ -693,6 +772,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -702,6 +782,7 @@ ...@@ -702,6 +782,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -711,6 +792,7 @@ ...@@ -711,6 +792,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that have any response type.", "BriefDescription": "Counts prefetch RFOs that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -720,6 +802,7 @@ ...@@ -720,6 +802,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that hit in the L3.", "BriefDescription": "Counts prefetch RFOs that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -729,6 +812,7 @@ ...@@ -729,6 +812,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -738,6 +822,7 @@ ...@@ -738,6 +822,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -747,6 +832,7 @@ ...@@ -747,6 +832,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -756,6 +842,7 @@ ...@@ -756,6 +842,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -765,6 +852,7 @@ ...@@ -765,6 +852,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD hit in the L3 and the snoop to one of the sibling cores hits the line in E/S/F state and the line is forwarded.", "BriefDescription": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD hit in the L3 and the snoop to one of the sibling cores hits the line in E/S/F state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -774,6 +862,7 @@ ...@@ -774,6 +862,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that have any response type.", "BriefDescription": "Counts all demand & prefetch RFOs that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -783,6 +872,7 @@ ...@@ -783,6 +872,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3.", "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -792,6 +882,7 @@ ...@@ -792,6 +882,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -801,6 +892,7 @@ ...@@ -801,6 +892,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -810,6 +902,7 @@ ...@@ -810,6 +902,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -819,6 +912,7 @@ ...@@ -819,6 +912,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -828,6 +922,7 @@ ...@@ -828,6 +922,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that have any response type.", "BriefDescription": "Counts all demand code reads that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -837,6 +932,7 @@ ...@@ -837,6 +932,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that hit in the L3.", "BriefDescription": "Counts all demand code reads that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -846,6 +942,7 @@ ...@@ -846,6 +942,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -855,6 +952,7 @@ ...@@ -855,6 +952,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -864,6 +962,7 @@ ...@@ -864,6 +962,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -873,6 +972,7 @@ ...@@ -873,6 +972,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -882,6 +982,7 @@ ...@@ -882,6 +982,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that have any response type.", "BriefDescription": "Counts demand data reads that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -891,6 +992,7 @@ ...@@ -891,6 +992,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that hit in the L3.", "BriefDescription": "Counts demand data reads that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -900,6 +1002,7 @@ ...@@ -900,6 +1002,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -909,6 +1012,7 @@ ...@@ -909,6 +1012,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -918,6 +1022,7 @@ ...@@ -918,6 +1022,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -927,6 +1032,7 @@ ...@@ -927,6 +1032,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -936,6 +1042,7 @@ ...@@ -936,6 +1042,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that have any response type.", "BriefDescription": "Counts all demand data writes (RFOs) that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -945,6 +1052,7 @@ ...@@ -945,6 +1052,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3.", "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -954,6 +1062,7 @@ ...@@ -954,6 +1062,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -963,6 +1072,7 @@ ...@@ -963,6 +1072,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -972,6 +1082,7 @@ ...@@ -972,6 +1082,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -981,6 +1092,7 @@ ...@@ -981,6 +1092,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -990,6 +1102,7 @@ ...@@ -990,6 +1102,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that have any response type.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -999,6 +1112,7 @@ ...@@ -999,6 +1112,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1008,6 +1122,7 @@ ...@@ -1008,6 +1122,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1017,6 +1132,7 @@ ...@@ -1017,6 +1132,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1026,6 +1142,7 @@ ...@@ -1026,6 +1142,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1035,6 +1152,7 @@ ...@@ -1035,6 +1152,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1044,6 +1162,7 @@ ...@@ -1044,6 +1162,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that have any response type.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1053,6 +1172,7 @@ ...@@ -1053,6 +1172,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1062,6 +1182,7 @@ ...@@ -1062,6 +1182,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1071,6 +1192,7 @@ ...@@ -1071,6 +1192,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1080,6 +1202,7 @@ ...@@ -1080,6 +1202,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1089,6 +1212,7 @@ ...@@ -1089,6 +1212,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1098,6 +1222,7 @@ ...@@ -1098,6 +1222,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1107,6 +1232,7 @@ ...@@ -1107,6 +1232,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1116,6 +1242,7 @@ ...@@ -1116,6 +1242,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1125,6 +1252,7 @@ ...@@ -1125,6 +1252,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1134,6 +1262,7 @@ ...@@ -1134,6 +1262,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1143,6 +1272,7 @@ ...@@ -1143,6 +1272,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1152,6 +1282,7 @@ ...@@ -1152,6 +1282,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1161,6 +1292,7 @@ ...@@ -1161,6 +1292,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1170,6 +1302,7 @@ ...@@ -1170,6 +1302,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1179,6 +1312,7 @@ ...@@ -1179,6 +1312,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1188,6 +1322,7 @@ ...@@ -1188,6 +1322,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1197,6 +1332,7 @@ ...@@ -1197,6 +1332,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1206,6 +1342,7 @@ ...@@ -1206,6 +1342,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1215,6 +1352,7 @@ ...@@ -1215,6 +1352,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1224,6 +1362,7 @@ ...@@ -1224,6 +1362,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1233,6 +1372,7 @@ ...@@ -1233,6 +1372,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1242,6 +1382,7 @@ ...@@ -1242,6 +1382,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1251,6 +1392,7 @@ ...@@ -1251,6 +1392,7 @@
}, },
{ {
"BriefDescription": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1260,14 +1402,24 @@ ...@@ -1260,14 +1402,24 @@
}, },
{ {
"BriefDescription": "Number of cache line split locks sent to uncore.", "BriefDescription": "Number of cache line split locks sent to uncore.",
"Counter": "0,1,2,3",
"EventCode": "0xF4", "EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK", "EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "Counts the number of cache line split locks sent to the uncore.", "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x10" "UMask": "0x10"
}, },
{
"BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.ANY",
"SampleAfterValue": "2000003",
"UMask": "0xf"
},
{ {
"BriefDescription": "Number of PREFETCHNTA instructions executed.", "BriefDescription": "Number of PREFETCHNTA instructions executed.",
"Counter": "0,1,2,3",
"EventCode": "0x32", "EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.NTA", "EventName": "SW_PREFETCH_ACCESS.NTA",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1275,6 +1427,7 @@ ...@@ -1275,6 +1427,7 @@
}, },
{ {
"BriefDescription": "Number of PREFETCHW instructions executed.", "BriefDescription": "Number of PREFETCHW instructions executed.",
"Counter": "0,1,2,3",
"EventCode": "0x32", "EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1282,6 +1435,7 @@ ...@@ -1282,6 +1435,7 @@
}, },
{ {
"BriefDescription": "Number of PREFETCHT0 instructions executed.", "BriefDescription": "Number of PREFETCHT0 instructions executed.",
"Counter": "0,1,2,3",
"EventCode": "0x32", "EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T0", "EventName": "SW_PREFETCH_ACCESS.T0",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -1289,6 +1443,7 @@ ...@@ -1289,6 +1443,7 @@
}, },
{ {
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"Counter": "0,1,2,3",
"EventCode": "0x32", "EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2", "EventName": "SW_PREFETCH_ACCESS.T1_T2",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
......
tools/perf/pmu-events/arch/x86/skylakex/counter.json 0 → 100644
View file @ 4c10b96f
[
{
"Unit": "core",
"CountersNumFixed": "3",
"CountersNumGeneric": "4"
},
{
"Unit": "CHA",
"CountersNumFixed": "0",
"CountersNumGeneric": "4"
},
{
"Unit": "IIO",
"CountersNumFixed": "0",
"CountersNumGeneric": "4"
},
{
"Unit": "IRP",
"CountersNumFixed": "0",
"CountersNumGeneric": "2"
},
{
"Unit": "UPI",
"CountersNumFixed": "0",
"CountersNumGeneric": "4"
},
{
"Unit": "M2M",
"CountersNumFixed": "0",
"CountersNumGeneric": "4"
},
{
"Unit": "iMC",
"CountersNumFixed": "1",
"CountersNumGeneric": "4"
},
{
"Unit": "M3UPI",
"CountersNumFixed": "0",
"CountersNumGeneric": "3"
},
{
"Unit": "PCU",
"CountersNumFixed": "0",
"CountersNumGeneric": "4"
},
{
"Unit": "UBOX",
"CountersNumFixed": "1",
"CountersNumGeneric": "2"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/skylakex/floating-point.json
View file @ 4c10b96f
[ [
{ {
"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -9,6 +10,7 @@ ...@@ -9,6 +10,7 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -17,6 +19,7 @@ ...@@ -17,6 +19,7 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -25,6 +28,7 @@ ...@@ -25,6 +28,7 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -33,6 +37,7 @@ ...@@ -33,6 +37,7 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -41,6 +46,7 @@ ...@@ -41,6 +46,7 @@
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -49,6 +55,7 @@ ...@@ -49,6 +55,7 @@
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -57,6 +64,7 @@ ...@@ -57,6 +64,7 @@
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -65,6 +73,7 @@ ...@@ -65,6 +73,7 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR", "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"PublicDescription": "Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -73,6 +82,7 @@ ...@@ -73,6 +82,7 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -81,6 +91,7 @@ ...@@ -81,6 +91,7 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -89,6 +100,7 @@ ...@@ -89,6 +100,7 @@
}, },
{ {
"BriefDescription": "Number of any Vector retired FP arithmetic instructions", "BriefDescription": "Number of any Vector retired FP arithmetic instructions",
"Counter": "0,1,2,3",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.VECTOR", "EventName": "FP_ARITH_INST_RETIRED.VECTOR",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -96,6 +108,7 @@ ...@@ -96,6 +108,7 @@
}, },
{ {
"BriefDescription": "Cycles with any input/output SSE or FP assist", "BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xCA", "EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY", "EventName": "FP_ASSIST.ANY",
......
tools/perf/pmu-events/arch/x86/skylakex/frontend.json
View file @ 4c10b96f
[ [
{ {
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"Counter": "0,1,2,3",
"EventCode": "0xE6", "EventCode": "0xE6",
"EventName": "BACLEARS.ANY", "EventName": "BACLEARS.ANY",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
...@@ -9,6 +10,7 @@ ...@@ -9,6 +10,7 @@
}, },
{ {
"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]", "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]",
"Counter": "0,1,2,3",
"EventCode": "0x87", "EventCode": "0x87",
"EventName": "DECODE.LCP", "EventName": "DECODE.LCP",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]", "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]",
...@@ -17,6 +19,7 @@ ...@@ -17,6 +19,7 @@
}, },
{ {
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
"Counter": "0,1,2,3",
"EventCode": "0xAB", "EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT", "EventName": "DSB2MITE_SWITCHES.COUNT",
"PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay.", "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay.",
...@@ -25,6 +28,7 @@ ...@@ -25,6 +28,7 @@
}, },
{ {
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"Counter": "0,1,2,3",
"EventCode": "0xAB", "EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
...@@ -33,6 +37,7 @@ ...@@ -33,6 +37,7 @@
}, },
{ {
"BriefDescription": "Retired Instructions who experienced DSB miss.", "BriefDescription": "Retired Instructions who experienced DSB miss.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -44,6 +49,7 @@ ...@@ -44,6 +49,7 @@
}, },
{ {
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.", "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.DSB_MISS", "EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -55,6 +61,7 @@ ...@@ -55,6 +61,7 @@
}, },
{ {
"BriefDescription": "Retired Instructions who experienced iTLB true miss.", "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS", "EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -66,6 +73,7 @@ ...@@ -66,6 +73,7 @@
}, },
{ {
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.L1I_MISS", "EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -76,6 +84,7 @@ ...@@ -76,6 +84,7 @@
}, },
{ {
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.L2_MISS", "EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -86,6 +95,7 @@ ...@@ -86,6 +95,7 @@
}, },
{ {
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
"Counter": "0,1,2,3",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -97,6 +107,7 @@ ...@@ -97,6 +107,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -107,6 +118,7 @@ ...@@ -107,6 +118,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -118,6 +130,7 @@ ...@@ -118,6 +130,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -128,6 +141,7 @@ ...@@ -128,6 +141,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -138,6 +152,7 @@ ...@@ -138,6 +152,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -149,6 +164,7 @@ ...@@ -149,6 +164,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -159,6 +175,7 @@ ...@@ -159,6 +175,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -169,6 +186,7 @@ ...@@ -169,6 +186,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -180,6 +198,7 @@ ...@@ -180,6 +198,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -190,6 +209,7 @@ ...@@ -190,6 +209,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -200,6 +220,7 @@ ...@@ -200,6 +220,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -210,6 +231,7 @@ ...@@ -210,6 +231,7 @@
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -221,6 +243,7 @@ ...@@ -221,6 +243,7 @@
}, },
{ {
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
"Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.STLB_MISS", "EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
...@@ -232,6 +255,7 @@ ...@@ -232,6 +255,7 @@
}, },
{ {
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
"Counter": "0,1,2,3",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL", "EventName": "ICACHE_16B.IFDATA_STALL",
"PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", "PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
...@@ -240,6 +264,7 @@ ...@@ -240,6 +264,7 @@
}, },
{ {
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
"Counter": "0,1,2,3",
"EventCode": "0x83", "EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT", "EventName": "ICACHE_64B.IFTAG_HIT",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
...@@ -247,6 +272,7 @@ ...@@ -247,6 +272,7 @@
}, },
{ {
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
"Counter": "0,1,2,3",
"EventCode": "0x83", "EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS", "EventName": "ICACHE_64B.IFTAG_MISS",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
...@@ -254,6 +280,7 @@ ...@@ -254,6 +280,7 @@
}, },
{ {
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
"Counter": "0,1,2,3",
"EventCode": "0x83", "EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_STALL", "EventName": "ICACHE_64B.IFTAG_STALL",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
...@@ -261,6 +288,7 @@ ...@@ -261,6 +288,7 @@
}, },
{ {
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
"Counter": "0,1,2,3",
"EventCode": "0x83", "EventCode": "0x83",
"EventName": "ICACHE_TAG.STALLS", "EventName": "ICACHE_TAG.STALLS",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
...@@ -268,6 +296,7 @@ ...@@ -268,6 +296,7 @@
}, },
{ {
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
"Counter": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
...@@ -277,6 +306,7 @@ ...@@ -277,6 +306,7 @@
}, },
{ {
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
...@@ -286,6 +316,7 @@ ...@@ -286,6 +316,7 @@
}, },
{ {
"BriefDescription": "Cycles MITE is delivering 4 Uops", "BriefDescription": "Cycles MITE is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
...@@ -295,6 +326,7 @@ ...@@ -295,6 +326,7 @@
}, },
{ {
"BriefDescription": "Cycles MITE is delivering any Uop", "BriefDescription": "Cycles MITE is delivering any Uop",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
...@@ -304,6 +336,7 @@ ...@@ -304,6 +336,7 @@
}, },
{ {
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES", "EventName": "IDQ.DSB_CYCLES",
...@@ -313,6 +346,7 @@ ...@@ -313,6 +346,7 @@
}, },
{ {
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY", "EventName": "IDQ.DSB_CYCLES_ANY",
...@@ -322,6 +356,7 @@ ...@@ -322,6 +356,7 @@
}, },
{ {
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
"Counter": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK", "EventName": "IDQ.DSB_CYCLES_OK",
...@@ -331,6 +366,7 @@ ...@@ -331,6 +366,7 @@
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS", "EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
...@@ -339,6 +375,7 @@ ...@@ -339,6 +375,7 @@
}, },
{ {
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES", "EventName": "IDQ.MITE_CYCLES",
...@@ -348,6 +385,7 @@ ...@@ -348,6 +385,7 @@
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS", "EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
...@@ -356,6 +394,7 @@ ...@@ -356,6 +394,7 @@
}, },
{ {
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES", "EventName": "IDQ.MS_CYCLES",
...@@ -365,6 +404,7 @@ ...@@ -365,6 +404,7 @@
}, },
{ {
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES", "EventName": "IDQ.MS_DSB_CYCLES",
...@@ -374,6 +414,7 @@ ...@@ -374,6 +414,7 @@
}, },
{ {
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"Counter": "0,1,2,3",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS", "EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
...@@ -382,6 +423,7 @@ ...@@ -382,6 +423,7 @@
}, },
{ {
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0x79", "EventCode": "0x79",
...@@ -392,6 +434,7 @@ ...@@ -392,6 +434,7 @@
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"Counter": "0,1,2,3",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_UOPS", "EventName": "IDQ.MS_UOPS",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
...@@ -400,6 +443,7 @@ ...@@ -400,6 +443,7 @@
}, },
{ {
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.", "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.",
...@@ -408,6 +452,7 @@ ...@@ -408,6 +452,7 @@
}, },
{ {
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
...@@ -417,6 +462,7 @@ ...@@ -417,6 +462,7 @@
}, },
{ {
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
...@@ -426,6 +472,7 @@ ...@@ -426,6 +472,7 @@
}, },
{ {
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterMask": "3", "CounterMask": "3",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
...@@ -435,6 +482,7 @@ ...@@ -435,6 +482,7 @@
}, },
{ {
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.", "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
...@@ -444,6 +492,7 @@ ...@@ -444,6 +492,7 @@
}, },
{ {
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.", "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x9C", "EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
......
tools/perf/pmu-events/arch/x86/skylakex/memory.json
View file @ 4c10b96f
[ [
{ {
"BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
...@@ -9,6 +10,7 @@ ...@@ -9,6 +10,7 @@
}, },
{ {
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "6", "CounterMask": "6",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
...@@ -17,6 +19,7 @@ ...@@ -17,6 +19,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
"Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED", "EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1", "PEBS": "1",
...@@ -26,6 +29,7 @@ ...@@ -26,6 +29,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
"Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_EVENTS", "EventName": "HLE_RETIRED.ABORTED_EVENTS",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -33,6 +37,7 @@ ...@@ -33,6 +37,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_MEM", "EventName": "HLE_RETIRED.ABORTED_MEM",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -40,6 +45,7 @@ ...@@ -40,6 +45,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
"Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_MEMTYPE", "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
"PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
...@@ -48,6 +54,7 @@ ...@@ -48,6 +54,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
"Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_TIMER", "EventName": "HLE_RETIRED.ABORTED_TIMER",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -55,6 +62,7 @@ ...@@ -55,6 +62,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
"Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -62,6 +70,7 @@ ...@@ -62,6 +70,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE execution successfully committed", "BriefDescription": "Number of times an HLE execution successfully committed",
"Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0xC8",
"EventName": "HLE_RETIRED.COMMIT", "EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.", "PublicDescription": "Number of times HLE commit succeeded.",
...@@ -70,6 +79,7 @@ ...@@ -70,6 +79,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE execution started.", "BriefDescription": "Number of times an HLE execution started.",
"Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0xC8",
"EventName": "HLE_RETIRED.START", "EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
...@@ -78,6 +88,7 @@ ...@@ -78,6 +88,7 @@
}, },
{ {
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"Counter": "0,1,2,3",
"Errata": "SKL089", "Errata": "SKL089",
"EventCode": "0xC3", "EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
...@@ -87,6 +98,7 @@ ...@@ -87,6 +98,7 @@
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
...@@ -99,6 +111,7 @@ ...@@ -99,6 +111,7 @@
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
...@@ -111,6 +124,7 @@ ...@@ -111,6 +124,7 @@
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
...@@ -123,6 +137,7 @@ ...@@ -123,6 +137,7 @@
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
...@@ -135,6 +150,7 @@ ...@@ -135,6 +150,7 @@
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
...@@ -147,6 +163,7 @@ ...@@ -147,6 +163,7 @@
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
...@@ -159,6 +176,7 @@ ...@@ -159,6 +176,7 @@
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
...@@ -171,6 +189,7 @@ ...@@ -171,6 +189,7 @@
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
...@@ -183,6 +202,7 @@ ...@@ -183,6 +202,7 @@
}, },
{ {
"BriefDescription": "Demand Data Read requests who miss L3 cache", "BriefDescription": "Demand Data Read requests who miss L3 cache",
"Counter": "0,1,2,3",
"EventCode": "0xB0", "EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"PublicDescription": "Demand Data Read requests who miss L3 cache.", "PublicDescription": "Demand Data Read requests who miss L3 cache.",
...@@ -191,6 +211,7 @@ ...@@ -191,6 +211,7 @@
}, },
{ {
"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
...@@ -199,6 +220,7 @@ ...@@ -199,6 +220,7 @@
}, },
{ {
"BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
"Counter": "0,1,2,3",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -206,6 +228,7 @@ ...@@ -206,6 +228,7 @@
}, },
{ {
"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
"Counter": "0,1,2,3",
"CounterMask": "6", "CounterMask": "6",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
...@@ -214,6 +237,7 @@ ...@@ -214,6 +237,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -223,6 +247,7 @@ ...@@ -223,6 +247,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -232,6 +257,7 @@ ...@@ -232,6 +257,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -241,6 +267,7 @@ ...@@ -241,6 +267,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -250,6 +277,7 @@ ...@@ -250,6 +277,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -259,6 +287,7 @@ ...@@ -259,6 +287,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -268,6 +297,7 @@ ...@@ -268,6 +297,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that miss in the L3.", "BriefDescription": "Counts all prefetch data reads that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -277,6 +307,7 @@ ...@@ -277,6 +307,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -286,6 +317,7 @@ ...@@ -286,6 +317,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -295,6 +327,7 @@ ...@@ -295,6 +327,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -304,6 +337,7 @@ ...@@ -304,6 +337,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -313,6 +347,7 @@ ...@@ -313,6 +347,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -322,6 +357,7 @@ ...@@ -322,6 +357,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that miss in the L3.", "BriefDescription": "Counts prefetch RFOs that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -331,6 +367,7 @@ ...@@ -331,6 +367,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -340,6 +377,7 @@ ...@@ -340,6 +377,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -349,6 +387,7 @@ ...@@ -349,6 +387,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -358,6 +397,7 @@ ...@@ -358,6 +397,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -367,6 +407,7 @@ ...@@ -367,6 +407,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -376,6 +417,7 @@ ...@@ -376,6 +417,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.", "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -385,6 +427,7 @@ ...@@ -385,6 +427,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -394,6 +437,7 @@ ...@@ -394,6 +437,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -403,6 +447,7 @@ ...@@ -403,6 +447,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -412,6 +457,7 @@ ...@@ -412,6 +457,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -421,6 +467,7 @@ ...@@ -421,6 +467,7 @@
}, },
{ {
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -430,6 +477,7 @@ ...@@ -430,6 +477,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that miss in the L3.", "BriefDescription": "Counts all demand code reads that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -439,6 +487,7 @@ ...@@ -439,6 +487,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -448,6 +497,7 @@ ...@@ -448,6 +497,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -457,6 +507,7 @@ ...@@ -457,6 +507,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -466,6 +517,7 @@ ...@@ -466,6 +517,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -475,6 +527,7 @@ ...@@ -475,6 +527,7 @@
}, },
{ {
"BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -484,6 +537,7 @@ ...@@ -484,6 +537,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that miss in the L3.", "BriefDescription": "Counts demand data reads that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -493,6 +547,7 @@ ...@@ -493,6 +547,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -502,6 +557,7 @@ ...@@ -502,6 +557,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -511,6 +567,7 @@ ...@@ -511,6 +567,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -520,6 +577,7 @@ ...@@ -520,6 +577,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -529,6 +587,7 @@ ...@@ -529,6 +587,7 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -538,6 +597,7 @@ ...@@ -538,6 +597,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.", "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -547,6 +607,7 @@ ...@@ -547,6 +607,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -556,6 +617,7 @@ ...@@ -556,6 +617,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -565,6 +627,7 @@ ...@@ -565,6 +627,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -574,6 +637,7 @@ ...@@ -574,6 +637,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -583,6 +647,7 @@ ...@@ -583,6 +647,7 @@
}, },
{ {
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -592,6 +657,7 @@ ...@@ -592,6 +657,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -601,6 +667,7 @@ ...@@ -601,6 +667,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -610,6 +677,7 @@ ...@@ -610,6 +677,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -619,6 +687,7 @@ ...@@ -619,6 +687,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -628,6 +697,7 @@ ...@@ -628,6 +697,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -637,6 +707,7 @@ ...@@ -637,6 +707,7 @@
}, },
{ {
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -646,6 +717,7 @@ ...@@ -646,6 +717,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -655,6 +727,7 @@ ...@@ -655,6 +727,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -664,6 +737,7 @@ ...@@ -664,6 +737,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -673,6 +747,7 @@ ...@@ -673,6 +747,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -682,6 +757,7 @@ ...@@ -682,6 +757,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -691,6 +767,7 @@ ...@@ -691,6 +767,7 @@
}, },
{ {
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -700,6 +777,7 @@ ...@@ -700,6 +777,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -709,6 +787,7 @@ ...@@ -709,6 +787,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -718,6 +797,7 @@ ...@@ -718,6 +797,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -727,6 +807,7 @@ ...@@ -727,6 +807,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -736,6 +817,7 @@ ...@@ -736,6 +817,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -745,6 +827,7 @@ ...@@ -745,6 +827,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -754,6 +837,7 @@ ...@@ -754,6 +837,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -763,6 +847,7 @@ ...@@ -763,6 +847,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -772,6 +857,7 @@ ...@@ -772,6 +857,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -781,6 +867,7 @@ ...@@ -781,6 +867,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -790,6 +877,7 @@ ...@@ -790,6 +877,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -799,6 +887,7 @@ ...@@ -799,6 +887,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -808,6 +897,7 @@ ...@@ -808,6 +897,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -817,6 +907,7 @@ ...@@ -817,6 +907,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -826,6 +917,7 @@ ...@@ -826,6 +917,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -835,6 +927,7 @@ ...@@ -835,6 +927,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -844,6 +937,7 @@ ...@@ -844,6 +937,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -853,6 +947,7 @@ ...@@ -853,6 +947,7 @@
}, },
{ {
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.", "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -862,6 +957,7 @@ ...@@ -862,6 +957,7 @@
}, },
{ {
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
"Counter": "0,1,2,3",
"EventCode": "0xC9", "EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED", "EventName": "RTM_RETIRED.ABORTED",
"PEBS": "2", "PEBS": "2",
...@@ -871,6 +967,7 @@ ...@@ -871,6 +967,7 @@
}, },
{ {
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
"Counter": "0,1,2,3",
"EventCode": "0xC9", "EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS", "EventName": "RTM_RETIRED.ABORTED_EVENTS",
"PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
...@@ -879,6 +976,7 @@ ...@@ -879,6 +976,7 @@
}, },
{ {
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
"Counter": "0,1,2,3",
"EventCode": "0xC9", "EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_MEM", "EventName": "RTM_RETIRED.ABORTED_MEM",
"PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
...@@ -887,6 +985,7 @@ ...@@ -887,6 +985,7 @@
}, },
{ {
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
"Counter": "0,1,2,3",
"EventCode": "0xC9", "EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
"PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
...@@ -895,6 +994,7 @@ ...@@ -895,6 +994,7 @@
}, },
{ {
"BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
"Counter": "0,1,2,3",
"EventCode": "0xC9", "EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_TIMER", "EventName": "RTM_RETIRED.ABORTED_TIMER",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -902,6 +1002,7 @@ ...@@ -902,6 +1002,7 @@
}, },
{ {
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
"Counter": "0,1,2,3",
"EventCode": "0xC9", "EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
"PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
...@@ -910,6 +1011,7 @@ ...@@ -910,6 +1011,7 @@
}, },
{ {
"BriefDescription": "Number of times an RTM execution successfully committed", "BriefDescription": "Number of times an RTM execution successfully committed",
"Counter": "0,1,2,3",
"EventCode": "0xC9", "EventCode": "0xC9",
"EventName": "RTM_RETIRED.COMMIT", "EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.", "PublicDescription": "Number of times RTM commit succeeded.",
...@@ -918,6 +1020,7 @@ ...@@ -918,6 +1020,7 @@
}, },
{ {
"BriefDescription": "Number of times an RTM execution started.", "BriefDescription": "Number of times an RTM execution started.",
"Counter": "0,1,2,3",
"EventCode": "0xC9", "EventCode": "0xC9",
"EventName": "RTM_RETIRED.START", "EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
...@@ -926,6 +1029,7 @@ ...@@ -926,6 +1029,7 @@
}, },
{ {
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
"Counter": "0,1,2,3",
"EventCode": "0x5d", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1", "EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -933,6 +1037,7 @@ ...@@ -933,6 +1037,7 @@
}, },
{ {
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
"Counter": "0,1,2,3",
"EventCode": "0x5d", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2", "EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
...@@ -941,6 +1046,7 @@ ...@@ -941,6 +1046,7 @@
}, },
{ {
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
"Counter": "0,1,2,3",
"EventCode": "0x5d", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3", "EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
...@@ -949,6 +1055,7 @@ ...@@ -949,6 +1055,7 @@
}, },
{ {
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
"Counter": "0,1,2,3",
"EventCode": "0x5d", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4", "EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.", "PublicDescription": "RTM region detected inside HLE.",
...@@ -957,6 +1064,7 @@ ...@@ -957,6 +1064,7 @@
}, },
{ {
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
"Counter": "0,1,2,3",
"EventCode": "0x5d", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5", "EventName": "TX_EXEC.MISC5",
"PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
...@@ -965,6 +1073,7 @@ ...@@ -965,6 +1073,7 @@
}, },
{ {
"BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
"Counter": "0,1,2,3",
"EventCode": "0x54", "EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY", "EventName": "TX_MEM.ABORT_CAPACITY",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -972,6 +1081,7 @@ ...@@ -972,6 +1081,7 @@
}, },
{ {
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
"Counter": "0,1,2,3",
"EventCode": "0x54", "EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT", "EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Number of times a TSX line had a cache conflict.", "PublicDescription": "Number of times a TSX line had a cache conflict.",
...@@ -980,6 +1090,7 @@ ...@@ -980,6 +1090,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
"Counter": "0,1,2,3",
"EventCode": "0x54", "EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
...@@ -988,6 +1099,7 @@ ...@@ -988,6 +1099,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
"Counter": "0,1,2,3",
"EventCode": "0x54", "EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
...@@ -996,6 +1108,7 @@ ...@@ -996,6 +1108,7 @@
}, },
{ {
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
"Counter": "0,1,2,3",
"EventCode": "0x54", "EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
...@@ -1004,6 +1117,7 @@ ...@@ -1004,6 +1117,7 @@
}, },
{ {
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
"Counter": "0,1,2,3",
"EventCode": "0x54", "EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
...@@ -1012,6 +1126,7 @@ ...@@ -1012,6 +1126,7 @@
}, },
{ {
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
"Counter": "0,1,2,3",
"EventCode": "0x54", "EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PublicDescription": "Number of times we could not allocate Lock Buffer.", "PublicDescription": "Number of times we could not allocate Lock Buffer.",
......
tools/perf/pmu-events/arch/x86/skylakex/metricgroups.json
View file @ 4c10b96f
...@@ -5,7 +5,20 @@ ...@@ -5,7 +5,20 @@
"BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
"Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
......
tools/perf/pmu-events/arch/x86/skylakex/other.json
View file @ 4c10b96f
[ [
{ {
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
"Counter": "0,1,2,3",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
...@@ -9,6 +10,7 @@ ...@@ -9,6 +10,7 @@
}, },
{ {
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
"Counter": "0,1,2,3",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
...@@ -17,6 +19,7 @@ ...@@ -17,6 +19,7 @@
}, },
{ {
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
"Counter": "0,1,2,3",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.",
...@@ -25,6 +28,7 @@ ...@@ -25,6 +28,7 @@
}, },
{ {
"BriefDescription": "Core cycles the core was throttled due to a pending power level request.", "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
"Counter": "0,1,2,3",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.THROTTLE", "EventName": "CORE_POWER.THROTTLE",
"PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.", "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
...@@ -33,6 +37,7 @@ ...@@ -33,6 +37,7 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
"Counter": "0,1,2,3",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -40,6 +45,7 @@ ...@@ -40,6 +45,7 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
"Counter": "0,1,2,3",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -47,6 +53,7 @@ ...@@ -47,6 +53,7 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
"Counter": "0,1,2,3",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -54,6 +61,7 @@ ...@@ -54,6 +61,7 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI",
"Counter": "0,1,2,3",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -61,6 +69,7 @@ ...@@ -61,6 +69,7 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
"Counter": "0,1,2,3",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -68,6 +77,7 @@ ...@@ -68,6 +77,7 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
"Counter": "0,1,2,3",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -75,6 +85,7 @@ ...@@ -75,6 +85,7 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
"Counter": "0,1,2,3",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -82,6 +93,7 @@ ...@@ -82,6 +93,7 @@
}, },
{ {
"BriefDescription": "Number of hardware interrupts received by the processor.", "BriefDescription": "Number of hardware interrupts received by the processor.",
"Counter": "0,1,2,3",
"EventCode": "0xCB", "EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.RECEIVED", "EventName": "HW_INTERRUPTS.RECEIVED",
"PublicDescription": "Counts the number of hardware interruptions received by the processor.", "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
...@@ -90,6 +102,7 @@ ...@@ -90,6 +102,7 @@
}, },
{ {
"BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
"Counter": "0,1,2,3",
"EventCode": "0xFE", "EventCode": "0xFE",
"EventName": "IDI_MISC.WB_DOWNGRADE", "EventName": "IDI_MISC.WB_DOWNGRADE",
"PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
...@@ -98,6 +111,7 @@ ...@@ -98,6 +111,7 @@
}, },
{ {
"BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
"Counter": "0,1,2,3",
"EventCode": "0xFE", "EventCode": "0xFE",
"EventName": "IDI_MISC.WB_UPGRADE", "EventName": "IDI_MISC.WB_UPGRADE",
"PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
...@@ -106,6 +120,7 @@ ...@@ -106,6 +120,7 @@
}, },
{ {
"BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
"Counter": "0,1,2,3",
"EventCode": "0x09", "EventCode": "0x09",
"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
......
tools/perf/pmu-events/arch/x86/skylakex/pipeline.json
View file @ 4c10b96f
[ [
{ {
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x14", "EventCode": "0x14",
"EventName": "ARITH.DIVIDER_ACTIVE", "EventName": "ARITH.DIVIDER_ACTIVE",
...@@ -9,6 +10,7 @@ ...@@ -9,6 +10,7 @@
}, },
{ {
"BriefDescription": "All (macro) branch instructions retired.", "BriefDescription": "All (macro) branch instructions retired.",
"Counter": "0,1,2,3",
"Errata": "SKL091", "Errata": "SKL091",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES", "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
...@@ -17,6 +19,7 @@ ...@@ -17,6 +19,7 @@
}, },
{ {
"BriefDescription": "All (macro) branch instructions retired.", "BriefDescription": "All (macro) branch instructions retired.",
"Counter": "0,1,2,3",
"Errata": "SKL091", "Errata": "SKL091",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
...@@ -27,6 +30,7 @@ ...@@ -27,6 +30,7 @@
}, },
{ {
"BriefDescription": "Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL]", "BriefDescription": "Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL]",
"Counter": "0,1,2,3",
"Errata": "SKL091", "Errata": "SKL091",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.COND", "EventName": "BR_INST_RETIRED.COND",
...@@ -36,6 +40,7 @@ ...@@ -36,6 +40,7 @@
}, },
{ {
"BriefDescription": "Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND]", "BriefDescription": "Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND]",
"Counter": "0,1,2,3",
"Errata": "SKL091", "Errata": "SKL091",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL", "EventName": "BR_INST_RETIRED.CONDITIONAL",
...@@ -46,6 +51,7 @@ ...@@ -46,6 +51,7 @@
}, },
{ {
"BriefDescription": "Not taken branch instructions retired.", "BriefDescription": "Not taken branch instructions retired.",
"Counter": "0,1,2,3",
"Errata": "SKL091", "Errata": "SKL091",
"EventCode": "0xc4", "EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN", "EventName": "BR_INST_RETIRED.COND_NTAKEN",
...@@ -55,6 +61,7 @@ ...@@ -55,6 +61,7 @@
}, },
{ {
"BriefDescription": "Far branch instructions retired.", "BriefDescription": "Far branch instructions retired.",
"Counter": "0,1,2,3",
"Errata": "SKL091", "Errata": "SKL091",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH", "EventName": "BR_INST_RETIRED.FAR_BRANCH",
...@@ -65,6 +72,7 @@ ...@@ -65,6 +72,7 @@
}, },
{ {
"BriefDescription": "Direct and indirect near call instructions retired.", "BriefDescription": "Direct and indirect near call instructions retired.",
"Counter": "0,1,2,3",
"Errata": "SKL091", "Errata": "SKL091",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL", "EventName": "BR_INST_RETIRED.NEAR_CALL",
...@@ -75,6 +83,7 @@ ...@@ -75,6 +83,7 @@
}, },
{ {
"BriefDescription": "Return instructions retired.", "BriefDescription": "Return instructions retired.",
"Counter": "0,1,2,3",
"Errata": "SKL091", "Errata": "SKL091",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN", "EventName": "BR_INST_RETIRED.NEAR_RETURN",
...@@ -85,6 +94,7 @@ ...@@ -85,6 +94,7 @@
}, },
{ {
"BriefDescription": "Taken branch instructions retired.", "BriefDescription": "Taken branch instructions retired.",
"Counter": "0,1,2,3",
"Errata": "SKL091", "Errata": "SKL091",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN", "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
...@@ -95,6 +105,7 @@ ...@@ -95,6 +105,7 @@
}, },
{ {
"BriefDescription": "Not taken branch instructions retired.", "BriefDescription": "Not taken branch instructions retired.",
"Counter": "0,1,2,3",
"Errata": "SKL091", "Errata": "SKL091",
"EventCode": "0xC4", "EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN", "EventName": "BR_INST_RETIRED.NOT_TAKEN",
...@@ -104,6 +115,7 @@ ...@@ -104,6 +115,7 @@
}, },
{ {
"BriefDescription": "Speculative and retired mispredicted macro conditional branches", "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
"Counter": "0,1,2,3",
"EventCode": "0x89", "EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES", "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
...@@ -112,6 +124,7 @@ ...@@ -112,6 +124,7 @@
}, },
{ {
"BriefDescription": "Speculative mispredicted indirect branches", "BriefDescription": "Speculative mispredicted indirect branches",
"Counter": "0,1,2,3",
"EventCode": "0x89", "EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT", "EventName": "BR_MISP_EXEC.INDIRECT",
"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).",
...@@ -120,6 +133,7 @@ ...@@ -120,6 +133,7 @@
}, },
{ {
"BriefDescription": "All mispredicted macro branch instructions retired.", "BriefDescription": "All mispredicted macro branch instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
...@@ -127,6 +141,7 @@ ...@@ -127,6 +141,7 @@
}, },
{ {
"BriefDescription": "Mispredicted macro branch instructions retired.", "BriefDescription": "Mispredicted macro branch instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2", "PEBS": "2",
...@@ -136,6 +151,7 @@ ...@@ -136,6 +151,7 @@
}, },
{ {
"BriefDescription": "Mispredicted conditional branch instructions retired.", "BriefDescription": "Mispredicted conditional branch instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL", "EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1", "PEBS": "1",
...@@ -145,6 +161,7 @@ ...@@ -145,6 +161,7 @@
}, },
{ {
"BriefDescription": "Mispredicted direct and indirect near call instructions retired.", "BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
"Counter": "0,1,2,3",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL", "EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1", "PEBS": "1",
...@@ -154,6 +171,7 @@ ...@@ -154,6 +171,7 @@
}, },
{ {
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
"Counter": "0,1,2,3",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1", "PEBS": "1",
...@@ -162,6 +180,7 @@ ...@@ -162,6 +180,7 @@
}, },
{ {
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
"Counter": "0,1,2,3",
"EventCode": "0xC5", "EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RET", "EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1", "PEBS": "1",
...@@ -171,6 +190,7 @@ ...@@ -171,6 +190,7 @@
}, },
{ {
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
"Counter": "0,1,2,3",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "25003", "SampleAfterValue": "25003",
...@@ -178,6 +198,7 @@ ...@@ -178,6 +198,7 @@
}, },
{ {
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.", "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
"Counter": "0,1,2,3",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"SampleAfterValue": "25003", "SampleAfterValue": "25003",
...@@ -186,6 +207,7 @@ ...@@ -186,6 +207,7 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
"Counter": "0,1,2,3",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "25003", "SampleAfterValue": "25003",
...@@ -193,6 +215,7 @@ ...@@ -193,6 +215,7 @@
}, },
{ {
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
"Counter": "0,1,2,3",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "25003", "SampleAfterValue": "25003",
...@@ -200,6 +223,7 @@ ...@@ -200,6 +223,7 @@
}, },
{ {
"BriefDescription": "Reference cycles when the core is not in halt state.", "BriefDescription": "Reference cycles when the core is not in halt state.",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC", "EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -207,6 +231,7 @@ ...@@ -207,6 +231,7 @@
}, },
{ {
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.", "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
"Counter": "0,1,2,3",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK", "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"SampleAfterValue": "25003", "SampleAfterValue": "25003",
...@@ -215,6 +240,7 @@ ...@@ -215,6 +240,7 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
"Counter": "0,1,2,3",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "25003", "SampleAfterValue": "25003",
...@@ -222,6 +248,7 @@ ...@@ -222,6 +248,7 @@
}, },
{ {
"BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.", "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0x3C", "EventCode": "0x3C",
...@@ -231,6 +258,7 @@ ...@@ -231,6 +258,7 @@
}, },
{ {
"BriefDescription": "Core cycles when the thread is not in halt state", "BriefDescription": "Core cycles when the thread is not in halt state",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD", "EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -239,12 +267,14 @@ ...@@ -239,12 +267,14 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"UMask": "0x2" "UMask": "0x2"
}, },
{ {
"BriefDescription": "Thread cycles when thread is not in halt state", "BriefDescription": "Thread cycles when thread is not in halt state",
"Counter": "0,1,2,3",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P", "EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
...@@ -253,12 +283,14 @@ ...@@ -253,12 +283,14 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"Counter": "0,1,2,3",
"EventCode": "0x3C", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003" "SampleAfterValue": "2000003"
}, },
{ {
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "8", "CounterMask": "8",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
...@@ -267,6 +299,7 @@ ...@@ -267,6 +299,7 @@
}, },
{ {
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
...@@ -275,6 +308,7 @@ ...@@ -275,6 +308,7 @@
}, },
{ {
"BriefDescription": "Cycles while memory subsystem has an outstanding load.", "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
"Counter": "0,1,2,3",
"CounterMask": "16", "CounterMask": "16",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
...@@ -283,6 +317,7 @@ ...@@ -283,6 +317,7 @@
}, },
{ {
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "12", "CounterMask": "12",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
...@@ -291,6 +326,7 @@ ...@@ -291,6 +326,7 @@
}, },
{ {
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterMask": "5", "CounterMask": "5",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
...@@ -299,6 +335,7 @@ ...@@ -299,6 +335,7 @@
}, },
{ {
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
"Counter": "0,1,2,3",
"CounterMask": "20", "CounterMask": "20",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
...@@ -307,6 +344,7 @@ ...@@ -307,6 +344,7 @@
}, },
{ {
"BriefDescription": "Total execution stalls.", "BriefDescription": "Total execution stalls.",
"Counter": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0xA3", "EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
...@@ -315,6 +353,7 @@ ...@@ -315,6 +353,7 @@
}, },
{ {
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
"Counter": "0,1,2,3",
"EventCode": "0xA6", "EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
...@@ -323,6 +362,7 @@ ...@@ -323,6 +362,7 @@
}, },
{ {
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
"Counter": "0,1,2,3",
"EventCode": "0xA6", "EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
...@@ -331,6 +371,7 @@ ...@@ -331,6 +371,7 @@
}, },
{ {
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
"Counter": "0,1,2,3",
"EventCode": "0xA6", "EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
...@@ -339,6 +380,7 @@ ...@@ -339,6 +380,7 @@
}, },
{ {
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
"Counter": "0,1,2,3",
"EventCode": "0xA6", "EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
...@@ -347,6 +389,7 @@ ...@@ -347,6 +389,7 @@
}, },
{ {
"BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.", "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
"Counter": "0,1,2,3",
"EventCode": "0xA6", "EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -354,6 +397,7 @@ ...@@ -354,6 +397,7 @@
}, },
{ {
"BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.", "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
"Counter": "0,1,2,3",
"EventCode": "0xA6", "EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
"PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.", "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
...@@ -362,6 +406,7 @@ ...@@ -362,6 +406,7 @@
}, },
{ {
"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]", "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]",
"Counter": "0,1,2,3",
"EventCode": "0x87", "EventCode": "0x87",
"EventName": "ILD_STALL.LCP", "EventName": "ILD_STALL.LCP",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]", "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]",
...@@ -370,6 +415,7 @@ ...@@ -370,6 +415,7 @@
}, },
{ {
"BriefDescription": "Instruction decoders utilized in a cycle", "BriefDescription": "Instruction decoders utilized in a cycle",
"Counter": "0,1,2,3",
"EventCode": "0x55", "EventCode": "0x55",
"EventName": "INST_DECODED.DECODERS", "EventName": "INST_DECODED.DECODERS",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.", "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
...@@ -378,6 +424,7 @@ ...@@ -378,6 +424,7 @@
}, },
{ {
"BriefDescription": "Instructions retired from execution.", "BriefDescription": "Instructions retired from execution.",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY", "EventName": "INST_RETIRED.ANY",
"PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", "PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -385,6 +432,7 @@ ...@@ -385,6 +432,7 @@
}, },
{ {
"BriefDescription": "Number of instructions retired. General Counter - architectural event", "BriefDescription": "Number of instructions retired. General Counter - architectural event",
"Counter": "0,1,2,3",
"Errata": "SKL091, SKL044", "Errata": "SKL091, SKL044",
"EventCode": "0xC0", "EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P", "EventName": "INST_RETIRED.ANY_P",
...@@ -393,15 +441,17 @@ ...@@ -393,15 +441,17 @@
}, },
{ {
"BriefDescription": "Number of all retired NOP instructions.", "BriefDescription": "Number of all retired NOP instructions.",
"Counter": "0,1,2,3",
"Errata": "SKL091, SKL044", "Errata": "SKL091, SKL044",
"EventCode": "0xC0", "EventCode": "0xC0",
"EventName": "INST_RETIRED.NOP", "EventName": "INST_RETIRED.NOP",
"PEBS": "2", "PEBS": "1",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"UMask": "0x2" "UMask": "0x2"
}, },
{ {
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
"Counter": "1",
"Errata": "SKL091, SKL044", "Errata": "SKL091, SKL044",
"EventCode": "0xC0", "EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST", "EventName": "INST_RETIRED.PREC_DIST",
...@@ -412,6 +462,7 @@ ...@@ -412,6 +462,7 @@
}, },
{ {
"BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.", "BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.",
"Counter": "0,2,3",
"CounterMask": "10", "CounterMask": "10",
"Errata": "SKL091, SKL044", "Errata": "SKL091, SKL044",
"EventCode": "0xC0", "EventCode": "0xC0",
...@@ -424,6 +475,7 @@ ...@@ -424,6 +475,7 @@
}, },
{ {
"BriefDescription": "Clears speculative count", "BriefDescription": "Clears speculative count",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0x0D", "EventCode": "0x0D",
...@@ -434,6 +486,7 @@ ...@@ -434,6 +486,7 @@
}, },
{ {
"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.", "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
"Counter": "0,1,2,3",
"EventCode": "0x0D", "EventCode": "0x0D",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -441,6 +494,7 @@ ...@@ -441,6 +494,7 @@
}, },
{ {
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
"Counter": "0,1,2,3",
"EventCode": "0x0D", "EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES", "EventName": "INT_MISC.RECOVERY_CYCLES",
"PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", "PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
...@@ -450,6 +504,7 @@ ...@@ -450,6 +504,7 @@
{ {
"AnyThread": "1", "AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
"Counter": "0,1,2,3",
"EventCode": "0x0D", "EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -457,6 +512,7 @@ ...@@ -457,6 +512,7 @@
}, },
{ {
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
"Counter": "0,1,2,3",
"EventCode": "0x03", "EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR", "EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
...@@ -465,6 +521,7 @@ ...@@ -465,6 +521,7 @@
}, },
{ {
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
"Counter": "0,1,2,3",
"EventCode": "0x03", "EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD", "EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
...@@ -473,6 +530,7 @@ ...@@ -473,6 +530,7 @@
}, },
{ {
"BriefDescription": "False dependencies in MOB due to partial compare on address.", "BriefDescription": "False dependencies in MOB due to partial compare on address.",
"Counter": "0,1,2,3",
"EventCode": "0x07", "EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", "PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
...@@ -481,6 +539,7 @@ ...@@ -481,6 +539,7 @@
}, },
{ {
"BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
"Counter": "0,1,2,3",
"EventCode": "0x4C", "EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF", "EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
...@@ -489,6 +548,7 @@ ...@@ -489,6 +548,7 @@
}, },
{ {
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_OK]", "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_OK]",
"Counter": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0xA8", "EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS", "EventName": "LSD.CYCLES_4_UOPS",
...@@ -498,6 +558,7 @@ ...@@ -498,6 +558,7 @@
}, },
{ {
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xA8", "EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE", "EventName": "LSD.CYCLES_ACTIVE",
...@@ -507,6 +568,7 @@ ...@@ -507,6 +568,7 @@
}, },
{ {
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS]", "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS]",
"Counter": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0xA8", "EventCode": "0xA8",
"EventName": "LSD.CYCLES_OK", "EventName": "LSD.CYCLES_OK",
...@@ -516,6 +578,7 @@ ...@@ -516,6 +578,7 @@
}, },
{ {
"BriefDescription": "Number of Uops delivered by the LSD.", "BriefDescription": "Number of Uops delivered by the LSD.",
"Counter": "0,1,2,3",
"EventCode": "0xA8", "EventCode": "0xA8",
"EventName": "LSD.UOPS", "EventName": "LSD.UOPS",
"PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).", "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
...@@ -524,6 +587,7 @@ ...@@ -524,6 +587,7 @@
}, },
{ {
"BriefDescription": "Number of machine clears (nukes) of any type.", "BriefDescription": "Number of machine clears (nukes) of any type.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0xC3", "EventCode": "0xC3",
...@@ -533,6 +597,7 @@ ...@@ -533,6 +597,7 @@
}, },
{ {
"BriefDescription": "Self-modifying code (SMC) detected.", "BriefDescription": "Self-modifying code (SMC) detected.",
"Counter": "0,1,2,3",
"EventCode": "0xC3", "EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC", "EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
...@@ -541,6 +606,7 @@ ...@@ -541,6 +606,7 @@
}, },
{ {
"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.", "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
"Counter": "0,1,2,3",
"EventCode": "0xC1", "EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY", "EventName": "OTHER_ASSISTS.ANY",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -548,6 +614,7 @@ ...@@ -548,6 +614,7 @@
}, },
{ {
"BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.", "BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
"Counter": "0,1,2,3",
"EventCode": "0x59", "EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
"PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.", "PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
...@@ -556,6 +623,7 @@ ...@@ -556,6 +623,7 @@
}, },
{ {
"BriefDescription": "Resource-related stall cycles", "BriefDescription": "Resource-related stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xa2", "EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.ANY", "EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "Counts resource-related stall cycles.", "PublicDescription": "Counts resource-related stall cycles.",
...@@ -564,6 +632,7 @@ ...@@ -564,6 +632,7 @@
}, },
{ {
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
"Counter": "0,1,2,3",
"EventCode": "0xA2", "EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB", "EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
...@@ -572,6 +641,7 @@ ...@@ -572,6 +641,7 @@
}, },
{ {
"BriefDescription": "Increments whenever there is an update to the LBR array.", "BriefDescription": "Increments whenever there is an update to the LBR array.",
"Counter": "0,1,2,3",
"EventCode": "0xCC", "EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
...@@ -580,6 +650,7 @@ ...@@ -580,6 +650,7 @@
}, },
{ {
"BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.", "BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
"Counter": "0,1,2,3",
"EventCode": "0xCC", "EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.PAUSE_INST", "EventName": "ROB_MISC_EVENTS.PAUSE_INST",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -587,6 +658,7 @@ ...@@ -587,6 +658,7 @@
}, },
{ {
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
"Counter": "0,1,2,3",
"EventCode": "0x5E", "EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES", "EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
...@@ -595,6 +667,7 @@ ...@@ -595,6 +667,7 @@
}, },
{ {
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0x5E", "EventCode": "0x5E",
...@@ -606,6 +679,7 @@ ...@@ -606,6 +679,7 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 0", "BriefDescription": "Cycles per thread when uops are executed in port 0",
"Counter": "0,1,2,3",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0", "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
...@@ -614,6 +688,7 @@ ...@@ -614,6 +688,7 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 1", "BriefDescription": "Cycles per thread when uops are executed in port 1",
"Counter": "0,1,2,3",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
...@@ -622,6 +697,7 @@ ...@@ -622,6 +697,7 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 2", "BriefDescription": "Cycles per thread when uops are executed in port 2",
"Counter": "0,1,2,3",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2", "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
...@@ -630,6 +706,7 @@ ...@@ -630,6 +706,7 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 3", "BriefDescription": "Cycles per thread when uops are executed in port 3",
"Counter": "0,1,2,3",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3", "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
...@@ -638,6 +715,7 @@ ...@@ -638,6 +715,7 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 4", "BriefDescription": "Cycles per thread when uops are executed in port 4",
"Counter": "0,1,2,3",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4", "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
...@@ -646,6 +724,7 @@ ...@@ -646,6 +724,7 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 5", "BriefDescription": "Cycles per thread when uops are executed in port 5",
"Counter": "0,1,2,3",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5", "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
...@@ -654,6 +733,7 @@ ...@@ -654,6 +733,7 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 6", "BriefDescription": "Cycles per thread when uops are executed in port 6",
"Counter": "0,1,2,3",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6", "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
...@@ -662,6 +742,7 @@ ...@@ -662,6 +742,7 @@
}, },
{ {
"BriefDescription": "Cycles per thread when uops are executed in port 7", "BriefDescription": "Cycles per thread when uops are executed in port 7",
"Counter": "0,1,2,3",
"EventCode": "0xA1", "EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7", "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
...@@ -670,6 +751,7 @@ ...@@ -670,6 +751,7 @@
}, },
{ {
"BriefDescription": "Number of uops executed on the core.", "BriefDescription": "Number of uops executed on the core.",
"Counter": "0,1,2,3",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE", "EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Number of uops executed from any thread.", "PublicDescription": "Number of uops executed from any thread.",
...@@ -678,6 +760,7 @@ ...@@ -678,6 +760,7 @@
}, },
{ {
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
...@@ -686,6 +769,7 @@ ...@@ -686,6 +769,7 @@
}, },
{ {
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
...@@ -694,6 +778,7 @@ ...@@ -694,6 +778,7 @@
}, },
{ {
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterMask": "3", "CounterMask": "3",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
...@@ -702,6 +787,7 @@ ...@@ -702,6 +787,7 @@
}, },
{ {
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
...@@ -710,6 +796,7 @@ ...@@ -710,6 +796,7 @@
}, },
{ {
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
...@@ -719,6 +806,7 @@ ...@@ -719,6 +806,7 @@
}, },
{ {
"BriefDescription": "Cycles where at least 1 uop was executed per-thread", "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
...@@ -728,6 +816,7 @@ ...@@ -728,6 +816,7 @@
}, },
{ {
"BriefDescription": "Cycles where at least 2 uops were executed per-thread", "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
"Counter": "0,1,2,3",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
...@@ -737,6 +826,7 @@ ...@@ -737,6 +826,7 @@
}, },
{ {
"BriefDescription": "Cycles where at least 3 uops were executed per-thread", "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
"Counter": "0,1,2,3",
"CounterMask": "3", "CounterMask": "3",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
...@@ -746,6 +836,7 @@ ...@@ -746,6 +836,7 @@
}, },
{ {
"BriefDescription": "Cycles where at least 4 uops were executed per-thread", "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
"Counter": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
...@@ -755,6 +846,7 @@ ...@@ -755,6 +846,7 @@
}, },
{ {
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES", "EventName": "UOPS_EXECUTED.STALL_CYCLES",
...@@ -765,6 +857,7 @@ ...@@ -765,6 +857,7 @@
}, },
{ {
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
"Counter": "0,1,2,3",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD", "EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Number of uops to be executed per-thread each cycle.", "PublicDescription": "Number of uops to be executed per-thread each cycle.",
...@@ -773,6 +866,7 @@ ...@@ -773,6 +866,7 @@
}, },
{ {
"BriefDescription": "Counts the number of x87 uops dispatched.", "BriefDescription": "Counts the number of x87 uops dispatched.",
"Counter": "0,1,2,3",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.X87", "EventName": "UOPS_EXECUTED.X87",
"PublicDescription": "Counts the number of x87 uops executed.", "PublicDescription": "Counts the number of x87 uops executed.",
...@@ -781,6 +875,7 @@ ...@@ -781,6 +875,7 @@
}, },
{ {
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
"Counter": "0,1,2,3",
"EventCode": "0x0E", "EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY", "EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
...@@ -789,6 +884,7 @@ ...@@ -789,6 +884,7 @@
}, },
{ {
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
"Counter": "0,1,2,3",
"EventCode": "0x0E", "EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA", "EventName": "UOPS_ISSUED.SLOW_LEA",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -796,6 +892,7 @@ ...@@ -796,6 +892,7 @@
}, },
{ {
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x0E", "EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES", "EventName": "UOPS_ISSUED.STALL_CYCLES",
...@@ -806,6 +903,7 @@ ...@@ -806,6 +903,7 @@
}, },
{ {
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
"Counter": "0,1,2,3",
"EventCode": "0x0E", "EventCode": "0x0E",
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
...@@ -814,6 +912,7 @@ ...@@ -814,6 +912,7 @@
}, },
{ {
"BriefDescription": "Number of macro-fused uops retired. (non precise)", "BriefDescription": "Number of macro-fused uops retired. (non precise)",
"Counter": "0,1,2,3",
"EventCode": "0xc2", "EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MACRO_FUSED", "EventName": "UOPS_RETIRED.MACRO_FUSED",
"PublicDescription": "Counts the number of macro-fused uops retired. (non precise)", "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
...@@ -822,6 +921,7 @@ ...@@ -822,6 +921,7 @@
}, },
{ {
"BriefDescription": "Retirement slots used.", "BriefDescription": "Retirement slots used.",
"Counter": "0,1,2,3",
"EventCode": "0xC2", "EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS", "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PublicDescription": "Counts the retirement slots used.", "PublicDescription": "Counts the retirement slots used.",
...@@ -830,6 +930,7 @@ ...@@ -830,6 +930,7 @@
}, },
{ {
"BriefDescription": "Cycles without actually retired uops.", "BriefDescription": "Cycles without actually retired uops.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xC2", "EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES", "EventName": "UOPS_RETIRED.STALL_CYCLES",
...@@ -840,6 +941,7 @@ ...@@ -840,6 +941,7 @@
}, },
{ {
"BriefDescription": "Cycles with less than 10 actually retired uops.", "BriefDescription": "Cycles with less than 10 actually retired uops.",
"Counter": "0,1,2,3",
"CounterMask": "16", "CounterMask": "16",
"EventCode": "0xC2", "EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES", "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
......
tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
View file @ 4c10b96f
...@@ -68,7 +68,7 @@ ...@@ -68,7 +68,7 @@
}, },
{ {
"BriefDescription": "Percentage of time spent in the active CPU power state C0", "BriefDescription": "Percentage of time spent in the active CPU power state C0",
"MetricExpr": "tma_info_system_cpu_utilization", "MetricExpr": "tma_info_system_cpus_utilized",
"MetricName": "cpu_utilization", "MetricName": "cpu_utilization",
"ScaleUnit": "100%" "ScaleUnit": "100%"
}, },
...@@ -163,7 +163,7 @@ ...@@ -163,7 +163,7 @@
}, },
{ {
"BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
"MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=0x12CC0233@ / INST_RETIRED.ANY", "MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=0x12cc0233@ / INST_RETIRED.ANY",
"MetricName": "llc_code_read_mpi_demand_plus_prefetch", "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
"ScaleUnit": "1per_instr" "ScaleUnit": "1per_instr"
}, },
...@@ -187,7 +187,7 @@ ...@@ -187,7 +187,7 @@
}, },
{ {
"BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
"MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=0x12D40433@ / INST_RETIRED.ANY", "MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=0x12d40433@ / INST_RETIRED.ANY",
"MetricName": "llc_data_read_mpi_demand_plus_prefetch", "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
"ScaleUnit": "1per_instr" "ScaleUnit": "1per_instr"
}, },
...@@ -310,7 +310,7 @@ ...@@ -310,7 +310,7 @@
{ {
"BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
"MetricExpr": "34 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info_thread_slots", "MetricExpr": "34 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info_thread_slots",
"MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
"MetricName": "tma_assists", "MetricName": "tma_assists",
"MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)",
"PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
...@@ -319,7 +319,7 @@ ...@@ -319,7 +319,7 @@
{ {
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
"MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_thread_slots", "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_thread_slots",
"MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group",
"MetricName": "tma_backend_bound", "MetricName": "tma_backend_bound",
"MetricThreshold": "tma_backend_bound > 0.2", "MetricThreshold": "tma_backend_bound > 0.2",
"MetricgroupNoGroup": "TopdownL1", "MetricgroupNoGroup": "TopdownL1",
...@@ -340,7 +340,7 @@ ...@@ -340,7 +340,7 @@
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
"MetricName": "tma_branch_mispredicts", "MetricName": "tma_branch_mispredicts",
"MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15",
"MetricgroupNoGroup": "TopdownL2", "MetricgroupNoGroup": "TopdownL2",
...@@ -378,7 +378,7 @@ ...@@ -378,7 +378,7 @@
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "(44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 44 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", "MetricExpr": "(44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 44 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
"MetricName": "tma_contested_accesses", "MetricName": "tma_contested_accesses",
"MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache",
...@@ -399,7 +399,7 @@ ...@@ -399,7 +399,7 @@
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", "MetricExpr": "44 * tma_info_system_core_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
"MetricName": "tma_data_sharing", "MetricName": "tma_data_sharing",
"MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache",
...@@ -417,7 +417,7 @@ ...@@ -417,7 +417,7 @@
{ {
"BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
"MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks", "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks",
"MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group",
"MetricName": "tma_divider", "MetricName": "tma_divider",
"MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
"PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
...@@ -448,14 +448,14 @@ ...@@ -448,14 +448,14 @@
"MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB",
"MetricName": "tma_dsb_switches", "MetricName": "tma_dsb_switches",
"MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
"ScaleUnit": "100%" "ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
"MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricConstraint": "NO_GROUP_EVENTS_NMI",
"MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks",
"MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group",
"MetricName": "tma_dtlb_load", "MetricName": "tma_dtlb_load",
"MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization", "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization",
...@@ -464,7 +464,7 @@ ...@@ -464,7 +464,7 @@
{ {
"BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
"MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks",
"MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group",
"MetricName": "tma_dtlb_store", "MetricName": "tma_dtlb_store",
"MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization", "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization",
...@@ -474,7 +474,7 @@ ...@@ -474,7 +474,7 @@
"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "(110 * tma_info_system_core_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_info_system_core_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_thread_clks", "MetricExpr": "(110 * tma_info_system_core_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_info_system_core_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_thread_clks",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group",
"MetricName": "tma_false_sharing", "MetricName": "tma_false_sharing",
"MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache",
...@@ -484,7 +484,7 @@ ...@@ -484,7 +484,7 @@
"BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
"MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricConstraint": "NO_GROUP_EVENTS_NMI",
"MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_thread_clks", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_thread_clks",
"MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group",
"MetricName": "tma_fb_full", "MetricName": "tma_fb_full",
"MetricThreshold": "tma_fb_full > 0.3", "MetricThreshold": "tma_fb_full > 0.3",
"PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores",
...@@ -497,7 +497,7 @@ ...@@ -497,7 +497,7 @@
"MetricName": "tma_fetch_bandwidth", "MetricName": "tma_fetch_bandwidth",
"MetricThreshold": "tma_fetch_bandwidth > 0.2", "MetricThreshold": "tma_fetch_bandwidth > 0.2",
"MetricgroupNoGroup": "TopdownL2", "MetricgroupNoGroup": "TopdownL2",
"PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
"ScaleUnit": "100%" "ScaleUnit": "100%"
}, },
{ {
...@@ -512,6 +512,7 @@ ...@@ -512,6 +512,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
"MetricConstraint": "NO_GROUP_EVENTS_NMI",
"MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
"MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0",
"MetricName": "tma_few_uops_instructions", "MetricName": "tma_few_uops_instructions",
...@@ -540,7 +541,7 @@ ...@@ -540,7 +541,7 @@
}, },
{ {
"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
"MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / UOPS_RETIRED.RETIRE_SLOTS", "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / UOPS_RETIRED.RETIRE_SLOTS",
"MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P",
"MetricName": "tma_fp_scalar", "MetricName": "tma_fp_scalar",
"MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)",
...@@ -587,7 +588,7 @@ ...@@ -587,7 +588,7 @@
{ {
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots",
"MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group",
"MetricName": "tma_frontend_bound", "MetricName": "tma_frontend_bound",
"MetricThreshold": "tma_frontend_bound > 0.15", "MetricThreshold": "tma_frontend_bound > 0.15",
"MetricgroupNoGroup": "TopdownL1", "MetricgroupNoGroup": "TopdownL1",
...@@ -597,7 +598,7 @@ ...@@ -597,7 +598,7 @@
{ {
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
"MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS", "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS",
"MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
"MetricName": "tma_fused_instructions", "MetricName": "tma_fused_instructions",
"MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6", "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6",
"PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}",
...@@ -616,7 +617,7 @@ ...@@ -616,7 +617,7 @@
{ {
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
"MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / tma_info_thread_clks", "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / tma_info_thread_clks",
"MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
"MetricName": "tma_icache_misses", "MetricName": "tma_icache_misses",
"MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
...@@ -649,24 +650,6 @@ ...@@ -649,24 +650,6 @@
"MetricGroup": "BrMispredicts", "MetricGroup": "BrMispredicts",
"MetricName": "tma_info_bad_spec_spec_clears_ratio" "MetricName": "tma_info_bad_spec_spec_clears_ratio"
}, },
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
"MetricExpr": "(100 * (1 - tma_core_bound / (((EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) if tma_core_bound < (((EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0)",
"MetricGroup": "Cor;SMT",
"MetricName": "tma_info_botlnk_core_bound_likely"
},
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
"MetricExpr": "100 * (100 * (tma_fetch_latency * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) + tma_fetch_bandwidth * tma_mite / (tma_mite + tma_dsb)))",
"MetricGroup": "DSBmiss;Fed",
"MetricName": "tma_info_botlnk_dsb_misses"
},
{
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.",
"MetricExpr": "100 * (100 * (tma_fetch_latency * ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD)))",
"MetricGroup": "Fed;FetchLat;IcMiss",
"MetricName": "tma_info_botlnk_ic_misses"
},
{ {
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
...@@ -675,6 +658,14 @@ ...@@ -675,6 +658,14 @@
"MetricName": "tma_info_botlnk_l0_core_bound_likely", "MetricName": "tma_info_botlnk_l0_core_bound_likely",
"MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5"
}, },
{
"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck",
"MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite)))",
"MetricGroup": "DSB;FetchBW;tma_issueFB",
"MetricName": "tma_info_botlnk_l2_dsb_bandwidth",
"MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10",
"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp"
},
{ {
"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
...@@ -682,7 +673,7 @@ ...@@ -682,7 +673,7 @@
"MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricGroup": "DSBmiss;Fed;tma_issueFB",
"MetricName": "tma_info_botlnk_l2_dsb_misses", "MetricName": "tma_info_botlnk_l2_dsb_misses",
"MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10",
"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp"
}, },
{ {
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck",
...@@ -692,40 +683,34 @@ ...@@ -692,40 +683,34 @@
"MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5",
"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: " "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: "
}, },
{
"BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.",
"MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
"MetricGroup": "Ret",
"MetricName": "tma_info_bottleneck_base_non_br",
"MetricThreshold": "tma_info_bottleneck_base_non_br > 20"
},
{ {
"BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
"MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB",
"MetricName": "tma_info_bottleneck_big_code", "MetricName": "tma_info_bottleneck_big_code",
"MetricThreshold": "tma_info_bottleneck_big_code > 20" "MetricThreshold": "tma_info_bottleneck_big_code > 20"
}, },
{ {
"BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", "BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA",
"MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots)", "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)",
"MetricGroup": "Ret", "MetricGroup": "BvBO;Ret",
"MetricName": "tma_info_bottleneck_branching_overhead", "MetricName": "tma_info_bottleneck_branching_overhead",
"MetricThreshold": "tma_info_bottleneck_branching_overhead > 5" "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5",
"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)"
}, },
{ {
"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks",
"MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))",
"MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW",
"MetricName": "tma_info_bottleneck_cache_memory_bandwidth", "MetricName": "tma_info_bottleneck_cache_memory_bandwidth",
"MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 20", "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 20",
"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" "PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full"
}, },
{ {
"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
"MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))", "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))",
"MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat",
"MetricName": "tma_info_bottleneck_cache_memory_latency", "MetricName": "tma_info_bottleneck_cache_memory_latency",
"MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20",
"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency" "PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency"
...@@ -733,23 +718,23 @@ ...@@ -733,23 +718,23 @@
{ {
"BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation", "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
"MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))",
"MetricGroup": "Cor;tma_issueComp", "MetricGroup": "BvCB;Cor;tma_issueComp",
"MetricName": "tma_info_bottleneck_compute_bound_est", "MetricName": "tma_info_bottleneck_compute_bound_est",
"MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20",
"PublicDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics: " "PublicDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics: "
}, },
{ {
"BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code", "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code",
"MetricGroup": "Fed;FetchBW;Frontend", "MetricGroup": "BvFB;Fed;FetchBW;Frontend",
"MetricName": "tma_info_bottleneck_instruction_fetch_bw", "MetricName": "tma_info_bottleneck_instruction_fetch_bw",
"MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20"
}, },
{ {
"BriefDescription": "Total pipeline cost of irregular execution (e.g", "BriefDescription": "Total pipeline cost of irregular execution (e.g",
"MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", "MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
"MetricGroup": "Bad;Cor;Ret;tma_issueMS", "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS",
"MetricName": "tma_info_bottleneck_irregular_overhead", "MetricName": "tma_info_bottleneck_irregular_overhead",
"MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10",
"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches" "PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches"
...@@ -757,8 +742,8 @@ ...@@ -757,8 +742,8 @@
{ {
"BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))", "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))",
"MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB",
"MetricName": "tma_info_bottleneck_memory_data_tlbs", "MetricName": "tma_info_bottleneck_memory_data_tlbs",
"MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20",
"PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization" "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization"
...@@ -766,7 +751,7 @@ ...@@ -766,7 +751,7 @@
{ {
"BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)", "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)",
"MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes))", "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes))",
"MetricGroup": "Mem;Offcore;tma_issueTLB", "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB",
"MetricName": "tma_info_bottleneck_memory_synchronization", "MetricName": "tma_info_bottleneck_memory_synchronization",
"MetricThreshold": "tma_info_bottleneck_memory_synchronization > 10", "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 10",
"PublicDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs" "PublicDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs"
...@@ -775,18 +760,25 @@ ...@@ -775,18 +760,25 @@
"BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
"MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM",
"MetricName": "tma_info_bottleneck_mispredictions", "MetricName": "tma_info_bottleneck_mispredictions",
"MetricThreshold": "tma_info_bottleneck_mispredictions > 20", "MetricThreshold": "tma_info_bottleneck_mispredictions > 20",
"PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers" "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers"
}, },
{ {
"BriefDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class)", "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
"MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info_bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_latency + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_synchronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_irregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottleneck_base_non_br)", "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info_bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_latency + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_synchronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_irregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottleneck_useful_work)",
"MetricGroup": "Cor;Offcore", "MetricGroup": "BvOB;Cor;Offcore",
"MetricName": "tma_info_bottleneck_other_bottlenecks", "MetricName": "tma_info_bottleneck_other_bottlenecks",
"MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20",
"PublicDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class). Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls." "PublicDescription": "Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls."
},
{
"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.",
"MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
"MetricGroup": "BvUW;Ret",
"MetricName": "tma_info_bottleneck_useful_work",
"MetricThreshold": "tma_info_bottleneck_useful_work > 20"
}, },
{ {
"BriefDescription": "Fraction of branches that are CALL or RET", "BriefDescription": "Fraction of branches that are CALL or RET",
...@@ -840,7 +832,7 @@ ...@@ -840,7 +832,7 @@
}, },
{ {
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
"MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@) / (2 * tma_info_core_core_clks)", "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@) / (2 * tma_info_core_core_clks)",
"MetricGroup": "Cor;Flops;HPC", "MetricGroup": "Cor;Flops;HPC",
"MetricName": "tma_info_core_fp_arith_utilization", "MetricName": "tma_info_core_fp_arith_utilization",
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
...@@ -857,7 +849,7 @@ ...@@ -857,7 +849,7 @@
"MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB",
"MetricName": "tma_info_frontend_dsb_coverage", "MetricName": "tma_info_frontend_dsb_coverage",
"MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35", "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35",
"PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp" "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp"
}, },
{ {
"BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
...@@ -918,7 +910,7 @@ ...@@ -918,7 +910,7 @@
{ {
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@)", "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@)",
"MetricGroup": "Flops;InsType", "MetricGroup": "Flops;InsType",
"MetricName": "tma_info_inst_mix_iparith", "MetricName": "tma_info_inst_mix_iparith",
"MetricThreshold": "tma_info_inst_mix_iparith < 10", "MetricThreshold": "tma_info_inst_mix_iparith < 10",
...@@ -1008,18 +1000,12 @@ ...@@ -1008,18 +1000,12 @@
"MetricThreshold": "tma_info_inst_mix_ipswpf < 100" "MetricThreshold": "tma_info_inst_mix_ipswpf < 100"
}, },
{ {
"BriefDescription": "Instruction per taken branch", "BriefDescription": "Instructions per taken branch",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB",
"MetricName": "tma_info_inst_mix_iptb", "MetricName": "tma_info_inst_mix_iptb",
"MetricThreshold": "tma_info_inst_mix_iptb < 9", "MetricThreshold": "tma_info_inst_mix_iptb < 9",
"PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" "PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp"
},
{
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_code_stlb_mpki",
"MetricGroup": "Fed;MemoryTLB",
"MetricName": "tma_info_memory_code_stlb_mpki"
}, },
{ {
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
...@@ -1057,12 +1043,6 @@ ...@@ -1057,12 +1043,6 @@
"MetricGroup": "Mem;MemoryBW", "MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t"
}, },
{
"BriefDescription": "Average Parallel L2 cache miss data reads",
"MetricExpr": "tma_info_memory_latency_data_l2_mlp",
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_data_l2_mlp"
},
{ {
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
"MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
...@@ -1070,17 +1050,11 @@ ...@@ -1070,17 +1050,11 @@
"MetricName": "tma_info_memory_fb_hpki" "MetricName": "tma_info_memory_fb_hpki"
}, },
{ {
"BriefDescription": "", "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW", "MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l1d_cache_fill_bw" "MetricName": "tma_info_memory_l1d_cache_fill_bw"
}, },
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l1d_cache_fill_bw_2t"
},
{ {
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
...@@ -1094,29 +1068,11 @@ ...@@ -1094,29 +1068,11 @@
"MetricName": "tma_info_memory_l1mpki_load" "MetricName": "tma_info_memory_l1mpki_load"
}, },
{ {
"BriefDescription": "", "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW", "MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l2_cache_fill_bw" "MetricName": "tma_info_memory_l2_cache_fill_bw"
}, },
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l2_cache_fill_bw_2t"
},
{
"BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
"MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY",
"MetricGroup": "L2Evicts;Mem;Server",
"MetricName": "tma_info_memory_l2_evictions_nonsilent_pki"
},
{
"BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
"MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY",
"MetricGroup": "L2Evicts;Mem;Server",
"MetricName": "tma_info_memory_l2_evictions_silent_pki"
},
{ {
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
"MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
...@@ -1148,29 +1104,23 @@ ...@@ -1148,29 +1104,23 @@
"MetricName": "tma_info_memory_l2mpki_load" "MetricName": "tma_info_memory_l2mpki_load"
}, },
{ {
"BriefDescription": "", "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.ANY",
"MetricGroup": "Mem;MemoryBW;Offcore", "MetricGroup": "CacheMisses;Offcore",
"MetricName": "tma_info_memory_l3_cache_access_bw" "MetricName": "tma_info_memory_l2mpki_rfo"
}, },
{ {
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duration_time * 1e3 / 1e3)", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW;Offcore", "MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "tma_info_memory_l3_cache_access_bw_2t" "MetricName": "tma_info_memory_l3_cache_access_bw"
}, },
{ {
"BriefDescription": "", "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW", "MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l3_cache_fill_bw" "MetricName": "tma_info_memory_l3_cache_fill_bw"
}, },
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time * 1e3 / 1e3)",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "tma_info_memory_l3_cache_fill_bw_2t"
},
{ {
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
...@@ -1183,29 +1133,17 @@ ...@@ -1183,29 +1133,17 @@
"MetricGroup": "Memory_BW;Offcore", "MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_latency_data_l2_mlp" "MetricName": "tma_info_memory_latency_data_l2_mlp"
}, },
{
"BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "tma_info_memory_load_l2_miss_latency",
"MetricGroup": "Memory_Lat;Offcore",
"MetricName": "tma_info_memory_latency_load_l2_miss_latency"
},
{
"BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "tma_info_memory_load_l2_mlp",
"MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_latency_load_l2_mlp"
},
{ {
"BriefDescription": "Average Latency for L2 cache miss demand Loads", "BriefDescription": "Average Latency for L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD",
"MetricGroup": "Memory_Lat;Offcore", "MetricGroup": "Memory_Lat;Offcore",
"MetricName": "tma_info_memory_load_l2_miss_latency" "MetricName": "tma_info_memory_latency_load_l2_miss_latency"
}, },
{ {
"BriefDescription": "Average Parallel L2 cache miss demand Loads", "BriefDescription": "Average Parallel L2 cache miss demand Loads",
"MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"MetricGroup": "Memory_BW;Offcore", "MetricGroup": "Memory_BW;Offcore",
"MetricName": "tma_info_memory_load_l2_mlp" "MetricName": "tma_info_memory_latency_load_l2_mlp"
}, },
{ {
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
...@@ -1213,15 +1151,9 @@ ...@@ -1213,15 +1151,9 @@
"MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "tma_info_memory_load_miss_real_latency" "MetricName": "tma_info_memory_load_miss_real_latency"
}, },
{
"BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_load_stlb_mpki",
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_load_stlb_mpki"
},
{ {
"BriefDescription": "Un-cacheable retired load per kilo instruction", "BriefDescription": "Un-cacheable retired load per kilo instruction",
"MetricExpr": "tma_info_memory_uc_load_pki", "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
"MetricGroup": "Mem", "MetricGroup": "Mem",
"MetricName": "tma_info_memory_mix_uc_load_pki" "MetricName": "tma_info_memory_mix_uc_load_pki"
}, },
...@@ -1232,18 +1164,6 @@ ...@@ -1232,18 +1164,6 @@
"MetricName": "tma_info_memory_mlp", "MetricName": "tma_info_memory_mlp",
"PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)"
}, },
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "tma_info_memory_tlb_page_walks_utilization",
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_page_walks_utilization"
},
{
"BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "tma_info_memory_tlb_store_stlb_mpki",
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "tma_info_memory_store_stlb_mpki"
},
{ {
"BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)",
"MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
...@@ -1271,17 +1191,23 @@ ...@@ -1271,17 +1191,23 @@
"MetricName": "tma_info_memory_tlb_store_stlb_mpki" "MetricName": "tma_info_memory_tlb_store_stlb_mpki"
}, },
{ {
"BriefDescription": "Un-cacheable retired load per kilo instruction", "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per core",
"MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY",
"MetricGroup": "Mem",
"MetricName": "tma_info_memory_uc_load_pki"
},
{
"BriefDescription": "",
"MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@)", "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@)",
"MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
"MetricName": "tma_info_pipeline_execute" "MetricName": "tma_info_pipeline_execute"
}, },
{
"BriefDescription": "Average number of uops fetched from DSB per cycle",
"MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY",
"MetricGroup": "Fed;FetchBW",
"MetricName": "tma_info_pipeline_fetch_dsb"
},
{
"BriefDescription": "Average number of uops fetched from MITE per cycle",
"MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES",
"MetricGroup": "Fed;FetchBW",
"MetricName": "tma_info_pipeline_fetch_mite"
},
{ {
"BriefDescription": "Instructions per a microcode Assist invocation", "BriefDescription": "Instructions per a microcode Assist invocation",
"MetricExpr": "INST_RETIRED.ANY / (FP_ASSIST.ANY + OTHER_ASSISTS.ANY)", "MetricExpr": "INST_RETIRED.ANY / (FP_ASSIST.ANY + OTHER_ASSISTS.ANY)",
...@@ -1304,13 +1230,13 @@ ...@@ -1304,13 +1230,13 @@
}, },
{ {
"BriefDescription": "Average CPU Utilization (percentage)", "BriefDescription": "Average CPU Utilization (percentage)",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online",
"MetricGroup": "HPC;Summary", "MetricGroup": "HPC;Summary",
"MetricName": "tma_info_system_cpu_utilization" "MetricName": "tma_info_system_cpu_utilization"
}, },
{ {
"BriefDescription": "Average number of utilized CPUs", "BriefDescription": "Average number of utilized CPUs",
"MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "Summary", "MetricGroup": "Summary",
"MetricName": "tma_info_system_cpus_utilized" "MetricName": "tma_info_system_cpus_utilized"
}, },
...@@ -1470,7 +1396,7 @@ ...@@ -1470,7 +1396,7 @@
"MetricThreshold": "tma_info_thread_uoppi > 1.05" "MetricThreshold": "tma_info_thread_uoppi > 1.05"
}, },
{ {
"BriefDescription": "Instruction per taken branch", "BriefDescription": "Uops per taken branch",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW", "MetricGroup": "Branches;Fed;FetchBW",
"MetricName": "tma_info_thread_uptb", "MetricName": "tma_info_thread_uptb",
...@@ -1479,7 +1405,7 @@ ...@@ -1479,7 +1405,7 @@
{ {
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
"MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks", "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks",
"MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
"MetricName": "tma_itlb_misses", "MetricName": "tma_itlb_misses",
"MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
...@@ -1494,11 +1420,20 @@ ...@@ -1494,11 +1420,20 @@
"PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1",
"ScaleUnit": "100%" "ScaleUnit": "100%"
}, },
{
"BriefDescription": "This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache",
"MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks",
"MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group",
"MetricName": "tma_l1_hit_latency",
"MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT",
"ScaleUnit": "100%"
},
{ {
"BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks)", "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks)",
"MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
"MetricName": "tma_l2_bound", "MetricName": "tma_l2_bound",
"MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)",
"PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
...@@ -1516,7 +1451,7 @@ ...@@ -1516,7 +1451,7 @@
{ {
"BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
"MetricExpr": "17 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks", "MetricExpr": "17 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks",
"MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency", "MetricName": "tma_l3_hit_latency",
"MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency", "PublicDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency",
...@@ -1528,7 +1463,7 @@ ...@@ -1528,7 +1463,7 @@
"MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB",
"MetricName": "tma_lcp", "MetricName": "tma_lcp",
"MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
"PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb",
"ScaleUnit": "100%" "ScaleUnit": "100%"
}, },
{ {
...@@ -1573,7 +1508,7 @@ ...@@ -1573,7 +1508,7 @@
"MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
"MetricName": "tma_local_mem", "MetricName": "tma_local_mem",
"MetricThreshold": "tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "MetricThreshold": "tma_local_mem > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS", "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
"ScaleUnit": "100%" "ScaleUnit": "100%"
}, },
{ {
...@@ -1582,14 +1517,14 @@ ...@@ -1582,14 +1517,14 @@
"MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group",
"MetricName": "tma_lock_latency", "MetricName": "tma_lock_latency",
"MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency",
"ScaleUnit": "100%" "ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
"MetricConstraint": "NO_GROUP_EVENTS", "MetricConstraint": "NO_GROUP_EVENTS",
"MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
"MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn",
"MetricName": "tma_machine_clears", "MetricName": "tma_machine_clears",
"MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15",
"MetricgroupNoGroup": "TopdownL2", "MetricgroupNoGroup": "TopdownL2",
...@@ -1599,7 +1534,7 @@ ...@@ -1599,7 +1534,7 @@
{ {
"BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM)", "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM)",
"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_thread_clks", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_thread_clks",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW",
"MetricName": "tma_mem_bandwidth", "MetricName": "tma_mem_bandwidth",
"MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full",
...@@ -1608,7 +1543,7 @@ ...@@ -1608,7 +1543,7 @@
{ {
"BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM)", "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM)",
"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat",
"MetricName": "tma_mem_latency", "MetricName": "tma_mem_latency",
"MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_latency", "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_latency",
...@@ -1635,6 +1570,7 @@ ...@@ -1635,6 +1570,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
"MetricConstraint": "NO_GROUP_EVENTS_NMI",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots",
"MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS",
"MetricName": "tma_microcode_sequencer", "MetricName": "tma_microcode_sequencer",
...@@ -1645,7 +1581,7 @@ ...@@ -1645,7 +1581,7 @@
{ {
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM",
"MetricName": "tma_mispredicts_resteers", "MetricName": "tma_mispredicts_resteers",
"MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions", "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions",
...@@ -1681,7 +1617,7 @@ ...@@ -1681,7 +1617,7 @@
{ {
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
"MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS",
"MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
"MetricName": "tma_non_fused_branches", "MetricName": "tma_non_fused_branches",
"MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_operations > 0.6", "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_operations > 0.6",
"PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
...@@ -1690,7 +1626,7 @@ ...@@ -1690,7 +1626,7 @@
{ {
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
"MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS", "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS",
"MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group", "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group",
"MetricName": "tma_nop_instructions", "MetricName": "tma_nop_instructions",
"MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6)", "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6)",
"PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
...@@ -1708,7 +1644,7 @@ ...@@ -1708,7 +1644,7 @@
{ {
"BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).",
"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)", "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)",
"MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group", "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_branch_mispredicts_group",
"MetricName": "tma_other_mispredicts", "MetricName": "tma_other_mispredicts",
"MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15)", "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15)",
"ScaleUnit": "100%" "ScaleUnit": "100%"
...@@ -1716,7 +1652,7 @@ ...@@ -1716,7 +1652,7 @@
{ {
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.",
"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT), 0.0001)", "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT), 0.0001)",
"MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group", "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group",
"MetricName": "tma_other_nukes", "MetricName": "tma_other_nukes",
"MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15)", "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15)",
"ScaleUnit": "100%" "ScaleUnit": "100%"
...@@ -1804,7 +1740,7 @@ ...@@ -1804,7 +1740,7 @@
}, },
{ {
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / tma_info_thread_clks * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks", "MetricExpr": "EXE_ACTIVITY.EXE_BOUND_0_PORTS / tma_info_thread_clks",
"MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_0", "MetricName": "tma_ports_utilized_0",
"MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
...@@ -1832,7 +1768,7 @@ ...@@ -1832,7 +1768,7 @@
{ {
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
"MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_core_clks", "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_core_clks",
"MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_3m", "MetricName": "tma_ports_utilized_3m",
"MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
"ScaleUnit": "100%" "ScaleUnit": "100%"
...@@ -1859,7 +1795,7 @@ ...@@ -1859,7 +1795,7 @@
{ {
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots",
"MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group",
"MetricName": "tma_retiring", "MetricName": "tma_retiring",
"MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1",
"MetricgroupNoGroup": "TopdownL1", "MetricgroupNoGroup": "TopdownL1",
...@@ -1869,7 +1805,7 @@ ...@@ -1869,7 +1805,7 @@
{ {
"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
"MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_thread_clks", "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_thread_clks",
"MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO", "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO",
"MetricName": "tma_serializing_operation", "MetricName": "tma_serializing_operation",
"MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
"PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related metrics: tma_ms_switches",
...@@ -1897,7 +1833,7 @@ ...@@ -1897,7 +1833,7 @@
{ {
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
"MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group",
"MetricName": "tma_sq_full", "MetricName": "tma_sq_full",
"MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth", "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth",
...@@ -1925,7 +1861,7 @@ ...@@ -1925,7 +1861,7 @@
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
"MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricConstraint": "NO_GROUP_EVENTS_NMI",
"MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group",
"MetricName": "tma_store_latency", "MetricName": "tma_store_latency",
"MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency",
...@@ -1958,7 +1894,7 @@ ...@@ -1958,7 +1894,7 @@
{ {
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
"MetricExpr": "9 * BACLEARS.ANY / tma_info_thread_clks", "MetricExpr": "9 * BACLEARS.ANY / tma_info_thread_clks",
"MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
"MetricName": "tma_unknown_branches", "MetricName": "tma_unknown_branches",
"MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY", "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY",
......
tools/perf/pmu-events/arch/x86/skylakex/uncore-cache.json
View file @ 4c10b96f
This source diff could not be displayed because it is too large. You can view the blob instead.
tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.json
View file @ 4c10b96f
This source diff could not be displayed because it is too large. You can view the blob instead.
tools/perf/pmu-events/arch/x86/skylakex/uncore-io.json
View file @ 4c10b96f
This source diff could not be displayed because it is too large. You can view the blob instead.
tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json
View file @ 4c10b96f
This source diff could not be displayed because it is too large. You can view the blob instead.
tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json
View file @ 4c10b96f
[ [
{ {
"BriefDescription": "pclk Cycles", "BriefDescription": "pclk Cycles",
"Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS", "EventName": "UNC_P_CLOCKTICKS",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.", "PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
"Counter": "0,1,2,3",
"EventCode": "0x60", "EventCode": "0x60",
"EventName": "UNC_P_CORE_TRANSITION_CYCLES", "EventName": "UNC_P_CORE_TRANSITION_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "UNC_P_DEMOTIONS", "BriefDescription": "UNC_P_DEMOTIONS",
"Counter": "0,1,2,3",
"EventCode": "0x30", "EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS", "EventName": "UNC_P_DEMOTIONS",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Phase Shed 0 Cycles", "BriefDescription": "Phase Shed 0 Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x75", "EventCode": "0x75",
"EventName": "UNC_P_FIVR_PS_PS0_CYCLES", "EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Cycles spent in phase-shedding power state 0", "PublicDescription": "Cycles spent in phase-shedding power state 0",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Phase Shed 1 Cycles", "BriefDescription": "Phase Shed 1 Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x76", "EventCode": "0x76",
"EventName": "UNC_P_FIVR_PS_PS1_CYCLES", "EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Cycles spent in phase-shedding power state 1", "PublicDescription": "Cycles spent in phase-shedding power state 1",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Phase Shed 2 Cycles", "BriefDescription": "Phase Shed 2 Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x77", "EventCode": "0x77",
"EventName": "UNC_P_FIVR_PS_PS2_CYCLES", "EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Cycles spent in phase-shedding power state 2", "PublicDescription": "Cycles spent in phase-shedding power state 2",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Phase Shed 3 Cycles", "BriefDescription": "Phase Shed 3 Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x78", "EventCode": "0x78",
"EventName": "UNC_P_FIVR_PS_PS3_CYCLES", "EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Cycles spent in phase-shedding power state 3", "PublicDescription": "Cycles spent in phase-shedding power state 3",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Thermal Strongest Upper Limit Cycles", "BriefDescription": "Thermal Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x4", "EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.", "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Power Strongest Upper Limit Cycles", "BriefDescription": "Power Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.", "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles", "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x73", "EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.", "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Cycles spent changing Frequency", "BriefDescription": "Cycles spent changing Frequency",
"Counter": "0,1,2,3",
"EventCode": "0x74", "EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES", "EventName": "UNC_P_FREQ_TRANS_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.", "PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES", "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES",
"Counter": "0,1,2,3",
"EventCode": "0x6", "EventCode": "0x6",
"EventName": "UNC_P_MCP_PROCHOT_CYCLES", "EventName": "UNC_P_MCP_PROCHOT_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Memory Phase Shedding Cycles", "BriefDescription": "Memory Phase Shedding Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x2F", "EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.", "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Package C State Residency - C0", "BriefDescription": "Package C State Residency - C0",
"Counter": "0,1,2,3",
"EventCode": "0x2A", "EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.", "PublicDescription": "Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Package C State Residency - C2E", "BriefDescription": "Package C State Residency - C2E",
"Counter": "0,1,2,3",
"EventCode": "0x2B", "EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.", "PublicDescription": "Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Package C State Residency - C3", "BriefDescription": "Package C State Residency - C3",
"Counter": "0,1,2,3",
"EventCode": "0x2C", "EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.", "PublicDescription": "Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Package C State Residency - C6", "BriefDescription": "Package C State Residency - C6",
"Counter": "0,1,2,3",
"EventCode": "0x2D", "EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.", "PublicDescription": "Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
"Counter": "0,1,2,3",
"EventCode": "0x7", "EventCode": "0x7",
"EventName": "UNC_P_PMAX_THROTTLED_CYCLES", "EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Number of cores in C-State; C0 and C1", "BriefDescription": "Number of cores in C-State; C0 and C1",
"Counter": "0,1,2,3",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"UMask": "0x40", "UMask": "0x40",
...@@ -149,8 +187,10 @@ ...@@ -149,8 +187,10 @@
}, },
{ {
"BriefDescription": "Number of cores in C-State; C3", "BriefDescription": "Number of cores in C-State; C3",
"Counter": "0,1,2,3",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"UMask": "0x80", "UMask": "0x80",
...@@ -158,8 +198,10 @@ ...@@ -158,8 +198,10 @@
}, },
{ {
"BriefDescription": "Number of cores in C-State; C6 and C7", "BriefDescription": "Number of cores in C-State; C6 and C7",
"Counter": "0,1,2,3",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"UMask": "0xc0", "UMask": "0xc0",
...@@ -167,32 +209,40 @@ ...@@ -167,32 +209,40 @@
}, },
{ {
"BriefDescription": "External Prochot", "BriefDescription": "External Prochot",
"Counter": "0,1,2,3",
"EventCode": "0xA", "EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.", "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Internal Prochot", "BriefDescription": "Internal Prochot",
"Counter": "0,1,2,3",
"EventCode": "0x9", "EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", "PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "Total Core C State Transition Cycles", "BriefDescription": "Total Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x72", "EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions across all cores.", "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU" "Unit": "PCU"
}, },
{ {
"BriefDescription": "VR Hot", "BriefDescription": "VR Hot",
"Counter": "0,1,2,3",
"EventCode": "0x42", "EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES", "EventName": "UNC_P_VR_HOT_CYCLES",
"Experimental": "1",
"PerPkg": "1", "PerPkg": "1",
"Unit": "PCU" "Unit": "PCU"
} }
......
tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json
View file @ 4c10b96f
[ [
{ {
"BriefDescription": "Load misses in all DTLB levels that cause page walks", "BriefDescription": "Load misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.", "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
...@@ -9,6 +10,7 @@ ...@@ -9,6 +10,7 @@
}, },
{ {
"BriefDescription": "Loads that miss the DTLB and hit the STLB.", "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
"Counter": "0,1,2,3",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT", "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
...@@ -17,6 +19,7 @@ ...@@ -17,6 +19,7 @@
}, },
{ {
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
...@@ -26,6 +29,7 @@ ...@@ -26,6 +29,7 @@
}, },
{ {
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
"Counter": "0,1,2,3",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
...@@ -34,6 +38,7 @@ ...@@ -34,6 +38,7 @@
}, },
{ {
"BriefDescription": "Page walk completed due to a demand data load to a 1G page", "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
"Counter": "0,1,2,3",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
...@@ -42,6 +47,7 @@ ...@@ -42,6 +47,7 @@
}, },
{ {
"BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
"Counter": "0,1,2,3",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
...@@ -50,6 +56,7 @@ ...@@ -50,6 +56,7 @@
}, },
{ {
"BriefDescription": "Page walk completed due to a demand data load to a 4K page", "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
"Counter": "0,1,2,3",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
...@@ -58,6 +65,7 @@ ...@@ -58,6 +65,7 @@
}, },
{ {
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"EventCode": "0x08", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.", "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
...@@ -66,6 +74,7 @@ ...@@ -66,6 +74,7 @@
}, },
{ {
"BriefDescription": "Store misses in all DTLB levels that cause page walks", "BriefDescription": "Store misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.", "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
...@@ -74,6 +83,7 @@ ...@@ -74,6 +83,7 @@
}, },
{ {
"BriefDescription": "Stores that miss the DTLB and hit the STLB.", "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
"Counter": "0,1,2,3",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT", "EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
...@@ -82,6 +92,7 @@ ...@@ -82,6 +92,7 @@
}, },
{ {
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
...@@ -91,6 +102,7 @@ ...@@ -91,6 +102,7 @@
}, },
{ {
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
"Counter": "0,1,2,3",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
...@@ -99,6 +111,7 @@ ...@@ -99,6 +111,7 @@
}, },
{ {
"BriefDescription": "Page walk completed due to a demand data store to a 1G page", "BriefDescription": "Page walk completed due to a demand data store to a 1G page",
"Counter": "0,1,2,3",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
...@@ -107,6 +120,7 @@ ...@@ -107,6 +120,7 @@
}, },
{ {
"BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page", "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
"Counter": "0,1,2,3",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
...@@ -115,6 +129,7 @@ ...@@ -115,6 +129,7 @@
}, },
{ {
"BriefDescription": "Page walk completed due to a demand data store to a 4K page", "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
"Counter": "0,1,2,3",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
...@@ -123,6 +138,7 @@ ...@@ -123,6 +138,7 @@
}, },
{ {
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"EventCode": "0x49", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING", "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.", "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
...@@ -131,6 +147,7 @@ ...@@ -131,6 +147,7 @@
}, },
{ {
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.", "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
"Counter": "0,1,2,3",
"EventCode": "0x4f", "EventCode": "0x4f",
"EventName": "EPT.WALK_PENDING", "EventName": "EPT.WALK_PENDING",
"PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.", "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
...@@ -139,6 +156,7 @@ ...@@ -139,6 +156,7 @@
}, },
{ {
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"EventCode": "0xAE", "EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH", "EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
...@@ -147,6 +165,7 @@ ...@@ -147,6 +165,7 @@
}, },
{ {
"BriefDescription": "Misses at all ITLB levels that cause page walks", "BriefDescription": "Misses at all ITLB levels that cause page walks",
"Counter": "0,1,2,3",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.", "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
...@@ -155,6 +174,7 @@ ...@@ -155,6 +174,7 @@
}, },
{ {
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
"Counter": "0,1,2,3",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT", "EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
...@@ -162,6 +182,7 @@ ...@@ -162,6 +182,7 @@
}, },
{ {
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.", "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE", "EventName": "ITLB_MISSES.WALK_ACTIVE",
...@@ -171,6 +192,7 @@ ...@@ -171,6 +192,7 @@
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
"Counter": "0,1,2,3",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED", "EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
...@@ -179,6 +201,7 @@ ...@@ -179,6 +201,7 @@
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
...@@ -187,6 +210,7 @@ ...@@ -187,6 +210,7 @@
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"Counter": "0,1,2,3",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
...@@ -195,6 +219,7 @@ ...@@ -195,6 +219,7 @@
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
...@@ -203,6 +228,7 @@ ...@@ -203,6 +228,7 @@
}, },
{ {
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.", "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"EventCode": "0x85", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING", "EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture.", "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture.",
...@@ -211,6 +237,7 @@ ...@@ -211,6 +237,7 @@
}, },
{ {
"BriefDescription": "DTLB flush attempts of the thread-specific entries", "BriefDescription": "DTLB flush attempts of the thread-specific entries",
"Counter": "0,1,2,3",
"EventCode": "0xBD", "EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD", "EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
...@@ -219,6 +246,7 @@ ...@@ -219,6 +246,7 @@
}, },
{ {
"BriefDescription": "STLB flush attempts", "BriefDescription": "STLB flush attempts",
"Counter": "0,1,2,3",
"EventCode": "0xBD", "EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY", "EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7