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Commit 4c12f41a authored by Zhengjun Xing's avatar Zhengjun Xing Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Update events and metrics for alderlake 

Update JSON events and metrics for alderlake to perf.

Based on ADL JSON event list v1.16:

https://github.com/intel/perfmon/tree/main/ADL/events

Generate the event list and metrics with the converter scripts:

https://github.com/intel/perfmon/pull/32Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarXing Zhengjun <zhengjun.xing@linux.intel.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221124031441.110134-4-zhengjun.xing@linux.intel.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
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tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json
View file @ 4c12f41a
...@@ -1287,14 +1287,14 @@ ...@@ -1287,14 +1287,14 @@
}, },
{ {
"BriefDescription": "Average CPU Utilization", "BriefDescription": "Average CPU Utilization",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary", "MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization", "MetricName": "CPU_Utilization",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
"MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time", "MetricExpr": "Turbo_Utilization * TSC / 1000000000 / duration_time",
"MetricGroup": "Power;Summary", "MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency", "MetricName": "Average_Frequency",
"Unit": "cpu_core" "Unit": "cpu_core"
...@@ -1337,18 +1337,25 @@ ...@@ -1337,18 +1337,25 @@
}, },
{ {
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
"MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000", "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1000000 / duration_time / 1000",
"MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use", "MetricName": "DRAM_BW_Use",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
"MetricGroup": "Mem;SoC", "MetricGroup": "Mem;SoC",
"MetricName": "MEM_Parallel_Requests", "MetricName": "MEM_Parallel_Requests",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
"MetricExpr": "UNC_CLOCK.SOCKET",
"MetricGroup": "SoC",
"MetricName": "Socket_CLKS",
"Unit": "cpu_core"
},
{ {
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
...@@ -1356,6 +1363,12 @@ ...@@ -1356,6 +1363,12 @@
"MetricName": "IpFarBranch", "MetricName": "IpFarBranch",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Uncore frequency per die [GHZ]",
"MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
"MetricGroup": "SoC",
"MetricName": "UNCORE_FREQ"
},
{ {
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.",
"MetricExpr": "TOPDOWN_FE_BOUND.ALL / SLOTS", "MetricExpr": "TOPDOWN_FE_BOUND.ALL / SLOTS",
...@@ -1902,7 +1915,7 @@ ...@@ -1902,7 +1915,7 @@
}, },
{ {
"BriefDescription": "Average CPU Utilization", "BriefDescription": "Average CPU Utilization",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricName": "CPU_Utilization", "MetricName": "CPU_Utilization",
"Unit": "cpu_atom" "Unit": "cpu_atom"
}, },
...@@ -1950,62 +1963,72 @@ ...@@ -1950,62 +1963,72 @@
}, },
{ {
"BriefDescription": "C1 residency percent per core", "BriefDescription": "C1 residency percent per core",
"MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C1_Core_Residency" "MetricName": "C1_Core_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C6 residency percent per core", "BriefDescription": "C6 residency percent per core",
"MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C6_Core_Residency" "MetricName": "C6_Core_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C7 residency percent per core", "BriefDescription": "C7 residency percent per core",
"MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C7_Core_Residency" "MetricName": "C7_Core_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C2 residency percent per package", "BriefDescription": "C2 residency percent per package",
"MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C2_Pkg_Residency" "MetricName": "C2_Pkg_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C3 residency percent per package", "BriefDescription": "C3 residency percent per package",
"MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C3_Pkg_Residency" "MetricName": "C3_Pkg_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C6 residency percent per package", "BriefDescription": "C6 residency percent per package",
"MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C6_Pkg_Residency" "MetricName": "C6_Pkg_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C7 residency percent per package", "BriefDescription": "C7 residency percent per package",
"MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C7_Pkg_Residency" "MetricName": "C7_Pkg_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C8 residency percent per package", "BriefDescription": "C8 residency percent per package",
"MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C8_Pkg_Residency" "MetricName": "C8_Pkg_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C9 residency percent per package", "BriefDescription": "C9 residency percent per package",
"MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C9_Pkg_Residency" "MetricName": "C9_Pkg_Residency",
"ScaleUnit": "100%"
}, },
{ {
"BriefDescription": "C10 residency percent per package", "BriefDescription": "C10 residency percent per package",
"MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100", "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C10_Pkg_Residency" "MetricName": "C10_Pkg_Residency",
"ScaleUnit": "100%"
} }
] ]
tools/perf/pmu-events/arch/x86/alderlake/cache.json
View file @ 4c12f41a
[ [
{
"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x41",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x4f",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x38",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x7",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"UMask": "0x80",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.ALL",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
"Speculative": "1",
"UMask": "0x7",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.RSV",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of load uops retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"UMask": "0x81",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of store uops retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"UMask": "0x82",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
"L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"PEBScounters": "0,1",
"SampleAfterValue": "1000003",
"TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
"L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
"PEBScounters": "0,1",
"SampleAfterValue": "1000003",
"TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
"L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
"PEBScounters": "0,1",
"SampleAfterValue": "1000003",
"TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
"L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"PEBScounters": "0,1",
"SampleAfterValue": "1000003",
"TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
"L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"PEBScounters": "0,1",
"SampleAfterValue": "1000003",
"TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
"L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
"PEBScounters": "0,1",
"SampleAfterValue": "1000003",
"TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
"L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
"PEBScounters": "0,1",
"SampleAfterValue": "1000003",
"TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
"L1_Hit_Indication": "1",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"PEBScounters": "0,1",
"SampleAfterValue": "1000003",
"TakenAlone": "1",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of retired split load uops.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"UMask": "0x41",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
"L1_Hit_Indication": "1",
"PEBS": "2",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"UMask": "0x6",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ICACHE",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "L1D.HWPF_MISS", "BriefDescription": "L1D.HWPF_MISS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x51", "EventCode": "0x51",
"EventName": "L1D.HWPF_MISS", "EventName": "L1D.HWPF_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x20", "UMask": "0x20",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x51", "EventCode": "0x51",
"EventName": "L1D.REPLACEMENT", "EventName": "L1D.REPLACEMENT",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x48", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL", "EventName": "L1D_PEND_MISS.FB_FULL",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.", "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0x48", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS", "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS",
"CollectPEBSRecord": "2", "Deprecated": "1",
"Counter": "0,1,2,3",
"EventCode": "0x48", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALL", "EventName": "L1D_PEND_MISS.L2_STALL",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x48", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALLS", "EventName": "L1D_PEND_MISS.L2_STALLS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of L1D misses that are outstanding", "BriefDescription": "Number of L1D misses that are outstanding",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x48", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING", "EventName": "L1D_PEND_MISS.PENDING",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles with L1D load Misses outstanding.", "BriefDescription": "Cycles with L1D load Misses outstanding.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x48", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES", "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "L2 cache lines filling L2", "BriefDescription": "L2 cache lines filling L2",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x25", "EventCode": "0x25",
"EventName": "L2_LINES_IN.ALL", "EventName": "L2_LINES_IN.ALL",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1f", "UMask": "0x1f",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x26", "EventCode": "0x26",
"EventName": "L2_LINES_OUT.USELESS_HWPF", "EventName": "L2_LINES_OUT.USELESS_HWPF",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]", "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_REQUEST.ALL", "EventName": "L2_REQUEST.ALL",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.REFERENCES]",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0xff", "UMask": "0xff",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]", "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_REQUEST.MISS", "EventName": "L2_REQUEST.MISS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.MISS]",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x3f", "UMask": "0x3f",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "L2 code requests", "BriefDescription": "L2 code requests",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD", "EventName": "L2_RQSTS.ALL_CODE_RD",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of L2 code requests.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0xe4", "UMask": "0xe4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Demand Data Read access L2 cache", "BriefDescription": "Demand Data Read access L2 cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0xe1", "UMask": "0xe1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Demand requests that miss L2 cache", "BriefDescription": "Demand requests that miss L2 cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS", "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts demand requests that miss L2 cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x27", "UMask": "0x27",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "L2_RQSTS.ALL_HWPF", "BriefDescription": "L2_RQSTS.ALL_HWPF",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_HWPF", "EventName": "L2_RQSTS.ALL_HWPF",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0xf0", "UMask": "0xf0",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "RFO requests to L2 cache.", "BriefDescription": "RFO requests to L2 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO", "EventName": "L2_RQSTS.ALL_RFO",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0xe2", "UMask": "0xe2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "L2 cache hits when fetching instructions, code reads.", "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT", "EventName": "L2_RQSTS.CODE_RD_HIT",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0xc4", "UMask": "0xc4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "L2 cache misses when fetching instructions", "BriefDescription": "L2 cache misses when fetching instructions",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS", "EventName": "L2_RQSTS.CODE_RD_MISS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts L2 cache misses when fetching instructions.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x24", "UMask": "0x24",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Demand Data Read requests that hit L2 cache", "BriefDescription": "Demand Data Read requests that hit L2 cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0xc1", "UMask": "0xc1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Demand Data Read miss L2 cache", "BriefDescription": "Demand Data Read miss L2 cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x21", "UMask": "0x21",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "L2_RQSTS.HWPF_MISS", "BriefDescription": "L2_RQSTS.HWPF_MISS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.HWPF_MISS", "EventName": "L2_RQSTS.HWPF_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x30", "UMask": "0x30",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]", "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.MISS", "EventName": "L2_RQSTS.MISS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.MISS]",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x3f", "UMask": "0x3f",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]", "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]",
"CollectPEBSRecord": "2", "EventCode": "0x24",
"Counter": "0,1,2,3", "EventName": "L2_RQSTS.REFERENCES",
"EventCode": "0x24", "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.ALL]",
"EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200003",
"PEBScounters": "0,1,2,3", "UMask": "0xff",
"Unit": "cpu_core"
},
{
"BriefDescription": "RFO requests that hit L2 cache.",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0xc2",
"Unit": "cpu_core"
},
{
"BriefDescription": "RFO requests that miss L2 cache",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x22",
"Unit": "cpu_core"
},
{
"BriefDescription": "SW prefetch requests that hit L2 cache.",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
"UMask": "0xc8",
"Unit": "cpu_core"
},
{
"BriefDescription": "SW prefetch requests that miss L2 cache.",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
"UMask": "0x28",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x41",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
"SampleAfterValue": "100003",
"UMask": "0x41",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x4f",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
"SampleAfterValue": "100003",
"UMask": "0x4f",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
"SampleAfterValue": "200003",
"UMask": "0x38",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1", "UMask": "0x20",
"UMask": "0xff", "Unit": "cpu_atom"
"Unit": "cpu_core"
}, },
{ {
"BriefDescription": "RFO requests that hit L2 cache.", "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
"CollectPEBSRecord": "2", "EventCode": "0x34",
"Counter": "0,1,2,3", "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
"EventCode": "0x24", "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
"EventName": "L2_RQSTS.RFO_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1", "UMask": "0x8",
"UMask": "0xc2", "Unit": "cpu_atom"
"Unit": "cpu_core"
}, },
{ {
"BriefDescription": "RFO requests that miss L2 cache", "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
"CollectPEBSRecord": "2", "EventCode": "0x34",
"Counter": "0,1,2,3", "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
"EventCode": "0x24", "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
"EventName": "L2_RQSTS.RFO_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1", "UMask": "0x10",
"UMask": "0x22", "Unit": "cpu_atom"
"Unit": "cpu_core"
}, },
{ {
"BriefDescription": "SW prefetch requests that hit L2 cache.", "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
"CollectPEBSRecord": "2", "EventCode": "0x34",
"Counter": "0,1,2,3", "EventName": "MEM_BOUND_STALLS.LOAD",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1", "UMask": "0x7",
"UMask": "0xc8", "Unit": "cpu_atom"
"Unit": "cpu_core"
}, },
{ {
"BriefDescription": "SW prefetch requests that miss L2 cache.", "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
"CollectPEBSRecord": "2", "EventCode": "0x34",
"Counter": "0,1,2,3", "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1", "UMask": "0x4",
"UMask": "0x28", "Unit": "cpu_atom"
"Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
"CollectPEBSRecord": "2", "EventCode": "0x34",
"Counter": "0,1,2,3,4,5,6,7", "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
"EventCode": "0x2e", "SampleAfterValue": "200003",
"EventName": "LONGEST_LAT_CACHE.MISS", "UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7", "Unit": "cpu_atom"
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x41",
"Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
"CollectPEBSRecord": "2", "EventCode": "0x34",
"Counter": "0,1,2,3,4,5,6,7", "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
"EventCode": "0x2e", "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
"EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200003",
"PEBScounters": "0,1,2,3,4,5,6,7", "UMask": "0x2",
"SampleAfterValue": "100003", "Unit": "cpu_atom"
"Speculative": "1",
"UMask": "0x4f",
"Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired load instructions.", "BriefDescription": "Retired load instructions.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd0", "EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS", "EventName": "MEM_INST_RETIRED.ALL_LOADS",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"UMask": "0x81", "UMask": "0x81",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired store instructions.", "BriefDescription": "Retired store instructions.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd0", "EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_STORES", "EventName": "MEM_INST_RETIRED.ALL_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts all retired store instructions.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"UMask": "0x82", "UMask": "0x82",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "All retired memory instructions.", "BriefDescription": "All retired memory instructions.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd0", "EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ANY", "EventName": "MEM_INST_RETIRED.ANY",
"L1_Hit_Indication": "1",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts all retired memory instructions - loads and stores.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"UMask": "0x83", "UMask": "0x83",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired load instructions with locked access.", "BriefDescription": "Retired load instructions with locked access.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd0", "EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS", "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts retired load instructions with locked access.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"UMask": "0x21", "UMask": "0x21",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired load instructions that split across a cacheline boundary.", "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd0", "EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x41", "UMask": "0x41",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired store instructions that split across a cacheline boundary.", "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd0", "EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES", "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x42", "UMask": "0x42",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired load instructions that miss the STLB.", "BriefDescription": "Retired load instructions that miss the STLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd0", "EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x11", "UMask": "0x11",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired store instructions that miss the STLB.", "BriefDescription": "Retired store instructions that miss the STLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd0", "EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x12", "UMask": "0x12",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Completed demand load uops that miss the L1 d-cache.", "BriefDescription": "Completed demand load uops that miss the L1 d-cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x43", "EventCode": "0x43",
"EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
"PEBScounters": "0,1,2,3", "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0xfd", "UMask": "0xfd",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd2", "EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
"SampleAfterValue": "20011", "SampleAfterValue": "20011",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd2", "EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"SampleAfterValue": "20011", "SampleAfterValue": "20011",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd2", "EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
"SampleAfterValue": "20011",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
"SampleAfterValue": "100003",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
"PEBS": "1",
"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"SampleAfterValue": "20011", "SampleAfterValue": "20011",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
"PEBS": "1",
"PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.",
"SampleAfterValue": "100007",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
"Data_LA": "1",
"EventCode": "0xd4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
"PEBS": "1",
"PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).",
"SampleAfterValue": "100007",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
"PEBS": "1",
"PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
"SampleAfterValue": "100007",
"UMask": "0x40",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
"PEBS": "1",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
"PEBS": "1",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
"SampleAfterValue": "200003",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
"PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
"SampleAfterValue": "200003",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"PEBS": "1",
"PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
"SampleAfterValue": "100021",
"UMask": "0x10",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
"PEBS": "1",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
"SampleAfterValue": "100021",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", "BriefDescription": "Retired load instructions missed L3 cache as data sources",
"CollectPEBSRecord": "2", "Data_LA": "1",
"Counter": "0,1,2,3", "EventCode": "0xd1",
"Data_LA": "1", "EventName": "MEM_LOAD_RETIRED.L3_MISS",
"EventCode": "0xd2", "PEBS": "1",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
"PEBS": "1", "SampleAfterValue": "50021",
"PEBScounters": "0,1,2,3", "UMask": "0x20",
"SampleAfterValue": "20011", "Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x80",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.ALL",
"SampleAfterValue": "20003",
"UMask": "0x7",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
"SampleAfterValue": "20003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.RSV",
"SampleAfterValue": "20003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
"SampleAfterValue": "20003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
"EventCode": "0x44",
"EventName": "MEM_STORE_RETIRED.L2_HIT",
"SampleAfterValue": "200003",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", "BriefDescription": "Counts the number of load uops retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd2", "EventCode": "0xd0",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of load uops retired.",
"SampleAfterValue": "100003", "SampleAfterValue": "200003",
"UMask": "0x8", "UMask": "0x81",
"Unit": "cpu_core" "Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", "BriefDescription": "Counts the number of store uops retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd2", "EventCode": "0xd0",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of store uops retired.",
"SampleAfterValue": "20011", "SampleAfterValue": "200003",
"UMask": "0x2", "UMask": "0x82",
"Unit": "cpu_core" "Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd3", "EventCode": "0xd0",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
"PEBScounters": "0,1,2,3", "MSRIndex": "0x3F6",
"SampleAfterValue": "100007", "MSRValue": "0x80",
"UMask": "0x1", "PEBS": "2",
"Unit": "cpu_core" "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd4", "EventCode": "0xd0",
"EventName": "MEM_LOAD_MISC_RETIRED.UC", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
"PEBS": "1", "MSRIndex": "0x3F6",
"PEBScounters": "0,1,2,3", "MSRValue": "0x10",
"SampleAfterValue": "100007", "PEBS": "2",
"UMask": "0x4", "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"Unit": "cpu_core" "SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd1", "EventCode": "0xd0",
"EventName": "MEM_LOAD_RETIRED.FB_HIT", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
"PEBS": "1", "MSRIndex": "0x3F6",
"PEBScounters": "0,1,2,3", "MSRValue": "0x100",
"SampleAfterValue": "100007", "PEBS": "2",
"UMask": "0x40", "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"Unit": "cpu_core" "SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Retired load instructions with L1 cache hits as data sources", "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd1", "EventCode": "0xd0",
"EventName": "MEM_LOAD_RETIRED.L1_HIT", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
"PEBS": "1", "MSRIndex": "0x3F6",
"PEBScounters": "0,1,2,3", "MSRValue": "0x20",
"PEBS": "2",
"PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"UMask": "0x1", "UMask": "0x5",
"Unit": "cpu_core" "Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Retired load instructions missed L1 cache as data sources", "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd1", "EventCode": "0xd0",
"EventName": "MEM_LOAD_RETIRED.L1_MISS", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
"PEBS": "1", "MSRIndex": "0x3F6",
"PEBScounters": "0,1,2,3", "MSRValue": "0x4",
"SampleAfterValue": "200003", "PEBS": "2",
"UMask": "0x8", "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"Unit": "cpu_core" "SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Retired load instructions with L2 cache hits as data sources", "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd1", "EventCode": "0xd0",
"EventName": "MEM_LOAD_RETIRED.L2_HIT", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
"PEBS": "1", "MSRIndex": "0x3F6",
"PEBScounters": "0,1,2,3", "MSRValue": "0x200",
"SampleAfterValue": "200003", "PEBS": "2",
"UMask": "0x2", "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"Unit": "cpu_core" "SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Retired load instructions missed L2 cache as data sources", "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd1", "EventCode": "0xd0",
"EventName": "MEM_LOAD_RETIRED.L2_MISS", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
"PEBS": "1", "MSRIndex": "0x3F6",
"PEBScounters": "0,1,2,3", "MSRValue": "0x40",
"SampleAfterValue": "100021", "PEBS": "2",
"UMask": "0x10", "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"Unit": "cpu_core" "SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Retired load instructions with L3 cache hits as data sources", "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd1", "EventCode": "0xd0",
"EventName": "MEM_LOAD_RETIRED.L3_HIT", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
"PEBS": "1", "MSRIndex": "0x3F6",
"PEBScounters": "0,1,2,3", "MSRValue": "0x8",
"SampleAfterValue": "100021", "PEBS": "2",
"UMask": "0x4", "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",
"Unit": "cpu_core" "SampleAfterValue": "1000003",
"UMask": "0x5",
"Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Retired load instructions missed L3 cache as data sources", "BriefDescription": "Counts the number of retired split load uops.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xd1", "EventCode": "0xd0",
"EventName": "MEM_LOAD_RETIRED.L3_MISS", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "SampleAfterValue": "200003",
"SampleAfterValue": "50021", "UMask": "0x41",
"UMask": "0x20", "Unit": "cpu_atom"
"Unit": "cpu_core"
}, },
{ {
"BriefDescription": "MEM_STORE_RETIRED.L2_HIT", "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
"CollectPEBSRecord": "2", "Data_LA": "1",
"Counter": "0,1,2,3", "EventCode": "0xd0",
"EventCode": "0x44", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
"EventName": "MEM_STORE_RETIRED.L2_HIT", "PEBS": "2",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.",
"SampleAfterValue": "200003", "SampleAfterValue": "1000003",
"UMask": "0x1", "UMask": "0x6",
"Unit": "cpu_core" "Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Retired memory uops for any access", "BriefDescription": "Retired memory uops for any access",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xe5", "EventCode": "0xe5",
"EventName": "MEM_UOP_RETIRED.ANY", "EventName": "MEM_UOP_RETIRED.ANY",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"UMask": "0x3", "UMask": "0x3",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B", "EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1181,9 +874,28 @@ ...@@ -1181,9 +874,28 @@
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B", "EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1192,9 +904,28 @@ ...@@ -1192,9 +904,28 @@
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B", "EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -1205,139 +936,111 @@ ...@@ -1205,139 +936,111 @@
}, },
{ {
"BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x21", "EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x80", "UMask": "0x80",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Demand and prefetch data reads", "BriefDescription": "Demand and prefetch data reads",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x21", "EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.DATA_RD", "EventName": "OFFCORE_REQUESTS.DATA_RD",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Demand Data Read requests sent to uncore", "BriefDescription": "Demand Data Read requests sent to uncore",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x21", "EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
"CollectPEBSRecord": "2", "Deprecated": "1",
"Counter": "0,1,2,3",
"Errata": "ADL038", "Errata": "ADL038",
"EventCode": "0x20", "EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"Errata": "ADL038", "Errata": "ADL038",
"EventCode": "0x20", "EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.", "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x20", "EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
"PEBScounters": "0,1,2,3", "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Errata": "ADL038", "Errata": "ADL038",
"EventCode": "0x20", "EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of PREFETCHNTA instructions executed.", "BriefDescription": "Number of PREFETCHNTA instructions executed.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x40", "EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.NTA", "EventName": "SW_PREFETCH_ACCESS.NTA",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of PREFETCHW instructions executed.", "BriefDescription": "Number of PREFETCHW instructions executed.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x40", "EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of PREFETCHT0 instructions executed.", "BriefDescription": "Number of PREFETCHT0 instructions executed.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x40", "EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.T0", "EventName": "SW_PREFETCH_ACCESS.T0",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x40", "EventCode": "0x40",
"EventName": "SW_PREFETCH_ACCESS.T1_T2", "EventName": "SW_PREFETCH_ACCESS.T1_T2",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ICACHE",
"SampleAfterValue": "1000003",
"UMask": "0x20",
"Unit": "cpu_atom"
} }
] ]
tools/perf/pmu-events/arch/x86/alderlake/floating-point.json
View file @ 4c12f41a
[ [
{
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "2000003",
"UMask": "0x8",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "ARITH.FPDIV_ACTIVE", "BriefDescription": "ARITH.FPDIV_ACTIVE",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xb0", "EventCode": "0xb0",
"EventName": "ARITH.FPDIV_ACTIVE", "EventName": "ARITH.FPDIV_ACTIVE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts all microcode FP assists.", "BriefDescription": "Counts all microcode FP assists.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1", "EventCode": "0xc1",
"EventName": "ASSISTS.FP", "EventName": "ASSISTS.FP",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts all microcode Floating Point assists.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "ASSISTS.SSE_AVX_MIX", "BriefDescription": "ASSISTS.SSE_AVX_MIX",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1", "EventCode": "0xc1",
"EventName": "ASSISTS.SSE_AVX_MIX", "EventName": "ASSISTS.SSE_AVX_MIX",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x10", "UMask": "0x10",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3", "EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_0", "EventName": "FP_ARITH_DISPATCHED.PORT_0",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3", "EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_1", "EventName": "FP_ARITH_DISPATCHED.PORT_1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5", "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3", "EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_5", "EventName": "FP_ARITH_DISPATCHED.PORT_5",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x10", "UMask": "0x10",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x20", "UMask": "0x20",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
"SampleAfterValue": "20003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x8",
"Unit": "cpu_atom"
} }
] ]
tools/perf/pmu-events/arch/x86/alderlake/frontend.json
View file @ 4c12f41a
[ [
{ {
"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xe6", "EventCode": "0xe6",
"EventName": "BACLEARS.ANY", "EventName": "BACLEARS.ANY",
"PEBScounters": "0,1,2,3,4,5", "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_atom" "Unit": "cpu_atom"
}, },
{
"BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x3",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of instruction cache misses.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Stalls caused by changing prefix length of the instruction.", "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x87", "EventCode": "0x87",
"EventName": "DECODE.LCP", "EventName": "DECODE.LCP",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
"SampleAfterValue": "500009", "SampleAfterValue": "500009",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles the Microcode Sequencer is busy.", "BriefDescription": "Cycles the Microcode Sequencer is busy.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x87", "EventCode": "0x87",
"EventName": "DECODE.MS_BUSY", "EventName": "DECODE.MS_BUSY",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "500009", "SampleAfterValue": "500009",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "DSB-to-MITE switch true penalty cycles.", "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x61", "EventCode": "0x61",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PEBScounters": "0,1,2,3", "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired Instructions who experienced DSB miss.", "BriefDescription": "Retired Instructions who experienced DSB miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x1", "MSRValue": "0x1",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.", "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.DSB_MISS", "EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x11", "MSRValue": "0x11",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired Instructions who experienced iTLB true miss.", "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS", "EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x14", "MSRValue": "0x14",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L1I_MISS", "EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x12", "MSRValue": "0x12",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L2_MISS", "EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x13", "MSRValue": "0x13",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x600106", "MSRValue": "0x600106",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x608006", "MSRValue": "0x608006",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x601006", "MSRValue": "0x601006",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x600206", "MSRValue": "0x600206",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x610006", "MSRValue": "0x610006",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x100206", "MSRValue": "0x100206",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x602006", "MSRValue": "0x602006",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x600406", "MSRValue": "0x600406",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x620006", "MSRValue": "0x620006",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x604006", "MSRValue": "0x604006",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x600806", "MSRValue": "0x600806",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.MS_FLOWS", "EventName": "FRONTEND_RETIRED.MS_FLOWS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x8", "MSRValue": "0x8",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.STLB_MISS", "EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x15", "MSRValue": "0x15",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x17", "MSRValue": "0x17",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x3",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of instruction cache misses.",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "ICACHE_DATA.STALLS", "EventName": "ICACHE_DATA.STALLS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.",
"SampleAfterValue": "500009", "SampleAfterValue": "500009",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x83", "EventCode": "0x83",
"EventName": "ICACHE_TAG.STALLS", "EventName": "ICACHE_TAG.STALLS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY", "EventName": "IDQ.DSB_CYCLES_ANY",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles DSB is delivering optimal number of Uops", "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "6", "CounterMask": "6",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK", "EventName": "IDQ.DSB_CYCLES_OK",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS", "EventName": "IDQ.DSB_UOPS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles MITE is delivering any Uop", "BriefDescription": "Cycles MITE is delivering any Uop",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_ANY", "EventName": "IDQ.MITE_CYCLES_ANY",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles MITE is delivering optimal number of Uops", "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "6", "CounterMask": "6",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_OK", "EventName": "IDQ.MITE_CYCLES_OK",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS", "EventName": "IDQ.MITE_UOPS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES_ANY", "EventName": "IDQ.MS_CYCLES_ANY",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x20", "UMask": "0x20",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of switches from DSB or MITE to the MS", "BriefDescription": "Number of switches from DSB or MITE to the MS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES", "EventName": "IDQ.MS_SWITCHES",
"PEBScounters": "0,1,2,3", "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x20", "UMask": "0x20",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Uops delivered to IDQ while MS is busy", "BriefDescription": "Uops delivered to IDQ while MS is busy",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x79", "EventCode": "0x79",
"EventName": "IDQ.MS_UOPS", "EventName": "IDQ.MS_UOPS",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS).",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x20", "UMask": "0x20",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c", "EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "6", "CounterMask": "6",
"EventCode": "0x9c", "EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x9c", "EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1", "Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
} }
......
tools/perf/pmu-events/arch/x86/alderlake/memory.json
View file @ 4c12f41a
[ [
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
"SampleAfterValue": "1000003",
"UMask": "0x6",
"Unit": "cpu_core"
},
{ {
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.", "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05", "EventCode": "0x05",
"EventName": "LD_HEAD.ANY_AT_RET", "EventName": "LD_HEAD.ANY_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0xff", "UMask": "0xff",
"Unit": "cpu_atom" "Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05", "EventCode": "0x05",
"EventName": "LD_HEAD.L1_BOUND_AT_RET", "EventName": "LD_HEAD.L1_BOUND_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0xf4", "UMask": "0xf4",
"Unit": "cpu_atom" "Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.", "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05", "EventCode": "0x05",
"EventName": "LD_HEAD.OTHER_AT_RET", "EventName": "LD_HEAD.OTHER_AT_RET",
"PEBScounters": "0,1,2,3,4,5", "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0xc0", "UMask": "0xc0",
"Unit": "cpu_atom" "Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.", "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05", "EventCode": "0x05",
"EventName": "LD_HEAD.PGWALK_AT_RET", "EventName": "LD_HEAD.PGWALK_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0xa0", "UMask": "0xa0",
"Unit": "cpu_atom" "Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.", "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05", "EventCode": "0x05",
"EventName": "LD_HEAD.ST_ADDR_AT_RET", "EventName": "LD_HEAD.ST_ADDR_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x84", "UMask": "0x84",
"Unit": "cpu_atom" "Unit": "cpu_atom"
}, },
{ {
"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xc3", "EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003", "SampleAfterValue": "20003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_atom" "Unit": "cpu_atom"
}, },
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x6",
"Unit": "cpu_core"
},
{ {
"BriefDescription": "Number of machine clears due to memory ordering conflicts.", "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3", "EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0x47", "EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "3", "CounterMask": "3",
"EventCode": "0x47", "EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x3", "UMask": "0x3",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "MEMORY_ACTIVITY.STALLS_L2_MISS", "BriefDescription": "MEMORY_ACTIVITY.STALLS_L2_MISS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "5", "CounterMask": "5",
"EventCode": "0x47", "EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x5", "UMask": "0x5",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "MEMORY_ACTIVITY.STALLS_L3_MISS", "BriefDescription": "MEMORY_ACTIVITY.STALLS_L3_MISS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "9", "CounterMask": "9",
"EventCode": "0x47", "EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x9", "UMask": "0x9",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
"CollectPEBSRecord": "2",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x80", "MSRValue": "0x80",
"PEBS": "2", "PEBS": "2",
"PEBScounters": "1,2,3,4,5,6,7", "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "1009", "SampleAfterValue": "1009",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
"CollectPEBSRecord": "2",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x10", "MSRValue": "0x10",
"PEBS": "2", "PEBS": "2",
"PEBScounters": "1,2,3,4,5,6,7", "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "20011", "SampleAfterValue": "20011",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
"CollectPEBSRecord": "2",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x100", "MSRValue": "0x100",
"PEBS": "2", "PEBS": "2",
"PEBScounters": "1,2,3,4,5,6,7", "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "503", "SampleAfterValue": "503",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
"CollectPEBSRecord": "2",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x20", "MSRValue": "0x20",
"PEBS": "2", "PEBS": "2",
"PEBScounters": "1,2,3,4,5,6,7", "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
"CollectPEBSRecord": "2",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x4", "MSRValue": "0x4",
"PEBS": "2", "PEBS": "2",
"PEBScounters": "1,2,3,4,5,6,7", "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
"CollectPEBSRecord": "2",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x200", "MSRValue": "0x200",
"PEBS": "2", "PEBS": "2",
"PEBScounters": "1,2,3,4,5,6,7", "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "101", "SampleAfterValue": "101",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
"CollectPEBSRecord": "2",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x40", "MSRValue": "0x40",
"PEBS": "2", "PEBS": "2",
"PEBScounters": "1,2,3,4,5,6,7", "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "2003", "SampleAfterValue": "2003",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
"CollectPEBSRecord": "2",
"Counter": "1,2,3,4,5,6,7",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x8", "MSRValue": "0x8",
"PEBS": "2", "PEBS": "2",
"PEBScounters": "1,2,3,4,5,6,7", "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "50021", "SampleAfterValue": "50021",
"TakenAlone": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
"CollectPEBSRecord": "2",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xcd", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
"PEBS": "2", "PEBS": "2",
"PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"EventCode": "0x2A,0x2B", "EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -342,9 +237,28 @@ ...@@ -342,9 +237,28 @@
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B", "EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_MISS", "EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -352,5 +266,33 @@ ...@@ -352,5 +266,33 @@
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Demand Data Read requests who miss L3 cache",
"EventCode": "0x21",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"PublicDescription": "Demand Data Read requests who miss L3 cache.",
"SampleAfterValue": "100003",
"UMask": "0x10",
"Unit": "cpu_core"
},
{
"BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
"EventCode": "0x20",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
"PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.",
"SampleAfterValue": "2000003",
"UMask": "0x10",
"Unit": "cpu_core"
} }
] ]
tools/perf/pmu-events/arch/x86/alderlake/other.json
View file @ 4c12f41a
[ [
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.COREWB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10008",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "ASSISTS.HARDWARE", "BriefDescription": "ASSISTS.HARDWARE",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1", "EventCode": "0xc1",
"EventName": "ASSISTS.HARDWARE", "EventName": "ASSISTS.HARDWARE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "ASSISTS.PAGE_FAULT", "BriefDescription": "ASSISTS.PAGE_FAULT",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1", "EventCode": "0xc1",
"EventName": "ASSISTS.PAGE_FAULT", "EventName": "ASSISTS.PAGE_FAULT",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "CORE_POWER.LICENSE_1", "BriefDescription": "CORE_POWER.LICENSE_1",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_1", "EventName": "CORE_POWER.LICENSE_1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "CORE_POWER.LICENSE_2", "BriefDescription": "CORE_POWER.LICENSE_2",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_2", "EventName": "CORE_POWER.LICENSE_2",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "CORE_POWER.LICENSE_3", "BriefDescription": "CORE_POWER.LICENSE_3",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_3", "EventName": "CORE_POWER.LICENSE_3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
"EventCode": "0xB7",
"EventName": "OCR.COREWB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10008",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Counts demand data reads that have any type of response.", "BriefDescription": "Counts demand data reads that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B", "EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -116,7 +71,6 @@ ...@@ -116,7 +71,6 @@
}, },
{ {
"BriefDescription": "Counts demand data reads that were supplied by DRAM.", "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B", "EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.DRAM", "EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -125,9 +79,18 @@ ...@@ -125,9 +79,18 @@
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B", "EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -138,7 +101,16 @@ ...@@ -138,7 +101,16 @@
}, },
{ {
"BriefDescription": "Counts streaming stores that have any type of response.", "BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"EventCode": "0x2A,0x2B", "EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
...@@ -149,68 +121,52 @@ ...@@ -149,68 +121,52 @@
}, },
{ {
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa5", "EventCode": "0xa5",
"EventName": "RS.EMPTY", "EventName": "RS.EMPTY",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x7", "UMask": "0x7",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0xa5", "EventCode": "0xa5",
"EventName": "RS.EMPTY_COUNT", "EventName": "RS.EMPTY_COUNT",
"Invert": "1", "Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x7", "UMask": "0x7",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT", "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"Deprecated": "1",
"EdgeDetect": "1", "EdgeDetect": "1",
"EventCode": "0xa5", "EventCode": "0xa5",
"EventName": "RS_EMPTY.COUNT", "EventName": "RS_EMPTY.COUNT",
"Invert": "1", "Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x7", "UMask": "0x7",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY", "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY",
"CollectPEBSRecord": "2", "Deprecated": "1",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa5", "EventCode": "0xa5",
"EventName": "RS_EMPTY.CYCLES", "EventName": "RS_EMPTY.CYCLES",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x7", "UMask": "0x7",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "XQ.FULL_CYCLES", "BriefDescription": "XQ.FULL_CYCLES",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x2d", "EventCode": "0x2d",
"EventName": "XQ.FULL_CYCLES", "EventName": "XQ.FULL_CYCLES",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1", "UMask": "0x1",
"Unit": "cpu_core" "Unit": "cpu_core"
} }
......
tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
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tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
View file @ 4c12f41a
[ [
{ {
"BriefDescription": "Number of clocks", "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).",
"Counter": "0,1,2,3,4", "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
"CounterType": "PGMABLE",
"EventCode": "0x01",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Incoming VC0 read request", "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
"Counter": "0,1,2,3,4", "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
"CounterType": "PGMABLE",
"EventCode": "0x02",
"EventName": "UNC_M_VC0_REQUESTS_RD",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Incoming VC0 write request", "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).",
"Counter": "0,1,2,3,4", "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
"CounterType": "PGMABLE",
"EventCode": "0x03",
"EventName": "UNC_M_VC0_REQUESTS_WR",
"PerPkg": "1", "PerPkg": "1",
"PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Incoming VC1 read request", "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
"Counter": "0,1,2,3,4", "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
"CounterType": "PGMABLE",
"EventCode": "0x04",
"EventName": "UNC_M_VC1_REQUESTS_RD",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Incoming VC1 write request", "BriefDescription": "ACT command for a read request sent to DRAM",
"Counter": "0,1,2,3,4", "EventCode": "0x24",
"CounterType": "PGMABLE", "EventName": "UNC_M_ACT_COUNT_RD",
"EventCode": "0x05",
"EventName": "UNC_M_VC1_REQUESTS_WR",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Incoming read prefetch request from IA", "BriefDescription": "ACT command sent to DRAM",
"Counter": "0,1,2,3,4", "EventCode": "0x26",
"CounterType": "PGMABLE", "EventName": "UNC_M_ACT_COUNT_TOTAL",
"EventCode": "0x0A",
"EventName": "UNC_M_PREFETCH_RD",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Any Rank at Hot state", "BriefDescription": "ACT command for a write request sent to DRAM",
"Counter": "0,1,2,3,4", "EventCode": "0x25",
"CounterType": "PGMABLE", "EventName": "UNC_M_ACT_COUNT_WR",
"EventCode": "0x19",
"EventName": "UNC_M_DRAM_THERMAL_HOT",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Any Rank at Warm state", "BriefDescription": "Read CAS command sent to DRAM",
"Counter": "0,1,2,3,4", "EventCode": "0x22",
"CounterType": "PGMABLE", "EventName": "UNC_M_CAS_COUNT_RD",
"EventCode": "0x1A",
"EventName": "UNC_M_DRAM_THERMAL_WARM",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "incoming read request page status is Page Hit", "BriefDescription": "Write CAS command sent to DRAM",
"Counter": "0,1,2,3,4", "EventCode": "0x23",
"CounterType": "PGMABLE", "EventName": "UNC_M_CAS_COUNT_WR",
"EventCode": "0x1C", "PerPkg": "1",
"EventName": "UNC_M_DRAM_PAGE_HIT_RD", "Unit": "iMC"
},
{
"BriefDescription": "Number of clocks",
"EventCode": "0x01",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "incoming read request page status is Page Empty", "BriefDescription": "incoming read request page status is Page Empty",
"Counter": "0,1,2,3,4",
"CounterType": "PGMABLE",
"EventCode": "0x1D", "EventCode": "0x1D",
"EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "incoming read request page status is Page Miss", "BriefDescription": "incoming write request page status is Page Empty",
"Counter": "0,1,2,3,4", "EventCode": "0x20",
"CounterType": "PGMABLE", "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR",
"EventCode": "0x1E", "PerPkg": "1",
"EventName": "UNC_M_DRAM_PAGE_MISS_RD", "Unit": "iMC"
},
{
"BriefDescription": "incoming read request page status is Page Hit",
"EventCode": "0x1C",
"EventName": "UNC_M_DRAM_PAGE_HIT_RD",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "incoming write request page status is Page Hit", "BriefDescription": "incoming write request page status is Page Hit",
"Counter": "0,1,2,3,4",
"CounterType": "PGMABLE",
"EventCode": "0x1F", "EventCode": "0x1F",
"EventName": "UNC_M_DRAM_PAGE_HIT_WR", "EventName": "UNC_M_DRAM_PAGE_HIT_WR",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "incoming write request page status is Page Empty", "BriefDescription": "incoming read request page status is Page Miss",
"Counter": "0,1,2,3,4", "EventCode": "0x1E",
"CounterType": "PGMABLE", "EventName": "UNC_M_DRAM_PAGE_MISS_RD",
"EventCode": "0x20",
"EventName": "UNC_M_DRAM_PAGE_EMPTY_WR",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "incoming write request page status is Page Miss", "BriefDescription": "incoming write request page status is Page Miss",
"Counter": "0,1,2,3,4",
"CounterType": "PGMABLE",
"EventCode": "0x21", "EventCode": "0x21",
"EventName": "UNC_M_DRAM_PAGE_MISS_WR", "EventName": "UNC_M_DRAM_PAGE_MISS_WR",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Read CAS command sent to DRAM", "BriefDescription": "Any Rank at Hot state",
"Counter": "0,1,2,3,4", "EventCode": "0x19",
"CounterType": "PGMABLE", "EventName": "UNC_M_DRAM_THERMAL_HOT",
"EventCode": "0x22",
"EventName": "UNC_M_CAS_COUNT_RD",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Write CAS command sent to DRAM",
"Counter": "0,1,2,3,4",
"CounterType": "PGMABLE",
"EventCode": "0x23",
"EventName": "UNC_M_CAS_COUNT_WR",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "ACT command for a read request sent to DRAM", "BriefDescription": "Any Rank at Warm state",
"Counter": "0,1,2,3,4", "EventCode": "0x1A",
"CounterType": "PGMABLE", "EventName": "UNC_M_DRAM_THERMAL_WARM",
"EventCode": "0x24",
"EventName": "UNC_M_ACT_COUNT_RD",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "ACT command for a write request sent to DRAM", "BriefDescription": "Incoming read prefetch request from IA.",
"Counter": "0,1,2,3,4", "EventCode": "0x0A",
"CounterType": "PGMABLE", "EventName": "UNC_M_PREFETCH_RD",
"EventCode": "0x25",
"EventName": "UNC_M_ACT_COUNT_WR",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "ACT command sent to DRAM", "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration",
"Counter": "0,1,2,3,4", "EventCode": "0x28",
"CounterType": "PGMABLE", "EventName": "UNC_M_PRE_COUNT_IDLE",
"EventCode": "0x26",
"EventName": "UNC_M_ACT_COUNT_TOTAL",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "PRE command sent to DRAM for a read/write request", "BriefDescription": "PRE command sent to DRAM for a read/write request",
"Counter": "0,1,2,3,4",
"CounterType": "PGMABLE",
"EventCode": "0x27", "EventCode": "0x27",
"EventName": "UNC_M_PRE_COUNT_PAGE_MISS", "EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", "BriefDescription": "Incoming VC0 read request",
"Counter": "0,1,2,3,4", "EventCode": "0x02",
"CounterType": "PGMABLE", "EventName": "UNC_M_VC0_REQUESTS_RD",
"EventCode": "0x28",
"EventName": "UNC_M_PRE_COUNT_IDLE",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels)",
"CounterType": "FREERUN",
"EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels)", "BriefDescription": "Incoming VC0 write request",
"Counter": "3", "EventCode": "0x03",
"CounterType": "FREERUN", "EventName": "UNC_M_VC0_REQUESTS_WR",
"EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM", "BriefDescription": "Incoming VC1 read request",
"Counter": "1", "EventCode": "0x04",
"CounterType": "FREERUN", "EventName": "UNC_M_VC1_REQUESTS_RD",
"EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
}, },
{ {
"BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM", "BriefDescription": "Incoming VC1 write request",
"Counter": "4", "EventCode": "0x05",
"CounterType": "FREERUN", "EventName": "UNC_M_VC1_REQUESTS_WR",
"EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
"PerPkg": "1", "PerPkg": "1",
"Unit": "iMC" "Unit": "iMC"
} }
......
tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json
View file @ 4c12f41a
[ [
{ {
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", "BriefDescription": "Number of requests allocated in Coherency Tracker.",
"Counter": "Fixed", "EventCode": "0x84",
"CounterType": "PGMABLE", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1", "PerPkg": "1",
"Unit": "CLOCK" "UMask": "0x1",
"Unit": "ARB"
}, },
{ {
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC", "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
"Counter": "0,1", "EventCode": "0x85",
"CounterType": "PGMABLE", "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
"EventCode": "0x85",
"EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Number of coherent read requests sent to memory controller that were issued by any core.",
"EventCode": "0x81", "EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL", "EventName": "UNC_ARB_DAT_REQUESTS.RD",
"PerPkg": "1", "PerPkg": "1",
"UMask": "0x01", "UMask": "0x2",
"Unit": "ARB" "Unit": "ARB"
}, },
{ {
"BriefDescription": "Number of requests allocated in Coherency Tracker", "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
"Counter": "0,1", "EventCode": "0x85",
"CounterType": "PGMABLE", "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1", "PerPkg": "1",
"UMask": "0x01", "UMask": "0x1",
"Unit": "ARB" "Unit": "ARB"
}, },
{ {
"BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic", "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_REQUESTS.RD",
"CounterType": "PGMABLE", "EventCode": "0x81",
"EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1", "PerPkg": "1",
"UMask": "0x01", "UMask": "0x1",
"Unit": "ARB" "Unit": "ARB"
},
{
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",
"Unit": "CLOCK"
} }
] ]
tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json
View file @ 4c12f41a
[ [
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSED_WALK",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.PDE_CACHE_MISS",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x80",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.DTLB_MISS_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x90",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Loads that miss the DTLB and hit the STLB.", "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x12", "EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT", "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x20", "UMask": "0x20",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x12", "EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10", "UMask": "0x10",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x12", "EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0xe", "UMask": "0xe",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Page walks completed due to a demand data load to a 1G page.", "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x12", "EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x12", "EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.", "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x12", "EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x12", "EventCode": "0x12",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10", "UMask": "0x10",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Stores that miss the DTLB and hit the STLB.", "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13", "EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.STLB_HIT", "EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x20", "UMask": "0x20",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x13", "EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10", "UMask": "0x10",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0xe",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13", "EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0xe", "UMask": "0xe",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Page walks completed due to a demand data store to a 1G page.", "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13", "EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x8", "UMask": "0x8",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13", "EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.", "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13", "EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13", "EventCode": "0x13",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING", "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10", "UMask": "0x10",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSED_WALK",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.PDE_CACHE_MISS",
"SampleAfterValue": "2000003",
"UMask": "0x80",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x11", "EventCode": "0x11",
"EventName": "ITLB_MISSES.STLB_HIT", "EventName": "ITLB_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x20", "UMask": "0x20",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x11", "EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_ACTIVE", "EventName": "ITLB_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10", "UMask": "0x10",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe",
"Unit": "cpu_atom"
},
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x11", "EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED", "EventName": "ITLB_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0xe", "UMask": "0xe",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x11", "EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4", "UMask": "0x4",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x11", "EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2", "UMask": "0x2",
"Unit": "cpu_core" "Unit": "cpu_core"
}, },
{ {
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x11", "EventCode": "0x11",
"EventName": "ITLB_MISSES.WALK_PENDING", "EventName": "ITLB_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10", "UMask": "0x10",
"Unit": "cpu_core" "Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
"EventCode": "0x05",
"EventName": "LD_HEAD.DTLB_MISS_AT_RET",
"SampleAfterValue": "1000003",
"UMask": "0x90",
"Unit": "cpu_atom"
} }
] ]
tools/perf/pmu-events/arch/x86/mapfile.csv
View file @ 4c12f41a
Family-model,Version,Filename,EventType Family-model,Version,Filename,EventType
GenuineIntel-6-(97|9A|B7|BA|BF),v1.15,alderlake,core GenuineIntel-6-(97|9A|B7|BA|BF),v1.16,alderlake,core
GenuineIntel-6-BE,v1.16,alderlaken,core GenuineIntel-6-BE,v1.16,alderlaken,core
GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-(3D|47),v26,broadwell,core
......
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