Commit 4c33f83a authored by Anjali Singhai Jain's avatar Anjali Singhai Jain Committed by Jeff Kirsher

i40e/i40evf: i40e_register.h update

This updates the register file for new hardware.
The format of the file has changed requiring drivers to
declare I40E_MASK. I40E_MASK is to be used with 32 bit registers.

This patch also updates the drivers to accommodate the register changes.

Change-ID: If9bc8d736391024cbf99054efe50f9acc12ee4f1
Signed-off-by: default avatarAnjali Singhai Jain <anjali.singhai@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent e0f802fb
...@@ -5744,26 +5744,28 @@ static void i40e_handle_mdd_event(struct i40e_pf *pf) ...@@ -5744,26 +5744,28 @@ static void i40e_handle_mdd_event(struct i40e_pf *pf)
/* find what triggered the MDD event */ /* find what triggered the MDD event */
reg = rd32(hw, I40E_GL_MDET_TX); reg = rd32(hw, I40E_GL_MDET_TX);
if (reg & I40E_GL_MDET_TX_VALID_MASK) { if (reg & I40E_GL_MDET_TX_VALID_MASK) {
u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK) u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
>> I40E_GL_MDET_TX_FUNCTION_SHIFT; I40E_GL_MDET_TX_PF_NUM_SHIFT;
u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT) u8 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
>> I40E_GL_MDET_TX_EVENT_SHIFT; I40E_GL_MDET_TX_VF_NUM_SHIFT;
u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT) >>
>> I40E_GL_MDET_TX_QUEUE_SHIFT; I40E_GL_MDET_TX_EVENT_SHIFT;
u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
I40E_GL_MDET_TX_QUEUE_SHIFT;
dev_info(&pf->pdev->dev, dev_info(&pf->pdev->dev,
"Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n", "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
event, queue, func); event, queue, pf_num, vf_num);
wr32(hw, I40E_GL_MDET_TX, 0xffffffff); wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
mdd_detected = true; mdd_detected = true;
} }
reg = rd32(hw, I40E_GL_MDET_RX); reg = rd32(hw, I40E_GL_MDET_RX);
if (reg & I40E_GL_MDET_RX_VALID_MASK) { if (reg & I40E_GL_MDET_RX_VALID_MASK) {
u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
>> I40E_GL_MDET_RX_FUNCTION_SHIFT; I40E_GL_MDET_RX_FUNCTION_SHIFT;
u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT) u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT) >>
>> I40E_GL_MDET_RX_EVENT_SHIFT; I40E_GL_MDET_RX_EVENT_SHIFT;
u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
>> I40E_GL_MDET_RX_QUEUE_SHIFT; I40E_GL_MDET_RX_QUEUE_SHIFT;
dev_info(&pf->pdev->dev, dev_info(&pf->pdev->dev,
"Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n", "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
event, queue, func); event, queue, func);
......
This source diff could not be displayed because it is too large. You can view the blob instead.
...@@ -50,6 +50,9 @@ ...@@ -50,6 +50,9 @@
(d) == I40E_DEV_ID_QSFP_B || \ (d) == I40E_DEV_ID_QSFP_B || \
(d) == I40E_DEV_ID_QSFP_C) (d) == I40E_DEV_ID_QSFP_C)
/* I40E_MASK is a macro used on 32 bit registers */
#define I40E_MASK(mask, shift) (mask << shift)
#define I40E_MAX_VSI_QP 16 #define I40E_MAX_VSI_QP 16
#define I40E_MAX_VF_VSI 3 #define I40E_MAX_VF_VSI 3
#define I40E_MAX_CHAINED_RX_BUFFERS 5 #define I40E_MAX_CHAINED_RX_BUFFERS 5
......
This source diff could not be displayed because it is too large. You can view the blob instead.
...@@ -50,6 +50,9 @@ ...@@ -50,6 +50,9 @@
(d) == I40E_DEV_ID_QSFP_B || \ (d) == I40E_DEV_ID_QSFP_B || \
(d) == I40E_DEV_ID_QSFP_C) (d) == I40E_DEV_ID_QSFP_C)
/* I40E_MASK is a macro used on 32 bit registers */
#define I40E_MASK(mask, shift) (mask << shift)
#define I40E_MAX_VSI_QP 16 #define I40E_MAX_VSI_QP 16
#define I40E_MAX_VF_VSI 3 #define I40E_MAX_VF_VSI 3
#define I40E_MAX_CHAINED_RX_BUFFERS 5 #define I40E_MAX_CHAINED_RX_BUFFERS 5
......
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