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Commit 4c5de09e authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by David S. Miller
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net: ethernet: mtk_wed: add configure wed wo support 

Enable RX Wireless Ethernet Dispatch available on MT7986 Soc.
Tested-by: default avatarDaniel Golle <daniel@makrotopia.org>
Co-developed-by: default avatarSujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: default avatarSujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 084d60ce
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Inline Side-by-side
Showing with 842 additions and 54 deletions
drivers/net/ethernet/mediatek/mtk_wed.c
View file @ 4c5de09e
This diff is collapsed.
drivers/net/ethernet/mediatek/mtk_wed.h
View file @ 4c5de09e
...@@ -86,6 +86,24 @@ wpdma_tx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val) ...@@ -86,6 +86,24 @@ wpdma_tx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)
writel(val, dev->tx_ring[ring].wpdma + reg); writel(val, dev->tx_ring[ring].wpdma + reg);
} }
static inline u32
wpdma_rx_r32(struct mtk_wed_device *dev, int ring, u32 reg)
{
if (!dev->rx_ring[ring].wpdma)
return 0;
return readl(dev->rx_ring[ring].wpdma + reg);
}
static inline void
wpdma_rx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)
{
if (!dev->rx_ring[ring].wpdma)
return;
writel(val, dev->rx_ring[ring].wpdma + reg);
}
static inline u32 static inline u32
wpdma_txfree_r32(struct mtk_wed_device *dev, u32 reg) wpdma_txfree_r32(struct mtk_wed_device *dev, u32 reg)
{ {
...@@ -128,6 +146,7 @@ static inline int mtk_wed_flow_add(int index) ...@@ -128,6 +146,7 @@ static inline int mtk_wed_flow_add(int index)
static inline void mtk_wed_flow_remove(int index) static inline void mtk_wed_flow_remove(int index)
{ {
} }
#endif #endif
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
......
drivers/net/ethernet/mediatek/mtk_wed_mcu.c
View file @ 4c5de09e
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#include <linux/of_reserved_mem.h> #include <linux/of_reserved_mem.h>
#include <linux/mfd/syscon.h> #include <linux/mfd/syscon.h>
#include <linux/soc/mediatek/mtk_wed.h> #include <linux/soc/mediatek/mtk_wed.h>
#include <asm/unaligned.h>
#include "mtk_wed_regs.h" #include "mtk_wed_regs.h"
#include "mtk_wed_wo.h" #include "mtk_wed_wo.h"
...@@ -60,24 +61,37 @@ void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb) ...@@ -60,24 +61,37 @@ void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb)
wake_up(&wo->mcu.wait); wake_up(&wo->mcu.wait);
} }
static void
mtk_wed_update_rx_stats(struct mtk_wed_device *wed, struct sk_buff *skb)
{
u32 count = get_unaligned_le32(skb->data);
struct mtk_wed_wo_rx_stats *stats;
int i;
if (count * sizeof(*stats) > skb->len - sizeof(u32))
return;
stats = (struct mtk_wed_wo_rx_stats *)(skb->data + sizeof(u32));
for (i = 0 ; i < count ; i++)
wed->wlan.update_wo_rx_stats(wed, &stats[i]);
}
void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo, void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
struct sk_buff *skb) struct sk_buff *skb)
{ {
struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data; struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
switch (hdr->cmd) { skb_pull(skb, sizeof(*hdr));
case MTK_WED_WO_EVT_LOG_DUMP: {
const char *msg = (const char *)(skb->data + sizeof(*hdr));
dev_notice(wo->hw->dev, "%s\n", msg); switch (hdr->cmd) {
case MTK_WED_WO_EVT_LOG_DUMP:
dev_notice(wo->hw->dev, "%s\n", skb->data);
break; break;
}
case MTK_WED_WO_EVT_PROFILING: { case MTK_WED_WO_EVT_PROFILING: {
struct mtk_wed_wo_log_info *info; struct mtk_wed_wo_log_info *info = (void *)skb->data;
u32 count = (skb->len - sizeof(*hdr)) / sizeof(*info); u32 count = skb->len / sizeof(*info);
int i; int i;
info = (struct mtk_wed_wo_log_info *)(skb->data + sizeof(*hdr));
for (i = 0 ; i < count ; i++) for (i = 0 ; i < count ; i++)
dev_notice(wo->hw->dev, dev_notice(wo->hw->dev,
"SN:%u latency: total=%u, rro:%u, mod:%u\n", "SN:%u latency: total=%u, rro:%u, mod:%u\n",
...@@ -88,6 +102,7 @@ void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo, ...@@ -88,6 +102,7 @@ void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
break; break;
} }
case MTK_WED_WO_EVT_RXCNT_INFO: case MTK_WED_WO_EVT_RXCNT_INFO:
mtk_wed_update_rx_stats(wo->hw->wed_dev, skb);
break; break;
default: default:
break; break;
...@@ -144,6 +159,8 @@ mtk_wed_mcu_parse_response(struct mtk_wed_wo *wo, struct sk_buff *skb, ...@@ -144,6 +159,8 @@ mtk_wed_mcu_parse_response(struct mtk_wed_wo *wo, struct sk_buff *skb,
skb_pull(skb, sizeof(*hdr)); skb_pull(skb, sizeof(*hdr));
switch (cmd) { switch (cmd) {
case MTK_WED_WO_CMD_RXCNT_INFO: case MTK_WED_WO_CMD_RXCNT_INFO:
mtk_wed_update_rx_stats(wo->hw->wed_dev, skb);
break;
default: default:
break; break;
} }
...@@ -182,6 +199,18 @@ int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd, ...@@ -182,6 +199,18 @@ int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
return ret; return ret;
} }
int mtk_wed_mcu_msg_update(struct mtk_wed_device *dev, int id, void *data,
int len)
{
struct mtk_wed_wo *wo = dev->hw->wed_wo;
if (dev->hw->version == 1)
return 0;
return mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO, id, data, len,
true);
}
static int static int
mtk_wed_get_memory_region(struct mtk_wed_wo *wo, mtk_wed_get_memory_region(struct mtk_wed_wo *wo,
struct mtk_wed_wo_memory_region *region) struct mtk_wed_wo_memory_region *region)
......
drivers/net/ethernet/mediatek/mtk_wed_regs.h
View file @ 4c5de09e
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
#ifndef __MTK_WED_REGS_H #ifndef __MTK_WED_REGS_H
#define __MTK_WED_REGS_H #define __MTK_WED_REGS_H
#define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8)
#define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0) #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)
#define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0) #define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0)
#define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15) #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
...@@ -28,6 +29,8 @@ struct mtk_wdma_desc { ...@@ -28,6 +29,8 @@ struct mtk_wdma_desc {
#define MTK_WED_RESET_WED_TX_DMA BIT(12) #define MTK_WED_RESET_WED_TX_DMA BIT(12)
#define MTK_WED_RESET_WDMA_RX_DRV BIT(17) #define MTK_WED_RESET_WDMA_RX_DRV BIT(17)
#define MTK_WED_RESET_WDMA_INT_AGENT BIT(19) #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
#define MTK_WED_RESET_RX_RRO_QM BIT(20)
#define MTK_WED_RESET_RX_ROUTE_QM BIT(21)
#define MTK_WED_RESET_WED BIT(31) #define MTK_WED_RESET_WED BIT(31)
#define MTK_WED_CTRL 0x00c #define MTK_WED_CTRL 0x00c
...@@ -39,8 +42,12 @@ struct mtk_wdma_desc { ...@@ -39,8 +42,12 @@ struct mtk_wdma_desc {
#define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9) #define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9)
#define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10) #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10)
#define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY BIT(11) #define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY BIT(11)
#define MTK_WED_CTRL_RESERVE_EN BIT(12) #define MTK_WED_CTRL_WED_RX_BM_EN BIT(12)
#define MTK_WED_CTRL_RESERVE_BUSY BIT(13) #define MTK_WED_CTRL_WED_RX_BM_BUSY BIT(13)
#define MTK_WED_CTRL_RX_RRO_QM_EN BIT(14)
#define MTK_WED_CTRL_RX_RRO_QM_BUSY BIT(15)
#define MTK_WED_CTRL_RX_ROUTE_QM_EN BIT(16)
#define MTK_WED_CTRL_RX_ROUTE_QM_BUSY BIT(17)
#define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24) #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
#define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25) #define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25)
#define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28) #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
...@@ -62,6 +69,9 @@ struct mtk_wdma_desc { ...@@ -62,6 +69,9 @@ struct mtk_wdma_desc {
#define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22) #define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22)
#define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23) #define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23)
#define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24) #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24)
#define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25)
#define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26)
#define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27)
#define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \ #define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \
MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \ MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \
MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \ MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \
...@@ -71,6 +81,8 @@ struct mtk_wdma_desc { ...@@ -71,6 +81,8 @@ struct mtk_wdma_desc {
MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR) MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR)
#define MTK_WED_EXT_INT_MASK 0x028 #define MTK_WED_EXT_INT_MASK 0x028
#define MTK_WED_EXT_INT_MASK1 0x02c
#define MTK_WED_EXT_INT_MASK2 0x030
#define MTK_WED_STATUS 0x060 #define MTK_WED_STATUS 0x060
#define MTK_WED_STATUS_TX GENMASK(15, 8) #define MTK_WED_STATUS_TX GENMASK(15, 8)
...@@ -151,6 +163,7 @@ struct mtk_wdma_desc { ...@@ -151,6 +163,7 @@ struct mtk_wdma_desc {
#define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10) #define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10)
#define MTK_WED_RING_RX(_n) (0x400 + (_n) * 0x10) #define MTK_WED_RING_RX(_n) (0x400 + (_n) * 0x10)
#define MTK_WED_RING_RX_DATA(_n) (0x420 + (_n) * 0x10)
#define MTK_WED_SCR0 0x3c0 #define MTK_WED_SCR0 0x3c0
#define MTK_WED_WPDMA_INT_TRIGGER 0x504 #define MTK_WED_WPDMA_INT_TRIGGER 0x504
...@@ -213,6 +226,12 @@ struct mtk_wdma_desc { ...@@ -213,6 +226,12 @@ struct mtk_wdma_desc {
#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG GENMASK(14, 10) #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG GENMASK(14, 10)
#define MTK_WED_WPDMA_INT_CTRL_RX 0x534 #define MTK_WED_WPDMA_INT_CTRL_RX 0x534
#define MTK_WED_WPDMA_INT_CTRL_RX0_EN BIT(0)
#define MTK_WED_WPDMA_INT_CTRL_RX0_CLR BIT(1)
#define MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG GENMASK(6, 2)
#define MTK_WED_WPDMA_INT_CTRL_RX1_EN BIT(8)
#define MTK_WED_WPDMA_INT_CTRL_RX1_CLR BIT(9)
#define MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG GENMASK(14, 10)
#define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538
#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0) #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0)
...@@ -242,11 +261,34 @@ struct mtk_wdma_desc { ...@@ -242,11 +261,34 @@ struct mtk_wdma_desc {
#define MTK_WED_WPDMA_RING_TX(_n) (0x600 + (_n) * 0x10) #define MTK_WED_WPDMA_RING_TX(_n) (0x600 + (_n) * 0x10)
#define MTK_WED_WPDMA_RING_RX(_n) (0x700 + (_n) * 0x10) #define MTK_WED_WPDMA_RING_RX(_n) (0x700 + (_n) * 0x10)
#define MTK_WED_WPDMA_RING_RX_DATA(_n) (0x730 + (_n) * 0x10)
#define MTK_WED_WPDMA_RX_D_GLO_CFG 0x75c
#define MTK_WED_WPDMA_RX_D_RX_DRV_EN BIT(0)
#define MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL GENMASK(11, 7)
#define MTK_WED_WPDMA_RX_D_RXD_READ_LEN GENMASK(31, 24)
#define MTK_WED_WPDMA_RX_D_RST_IDX 0x760
#define MTK_WED_WPDMA_RX_D_RST_CRX_IDX GENMASK(17, 16)
#define MTK_WED_WPDMA_RX_D_RST_DRV_IDX GENMASK(25, 24)
#define MTK_WED_WPDMA_RX_GLO_CFG 0x76c
#define MTK_WED_WPDMA_RX_RING 0x770
#define MTK_WED_WPDMA_RX_D_MIB(_n) (0x774 + (_n) * 4)
#define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n) (0x784 + (_n) * 4)
#define MTK_WED_WPDMA_RX_D_COHERENT_MIB 0x78c
#define MTK_WED_WDMA_RING_TX 0x800
#define MTK_WED_WDMA_TX_MIB 0x810
#define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10) #define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10)
#define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4) #define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4)
#define MTK_WED_WDMA_GLO_CFG 0xa04 #define MTK_WED_WDMA_GLO_CFG 0xa04
#define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0) #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)
#define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK BIT(1)
#define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN BIT(2) #define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN BIT(2)
#define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY BIT(3) #define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
#define MTK_WED_WDMA_GLO_CFG_BT_SIZE GENMASK(5, 4) #define MTK_WED_WDMA_GLO_CFG_BT_SIZE GENMASK(5, 4)
...@@ -291,6 +333,20 @@ struct mtk_wdma_desc { ...@@ -291,6 +333,20 @@ struct mtk_wdma_desc {
#define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4) #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4)
#define MTK_WED_WDMA_RX_PROCESSED_MIB(_n) (0xaf0 + (_n) * 4) #define MTK_WED_WDMA_RX_PROCESSED_MIB(_n) (0xaf0 + (_n) * 4)
#define MTK_WED_RX_BM_RX_DMAD 0xd80
#define MTK_WED_RX_BM_RX_DMAD_SDL0 GENMASK(13, 0)
#define MTK_WED_RX_BM_BASE 0xd84
#define MTK_WED_RX_BM_INIT_PTR 0xd88
#define MTK_WED_RX_BM_SW_TAIL GENMASK(15, 0)
#define MTK_WED_RX_BM_INIT_SW_TAIL BIT(16)
#define MTK_WED_RX_PTR 0xd8c
#define MTK_WED_RX_BM_DYN_ALLOC_TH 0xdb4
#define MTK_WED_RX_BM_DYN_ALLOC_TH_H GENMASK(31, 16)
#define MTK_WED_RX_BM_DYN_ALLOC_TH_L GENMASK(15, 0)
#define MTK_WED_RING_OFS_BASE 0x00 #define MTK_WED_RING_OFS_BASE 0x00
#define MTK_WED_RING_OFS_COUNT 0x04 #define MTK_WED_RING_OFS_COUNT 0x04
#define MTK_WED_RING_OFS_CPU_IDX 0x08 #define MTK_WED_RING_OFS_CPU_IDX 0x08
...@@ -301,7 +357,9 @@ struct mtk_wdma_desc { ...@@ -301,7 +357,9 @@ struct mtk_wdma_desc {
#define MTK_WDMA_GLO_CFG 0x204 #define MTK_WDMA_GLO_CFG 0x204
#define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0) #define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0)
#define MTK_WDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
#define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2) #define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2)
#define MTK_WDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
#define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26) #define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26)
#define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27) #define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)
#define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28) #define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28)
...@@ -330,4 +388,70 @@ struct mtk_wdma_desc { ...@@ -330,4 +388,70 @@ struct mtk_wdma_desc {
/* DMA channel mapping */ /* DMA channel mapping */
#define HIFSYS_DMA_AG_MAP 0x008 #define HIFSYS_DMA_AG_MAP 0x008
#define MTK_WED_RTQM_GLO_CFG 0xb00
#define MTK_WED_RTQM_BUSY BIT(1)
#define MTK_WED_RTQM_Q_RST BIT(2)
#define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5)
#define MTK_WED_RTQM_TXDMAD_FPORT GENMASK(23, 20)
#define MTK_WED_RTQM_R2H_MIB(_n) (0xb70 + (_n) * 0x4)
#define MTK_WED_RTQM_R2Q_MIB(_n) (0xb78 + (_n) * 0x4)
#define MTK_WED_RTQM_Q2N_MIB 0xb80
#define MTK_WED_RTQM_Q2H_MIB(_n) (0xb84 + (_n) * 0x4)
#define MTK_WED_RTQM_Q2B_MIB 0xb8c
#define MTK_WED_RTQM_PFDBK_MIB 0xb90
#define MTK_WED_RROQM_GLO_CFG 0xc04
#define MTK_WED_RROQM_RST_IDX 0xc08
#define MTK_WED_RROQM_RST_IDX_MIOD BIT(0)
#define MTK_WED_RROQM_RST_IDX_FDBK BIT(4)
#define MTK_WED_RROQM_MIOD_CTRL0 0xc40
#define MTK_WED_RROQM_MIOD_CTRL1 0xc44
#define MTK_WED_RROQM_MIOD_CNT GENMASK(11, 0)
#define MTK_WED_RROQM_MIOD_CTRL2 0xc48
#define MTK_WED_RROQM_MIOD_CTRL3 0xc4c
#define MTK_WED_RROQM_FDBK_CTRL0 0xc50
#define MTK_WED_RROQM_FDBK_CTRL1 0xc54
#define MTK_WED_RROQM_FDBK_CNT GENMASK(11, 0)
#define MTK_WED_RROQM_FDBK_CTRL2 0xc58
#define MTK_WED_RROQ_BASE_L 0xc80
#define MTK_WED_RROQ_BASE_H 0xc84
#define MTK_WED_RROQM_MIOD_CFG 0xc8c
#define MTK_WED_RROQM_MIOD_MID_DW GENMASK(5, 0)
#define MTK_WED_RROQM_MIOD_MOD_DW GENMASK(13, 8)
#define MTK_WED_RROQM_MIOD_ENTRY_DW GENMASK(22, 16)
#define MTK_WED_RROQM_MID_MIB 0xcc0
#define MTK_WED_RROQM_MOD_MIB 0xcc4
#define MTK_WED_RROQM_MOD_COHERENT_MIB 0xcc8
#define MTK_WED_RROQM_FDBK_MIB 0xcd0
#define MTK_WED_RROQM_FDBK_COHERENT_MIB 0xcd4
#define MTK_WED_RROQM_FDBK_IND_MIB 0xce0
#define MTK_WED_RROQM_FDBK_ENQ_MIB 0xce4
#define MTK_WED_RROQM_FDBK_ANC_MIB 0xce8
#define MTK_WED_RROQM_FDBK_ANC2H_MIB 0xcec
#define MTK_WED_RX_BM_RX_DMAD 0xd80
#define MTK_WED_RX_BM_BASE 0xd84
#define MTK_WED_RX_BM_INIT_PTR 0xd88
#define MTK_WED_RX_BM_PTR 0xd8c
#define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16)
#define MTK_WED_RX_BM_PTR_TAIL GENMASK(15, 0)
#define MTK_WED_RX_BM_BLEN 0xd90
#define MTK_WED_RX_BM_STS 0xd94
#define MTK_WED_RX_BM_INTF2 0xd98
#define MTK_WED_RX_BM_INTF 0xd9c
#define MTK_WED_RX_BM_ERR_STS 0xda8
#define MTK_WED_WOCPU_VIEW_MIOD_BASE 0x8000
#define MTK_WED_PCIE_INT_MASK 0x0
#endif #endif
drivers/net/ethernet/mediatek/mtk_wed_wo.h
View file @ 4c5de09e
...@@ -49,6 +49,10 @@ enum { ...@@ -49,6 +49,10 @@ enum {
MTK_WED_WARP_CMD_FLAG_FROM_TO_WO = BIT(2), MTK_WED_WARP_CMD_FLAG_FROM_TO_WO = BIT(2),
}; };
#define MTK_WED_WO_CPU_MCUSYS_RESET_ADDR 0x15194050
#define MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK 0x20
#define MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK 0x1
enum { enum {
MTK_WED_WO_REGION_EMI, MTK_WED_WO_REGION_EMI,
MTK_WED_WO_REGION_ILM, MTK_WED_WO_REGION_ILM,
...@@ -57,6 +61,28 @@ enum { ...@@ -57,6 +61,28 @@ enum {
__MTK_WED_WO_REGION_MAX, __MTK_WED_WO_REGION_MAX,
}; };
enum mtk_wed_wo_state {
MTK_WED_WO_STATE_UNDEFINED,
MTK_WED_WO_STATE_INIT,
MTK_WED_WO_STATE_ENABLE,
MTK_WED_WO_STATE_DISABLE,
MTK_WED_WO_STATE_HALT,
MTK_WED_WO_STATE_GATING,
MTK_WED_WO_STATE_SER_RESET,
MTK_WED_WO_STATE_WF_RESET,
};
enum mtk_wed_wo_done_state {
MTK_WED_WOIF_UNDEFINED,
MTK_WED_WOIF_DISABLE_DONE,
MTK_WED_WOIF_TRIGGER_ENABLE,
MTK_WED_WOIF_ENABLE_DONE,
MTK_WED_WOIF_TRIGGER_GATING,
MTK_WED_WOIF_GATING_DONE,
MTK_WED_WOIF_TRIGGER_HALT,
MTK_WED_WOIF_HALT_DONE,
};
enum mtk_wed_dummy_cr_idx { enum mtk_wed_dummy_cr_idx {
MTK_WED_DUMMY_CR_FWDL, MTK_WED_DUMMY_CR_FWDL,
MTK_WED_DUMMY_CR_WO_STATUS, MTK_WED_DUMMY_CR_WO_STATUS,
...@@ -245,6 +271,8 @@ void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo, ...@@ -245,6 +271,8 @@ void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
struct sk_buff *skb); struct sk_buff *skb);
int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd, int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
const void *data, int len, bool wait_resp); const void *data, int len, bool wait_resp);
int mtk_wed_mcu_msg_update(struct mtk_wed_device *dev, int id, void *data,
int len);
int mtk_wed_mcu_init(struct mtk_wed_wo *wo); int mtk_wed_mcu_init(struct mtk_wed_wo *wo);
int mtk_wed_wo_init(struct mtk_wed_hw *hw); int mtk_wed_wo_init(struct mtk_wed_hw *hw);
void mtk_wed_wo_deinit(struct mtk_wed_hw *hw); void mtk_wed_wo_deinit(struct mtk_wed_hw *hw);
......
include/linux/soc/mediatek/mtk_wed.h
View file @ 4c5de09e
...@@ -5,10 +5,13 @@ ...@@ -5,10 +5,13 @@
#include <linux/rcupdate.h> #include <linux/rcupdate.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/skbuff.h>
#define MTK_WED_TX_QUEUES 2 #define MTK_WED_TX_QUEUES 2
#define MTK_WED_RX_QUEUES 2 #define MTK_WED_RX_QUEUES 2
#define WED_WO_STA_REC 0x6
struct mtk_wed_hw; struct mtk_wed_hw;
struct mtk_wdma_desc; struct mtk_wdma_desc;
...@@ -41,21 +44,37 @@ enum mtk_wed_wo_cmd { ...@@ -41,21 +44,37 @@ enum mtk_wed_wo_cmd {
MTK_WED_WO_CMD_WED_END MTK_WED_WO_CMD_WED_END
}; };
struct mtk_rxbm_desc {
__le32 buf0;
__le32 token;
} __packed __aligned(4);
enum mtk_wed_bus_tye { enum mtk_wed_bus_tye {
MTK_WED_BUS_PCIE, MTK_WED_BUS_PCIE,
MTK_WED_BUS_AXI, MTK_WED_BUS_AXI,
}; };
#define MTK_WED_RING_CONFIGURED BIT(0)
struct mtk_wed_ring { struct mtk_wed_ring {
struct mtk_wdma_desc *desc; struct mtk_wdma_desc *desc;
dma_addr_t desc_phys; dma_addr_t desc_phys;
u32 desc_size; u32 desc_size;
int size; int size;
u32 flags;
u32 reg_base; u32 reg_base;
void __iomem *wpdma; void __iomem *wpdma;
}; };
struct mtk_wed_wo_rx_stats {
__le16 wlan_idx;
__le16 tid;
__le32 rx_pkt_cnt;
__le32 rx_byte_cnt;
__le32 rx_err_cnt;
__le32 rx_drop_cnt;
};
struct mtk_wed_device { struct mtk_wed_device {
#ifdef CONFIG_NET_MEDIATEK_SOC_WED #ifdef CONFIG_NET_MEDIATEK_SOC_WED
const struct mtk_wed_ops *ops; const struct mtk_wed_ops *ops;
...@@ -64,9 +83,12 @@ struct mtk_wed_device { ...@@ -64,9 +83,12 @@ struct mtk_wed_device {
bool init_done, running; bool init_done, running;
int wdma_idx; int wdma_idx;
int irq; int irq;
u8 version;
struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES]; struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES];
struct mtk_wed_ring rx_ring[MTK_WED_RX_QUEUES];
struct mtk_wed_ring txfree_ring; struct mtk_wed_ring txfree_ring;
struct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES];
struct mtk_wed_ring rx_wdma[MTK_WED_RX_QUEUES]; struct mtk_wed_ring rx_wdma[MTK_WED_RX_QUEUES];
struct { struct {
...@@ -74,7 +96,20 @@ struct mtk_wed_device { ...@@ -74,7 +96,20 @@ struct mtk_wed_device {
void **pages; void **pages;
struct mtk_wdma_desc *desc; struct mtk_wdma_desc *desc;
dma_addr_t desc_phys; dma_addr_t desc_phys;
} buf_ring; } tx_buf_ring;
struct {
int size;
struct page_frag_cache rx_page;
struct mtk_rxbm_desc *desc;
dma_addr_t desc_phys;
} rx_buf_ring;
struct {
struct mtk_wed_ring ring;
dma_addr_t miod_phys;
dma_addr_t fdbk_phys;
} rro;
/* filled by driver: */ /* filled by driver: */
struct { struct {
...@@ -83,22 +118,36 @@ struct mtk_wed_device { ...@@ -83,22 +118,36 @@ struct mtk_wed_device {
struct pci_dev *pci_dev; struct pci_dev *pci_dev;
}; };
enum mtk_wed_bus_tye bus_type; enum mtk_wed_bus_tye bus_type;
void __iomem *base;
u32 phy_base;
u32 wpdma_phys; u32 wpdma_phys;
u32 wpdma_int; u32 wpdma_int;
u32 wpdma_mask; u32 wpdma_mask;
u32 wpdma_tx; u32 wpdma_tx;
u32 wpdma_txfree; u32 wpdma_txfree;
u32 wpdma_rx_glo;
u32 wpdma_rx;
bool wcid_512;
u16 token_start; u16 token_start;
unsigned int nbuf; unsigned int nbuf;
unsigned int rx_nbuf;
unsigned int rx_npkt;
unsigned int rx_size;
u8 tx_tbit[MTK_WED_TX_QUEUES]; u8 tx_tbit[MTK_WED_TX_QUEUES];
u8 rx_tbit[MTK_WED_RX_QUEUES];
u8 txfree_tbit; u8 txfree_tbit;
u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id); u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id);
int (*offload_enable)(struct mtk_wed_device *wed); int (*offload_enable)(struct mtk_wed_device *wed);
void (*offload_disable)(struct mtk_wed_device *wed); void (*offload_disable)(struct mtk_wed_device *wed);
u32 (*init_rx_buf)(struct mtk_wed_device *wed, int size);
void (*release_rx_buf)(struct mtk_wed_device *wed);
void (*update_wo_rx_stats)(struct mtk_wed_device *wed,
struct mtk_wed_wo_rx_stats *stats);
} wlan; } wlan;
#endif #endif
}; };
...@@ -107,9 +156,15 @@ struct mtk_wed_ops { ...@@ -107,9 +156,15 @@ struct mtk_wed_ops {
int (*attach)(struct mtk_wed_device *dev); int (*attach)(struct mtk_wed_device *dev);
int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring, int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring,
void __iomem *regs); void __iomem *regs);
int (*rx_ring_setup)(struct mtk_wed_device *dev, int ring,
void __iomem *regs);
int (*txfree_ring_setup)(struct mtk_wed_device *dev, int (*txfree_ring_setup)(struct mtk_wed_device *dev,
void __iomem *regs); void __iomem *regs);
int (*msg_update)(struct mtk_wed_device *dev, int cmd_id,
void *data, int len);
void (*detach)(struct mtk_wed_device *dev); void (*detach)(struct mtk_wed_device *dev);
void (*ppe_check)(struct mtk_wed_device *dev, struct sk_buff *skb,
u32 reason, u32 hash);
void (*stop)(struct mtk_wed_device *dev); void (*stop)(struct mtk_wed_device *dev);
void (*start)(struct mtk_wed_device *dev, u32 irq_mask); void (*start)(struct mtk_wed_device *dev, u32 irq_mask);
...@@ -144,6 +199,16 @@ mtk_wed_device_attach(struct mtk_wed_device *dev) ...@@ -144,6 +199,16 @@ mtk_wed_device_attach(struct mtk_wed_device *dev)
return ret; return ret;
} }
static inline bool
mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
{
#ifdef CONFIG_NET_MEDIATEK_SOC_WED
return dev->version != 1;
#else
return false;
#endif
}
#ifdef CONFIG_NET_MEDIATEK_SOC_WED #ifdef CONFIG_NET_MEDIATEK_SOC_WED
#define mtk_wed_device_active(_dev) !!(_dev)->ops #define mtk_wed_device_active(_dev) !!(_dev)->ops
#define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev) #define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)
...@@ -160,6 +225,12 @@ mtk_wed_device_attach(struct mtk_wed_device *dev) ...@@ -160,6 +225,12 @@ mtk_wed_device_attach(struct mtk_wed_device *dev)
(_dev)->ops->irq_get(_dev, _mask) (_dev)->ops->irq_get(_dev, _mask)
#define mtk_wed_device_irq_set_mask(_dev, _mask) \ #define mtk_wed_device_irq_set_mask(_dev, _mask) \
(_dev)->ops->irq_set_mask(_dev, _mask) (_dev)->ops->irq_set_mask(_dev, _mask)
#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) \
(_dev)->ops->rx_ring_setup(_dev, _ring, _regs)
#define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) \
(_dev)->ops->ppe_check(_dev, _skb, _reason, _hash)
#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \
(_dev)->ops->msg_update(_dev, _id, _msg, _len)
#else #else
static inline bool mtk_wed_device_active(struct mtk_wed_device *dev) static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
{ {
...@@ -173,6 +244,9 @@ static inline bool mtk_wed_device_active(struct mtk_wed_device *dev) ...@@ -173,6 +244,9 @@ static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
#define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0) #define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)
#define mtk_wed_device_irq_get(_dev, _mask) 0 #define mtk_wed_device_irq_get(_dev, _mask) 0
#define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0) #define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0)
#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs) -ENODEV
#define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) do {} while (0)
#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) -ENODEV
#endif #endif
#endif #endif
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