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Commit 4c87bc26 authored by Christian König's avatar Christian König Committed by Dave Airlie
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drm/radeon: make some asic pointers per ring 

Emitting fences, semaphores and ib works differently
on different ring, so its is easier to maintain
separate functions for each ring.
Signed-off-by: default avatarChristian König <deathsimple@vodafone.de>
Reviewed-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 60a7e396
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Showing with 144 additions and 64 deletions
drivers/gpu/drm/radeon/radeon.h
View file @ 4c87bc26
...@@ -950,16 +950,18 @@ struct radeon_asic { ...@@ -950,16 +950,18 @@ struct radeon_asic {
void (*cp_fini)(struct radeon_device *rdev); void (*cp_fini)(struct radeon_device *rdev);
void (*cp_disable)(struct radeon_device *rdev); void (*cp_disable)(struct radeon_device *rdev);
void (*ring_start)(struct radeon_device *rdev); void (*ring_start)(struct radeon_device *rdev);
struct {
void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_cp *cp,
struct radeon_semaphore *semaphore, bool emit_wait);
} ring[RADEON_NUM_RINGS];
int (*ring_test)(struct radeon_device *rdev, struct radeon_cp *cp); int (*ring_test)(struct radeon_device *rdev, struct radeon_cp *cp);
void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
int (*irq_set)(struct radeon_device *rdev); int (*irq_set)(struct radeon_device *rdev);
int (*irq_process)(struct radeon_device *rdev); int (*irq_process)(struct radeon_device *rdev);
u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
void (*semaphore_ring_emit)(struct radeon_device *rdev,
struct radeon_cp *cp,
struct radeon_semaphore *semaphore,
bool emit_wait);
int (*cs_parse)(struct radeon_cs_parser *p); int (*cs_parse)(struct radeon_cs_parser *p);
int (*copy_blit)(struct radeon_device *rdev, int (*copy_blit)(struct radeon_device *rdev,
uint64_t src_offset, uint64_t src_offset,
...@@ -1500,12 +1502,12 @@ void radeon_ring_write(struct radeon_cp *cp, uint32_t v); ...@@ -1500,12 +1502,12 @@ void radeon_ring_write(struct radeon_cp *cp, uint32_t v);
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
#define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp)) #define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
#define radeon_semaphore_ring_emit(rdev, cp, semaphore, emit_wait) (rdev)->asic->semaphore_ring_emit((rdev), (cp), (semaphore), (emit_wait)) #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
......
drivers/gpu/drm/radeon/radeon_asic.c
View file @ 4c87bc26
...@@ -140,12 +140,16 @@ static struct radeon_asic r100_asic = { ...@@ -140,12 +140,16 @@ static struct radeon_asic r100_asic = {
.gart_set_page = &r100_pci_gart_set_page, .gart_set_page = &r100_pci_gart_set_page,
.ring_start = &r100_ring_start, .ring_start = &r100_ring_start,
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute,
.emit_fence = &r100_fence_ring_emit,
.emit_semaphore = &r100_semaphore_ring_emit,
}
},
.irq_set = &r100_irq_set, .irq_set = &r100_irq_set,
.irq_process = &r100_irq_process, .irq_process = &r100_irq_process,
.get_vblank_counter = &r100_get_vblank_counter, .get_vblank_counter = &r100_get_vblank_counter,
.fence_ring_emit = &r100_fence_ring_emit,
.semaphore_ring_emit = &r100_semaphore_ring_emit,
.cs_parse = &r100_cs_parse, .cs_parse = &r100_cs_parse,
.copy_blit = &r100_copy_blit, .copy_blit = &r100_copy_blit,
.copy_dma = NULL, .copy_dma = NULL,
...@@ -188,12 +192,16 @@ static struct radeon_asic r200_asic = { ...@@ -188,12 +192,16 @@ static struct radeon_asic r200_asic = {
.gart_set_page = &r100_pci_gart_set_page, .gart_set_page = &r100_pci_gart_set_page,
.ring_start = &r100_ring_start, .ring_start = &r100_ring_start,
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute,
.emit_fence = &r100_fence_ring_emit,
.emit_semaphore = &r100_semaphore_ring_emit,
}
},
.irq_set = &r100_irq_set, .irq_set = &r100_irq_set,
.irq_process = &r100_irq_process, .irq_process = &r100_irq_process,
.get_vblank_counter = &r100_get_vblank_counter, .get_vblank_counter = &r100_get_vblank_counter,
.fence_ring_emit = &r100_fence_ring_emit,
.semaphore_ring_emit = &r100_semaphore_ring_emit,
.cs_parse = &r100_cs_parse, .cs_parse = &r100_cs_parse,
.copy_blit = &r100_copy_blit, .copy_blit = &r100_copy_blit,
.copy_dma = &r200_copy_dma, .copy_dma = &r200_copy_dma,
...@@ -235,12 +243,16 @@ static struct radeon_asic r300_asic = { ...@@ -235,12 +243,16 @@ static struct radeon_asic r300_asic = {
.gart_set_page = &r100_pci_gart_set_page, .gart_set_page = &r100_pci_gart_set_page,
.ring_start = &r300_ring_start, .ring_start = &r300_ring_start,
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute,
.emit_fence = &r300_fence_ring_emit,
.emit_semaphore = &r100_semaphore_ring_emit,
}
},
.irq_set = &r100_irq_set, .irq_set = &r100_irq_set,
.irq_process = &r100_irq_process, .irq_process = &r100_irq_process,
.get_vblank_counter = &r100_get_vblank_counter, .get_vblank_counter = &r100_get_vblank_counter,
.fence_ring_emit = &r300_fence_ring_emit,
.semaphore_ring_emit = &r100_semaphore_ring_emit,
.cs_parse = &r300_cs_parse, .cs_parse = &r300_cs_parse,
.copy_blit = &r100_copy_blit, .copy_blit = &r100_copy_blit,
.copy_dma = &r200_copy_dma, .copy_dma = &r200_copy_dma,
...@@ -283,12 +295,16 @@ static struct radeon_asic r300_asic_pcie = { ...@@ -283,12 +295,16 @@ static struct radeon_asic r300_asic_pcie = {
.gart_set_page = &rv370_pcie_gart_set_page, .gart_set_page = &rv370_pcie_gart_set_page,
.ring_start = &r300_ring_start, .ring_start = &r300_ring_start,
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute,
.emit_fence = &r300_fence_ring_emit,
.emit_semaphore = &r100_semaphore_ring_emit,
}
},
.irq_set = &r100_irq_set, .irq_set = &r100_irq_set,
.irq_process = &r100_irq_process, .irq_process = &r100_irq_process,
.get_vblank_counter = &r100_get_vblank_counter, .get_vblank_counter = &r100_get_vblank_counter,
.fence_ring_emit = &r300_fence_ring_emit,
.semaphore_ring_emit = &r100_semaphore_ring_emit,
.cs_parse = &r300_cs_parse, .cs_parse = &r300_cs_parse,
.copy_blit = &r100_copy_blit, .copy_blit = &r100_copy_blit,
.copy_dma = &r200_copy_dma, .copy_dma = &r200_copy_dma,
...@@ -330,12 +346,16 @@ static struct radeon_asic r420_asic = { ...@@ -330,12 +346,16 @@ static struct radeon_asic r420_asic = {
.gart_set_page = &rv370_pcie_gart_set_page, .gart_set_page = &rv370_pcie_gart_set_page,
.ring_start = &r300_ring_start, .ring_start = &r300_ring_start,
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute,
.emit_fence = &r300_fence_ring_emit,
.emit_semaphore = &r100_semaphore_ring_emit,
}
},
.irq_set = &r100_irq_set, .irq_set = &r100_irq_set,
.irq_process = &r100_irq_process, .irq_process = &r100_irq_process,
.get_vblank_counter = &r100_get_vblank_counter, .get_vblank_counter = &r100_get_vblank_counter,
.fence_ring_emit = &r300_fence_ring_emit,
.semaphore_ring_emit = &r100_semaphore_ring_emit,
.cs_parse = &r300_cs_parse, .cs_parse = &r300_cs_parse,
.copy_blit = &r100_copy_blit, .copy_blit = &r100_copy_blit,
.copy_dma = &r200_copy_dma, .copy_dma = &r200_copy_dma,
...@@ -378,12 +398,16 @@ static struct radeon_asic rs400_asic = { ...@@ -378,12 +398,16 @@ static struct radeon_asic rs400_asic = {
.gart_set_page = &rs400_gart_set_page, .gart_set_page = &rs400_gart_set_page,
.ring_start = &r300_ring_start, .ring_start = &r300_ring_start,
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute,
.emit_fence = &r300_fence_ring_emit,
.emit_semaphore = &r100_semaphore_ring_emit,
}
},
.irq_set = &r100_irq_set, .irq_set = &r100_irq_set,
.irq_process = &r100_irq_process, .irq_process = &r100_irq_process,
.get_vblank_counter = &r100_get_vblank_counter, .get_vblank_counter = &r100_get_vblank_counter,
.fence_ring_emit = &r300_fence_ring_emit,
.semaphore_ring_emit = &r100_semaphore_ring_emit,
.cs_parse = &r300_cs_parse, .cs_parse = &r300_cs_parse,
.copy_blit = &r100_copy_blit, .copy_blit = &r100_copy_blit,
.copy_dma = &r200_copy_dma, .copy_dma = &r200_copy_dma,
...@@ -426,12 +450,16 @@ static struct radeon_asic rs600_asic = { ...@@ -426,12 +450,16 @@ static struct radeon_asic rs600_asic = {
.gart_set_page = &rs600_gart_set_page, .gart_set_page = &rs600_gart_set_page,
.ring_start = &r300_ring_start, .ring_start = &r300_ring_start,
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute,
.emit_fence = &r300_fence_ring_emit,
.emit_semaphore = &r100_semaphore_ring_emit,
}
},
.irq_set = &rs600_irq_set, .irq_set = &rs600_irq_set,
.irq_process = &rs600_irq_process, .irq_process = &rs600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter, .get_vblank_counter = &rs600_get_vblank_counter,
.fence_ring_emit = &r300_fence_ring_emit,
.semaphore_ring_emit = &r100_semaphore_ring_emit,
.cs_parse = &r300_cs_parse, .cs_parse = &r300_cs_parse,
.copy_blit = &r100_copy_blit, .copy_blit = &r100_copy_blit,
.copy_dma = &r200_copy_dma, .copy_dma = &r200_copy_dma,
...@@ -474,12 +502,16 @@ static struct radeon_asic rs690_asic = { ...@@ -474,12 +502,16 @@ static struct radeon_asic rs690_asic = {
.gart_set_page = &rs400_gart_set_page, .gart_set_page = &rs400_gart_set_page,
.ring_start = &r300_ring_start, .ring_start = &r300_ring_start,
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute,
.emit_fence = &r300_fence_ring_emit,
.emit_semaphore = &r100_semaphore_ring_emit,
}
},
.irq_set = &rs600_irq_set, .irq_set = &rs600_irq_set,
.irq_process = &rs600_irq_process, .irq_process = &rs600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter, .get_vblank_counter = &rs600_get_vblank_counter,
.fence_ring_emit = &r300_fence_ring_emit,
.semaphore_ring_emit = &r100_semaphore_ring_emit,
.cs_parse = &r300_cs_parse, .cs_parse = &r300_cs_parse,
.copy_blit = &r100_copy_blit, .copy_blit = &r100_copy_blit,
.copy_dma = &r200_copy_dma, .copy_dma = &r200_copy_dma,
...@@ -522,12 +554,16 @@ static struct radeon_asic rv515_asic = { ...@@ -522,12 +554,16 @@ static struct radeon_asic rv515_asic = {
.gart_set_page = &rv370_pcie_gart_set_page, .gart_set_page = &rv370_pcie_gart_set_page,
.ring_start = &rv515_ring_start, .ring_start = &rv515_ring_start,
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute,
.emit_fence = &r300_fence_ring_emit,
.emit_semaphore = &r100_semaphore_ring_emit,
}
},
.irq_set = &rs600_irq_set, .irq_set = &rs600_irq_set,
.irq_process = &rs600_irq_process, .irq_process = &rs600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter, .get_vblank_counter = &rs600_get_vblank_counter,
.fence_ring_emit = &r300_fence_ring_emit,
.semaphore_ring_emit = &r100_semaphore_ring_emit,
.cs_parse = &r300_cs_parse, .cs_parse = &r300_cs_parse,
.copy_blit = &r100_copy_blit, .copy_blit = &r100_copy_blit,
.copy_dma = &r200_copy_dma, .copy_dma = &r200_copy_dma,
...@@ -570,12 +606,16 @@ static struct radeon_asic r520_asic = { ...@@ -570,12 +606,16 @@ static struct radeon_asic r520_asic = {
.gart_set_page = &rv370_pcie_gart_set_page, .gart_set_page = &rv370_pcie_gart_set_page,
.ring_start = &rv515_ring_start, .ring_start = &rv515_ring_start,
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r100_ring_ib_execute,
.emit_fence = &r300_fence_ring_emit,
.emit_semaphore = &r100_semaphore_ring_emit,
}
},
.irq_set = &rs600_irq_set, .irq_set = &rs600_irq_set,
.irq_process = &rs600_irq_process, .irq_process = &rs600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter, .get_vblank_counter = &rs600_get_vblank_counter,
.fence_ring_emit = &r300_fence_ring_emit,
.semaphore_ring_emit = &r100_semaphore_ring_emit,
.cs_parse = &r300_cs_parse, .cs_parse = &r300_cs_parse,
.copy_blit = &r100_copy_blit, .copy_blit = &r100_copy_blit,
.copy_dma = &r200_copy_dma, .copy_dma = &r200_copy_dma,
...@@ -617,12 +657,16 @@ static struct radeon_asic r600_asic = { ...@@ -617,12 +657,16 @@ static struct radeon_asic r600_asic = {
.gart_tlb_flush = &r600_pcie_gart_tlb_flush, .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page, .gart_set_page = &rs600_gart_set_page,
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ring_ib_execute = &r600_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r600_ring_ib_execute,
.emit_fence = &r600_fence_ring_emit,
.emit_semaphore = &r600_semaphore_ring_emit,
}
},
.irq_set = &r600_irq_set, .irq_set = &r600_irq_set,
.irq_process = &r600_irq_process, .irq_process = &r600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter, .get_vblank_counter = &rs600_get_vblank_counter,
.fence_ring_emit = &r600_fence_ring_emit,
.semaphore_ring_emit = &r600_semaphore_ring_emit,
.cs_parse = &r600_cs_parse, .cs_parse = &r600_cs_parse,
.copy_blit = &r600_copy_blit, .copy_blit = &r600_copy_blit,
.copy_dma = NULL, .copy_dma = NULL,
...@@ -664,12 +708,16 @@ static struct radeon_asic rs780_asic = { ...@@ -664,12 +708,16 @@ static struct radeon_asic rs780_asic = {
.gart_tlb_flush = &r600_pcie_gart_tlb_flush, .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page, .gart_set_page = &rs600_gart_set_page,
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ring_ib_execute = &r600_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r600_ring_ib_execute,
.emit_fence = &r600_fence_ring_emit,
.emit_semaphore = &r600_semaphore_ring_emit,
}
},
.irq_set = &r600_irq_set, .irq_set = &r600_irq_set,
.irq_process = &r600_irq_process, .irq_process = &r600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter, .get_vblank_counter = &rs600_get_vblank_counter,
.fence_ring_emit = &r600_fence_ring_emit,
.semaphore_ring_emit = &r600_semaphore_ring_emit,
.cs_parse = &r600_cs_parse, .cs_parse = &r600_cs_parse,
.copy_blit = &r600_copy_blit, .copy_blit = &r600_copy_blit,
.copy_dma = NULL, .copy_dma = NULL,
...@@ -711,12 +759,16 @@ static struct radeon_asic rv770_asic = { ...@@ -711,12 +759,16 @@ static struct radeon_asic rv770_asic = {
.gart_tlb_flush = &r600_pcie_gart_tlb_flush, .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page, .gart_set_page = &rs600_gart_set_page,
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ring_ib_execute = &r600_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &r600_ring_ib_execute,
.emit_fence = &r600_fence_ring_emit,
.emit_semaphore = &r600_semaphore_ring_emit,
}
},
.irq_set = &r600_irq_set, .irq_set = &r600_irq_set,
.irq_process = &r600_irq_process, .irq_process = &r600_irq_process,
.get_vblank_counter = &rs600_get_vblank_counter, .get_vblank_counter = &rs600_get_vblank_counter,
.fence_ring_emit = &r600_fence_ring_emit,
.semaphore_ring_emit = &r600_semaphore_ring_emit,
.cs_parse = &r600_cs_parse, .cs_parse = &r600_cs_parse,
.copy_blit = &r600_copy_blit, .copy_blit = &r600_copy_blit,
.copy_dma = NULL, .copy_dma = NULL,
...@@ -758,12 +810,16 @@ static struct radeon_asic evergreen_asic = { ...@@ -758,12 +810,16 @@ static struct radeon_asic evergreen_asic = {
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page, .gart_set_page = &rs600_gart_set_page,
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ring_ib_execute = &evergreen_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &evergreen_ring_ib_execute,
.emit_fence = &r600_fence_ring_emit,
.emit_semaphore = &r600_semaphore_ring_emit,
}
},
.irq_set = &evergreen_irq_set, .irq_set = &evergreen_irq_set,
.irq_process = &evergreen_irq_process, .irq_process = &evergreen_irq_process,
.get_vblank_counter = &evergreen_get_vblank_counter, .get_vblank_counter = &evergreen_get_vblank_counter,
.fence_ring_emit = &r600_fence_ring_emit,
.semaphore_ring_emit = &r600_semaphore_ring_emit,
.cs_parse = &evergreen_cs_parse, .cs_parse = &evergreen_cs_parse,
.copy_blit = &r600_copy_blit, .copy_blit = &r600_copy_blit,
.copy_dma = NULL, .copy_dma = NULL,
...@@ -805,12 +861,16 @@ static struct radeon_asic sumo_asic = { ...@@ -805,12 +861,16 @@ static struct radeon_asic sumo_asic = {
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page, .gart_set_page = &rs600_gart_set_page,
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ring_ib_execute = &evergreen_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &evergreen_ring_ib_execute,
.emit_fence = &r600_fence_ring_emit,
.emit_semaphore = &r600_semaphore_ring_emit,
}
},
.irq_set = &evergreen_irq_set, .irq_set = &evergreen_irq_set,
.irq_process = &evergreen_irq_process, .irq_process = &evergreen_irq_process,
.get_vblank_counter = &evergreen_get_vblank_counter, .get_vblank_counter = &evergreen_get_vblank_counter,
.fence_ring_emit = &r600_fence_ring_emit,
.semaphore_ring_emit = &r600_semaphore_ring_emit,
.cs_parse = &evergreen_cs_parse, .cs_parse = &evergreen_cs_parse,
.copy_blit = &r600_copy_blit, .copy_blit = &r600_copy_blit,
.copy_dma = NULL, .copy_dma = NULL,
...@@ -852,12 +912,16 @@ static struct radeon_asic btc_asic = { ...@@ -852,12 +912,16 @@ static struct radeon_asic btc_asic = {
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page, .gart_set_page = &rs600_gart_set_page,
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ring_ib_execute = &evergreen_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &evergreen_ring_ib_execute,
.emit_fence = &r600_fence_ring_emit,
.emit_semaphore = &r600_semaphore_ring_emit,
}
},
.irq_set = &evergreen_irq_set, .irq_set = &evergreen_irq_set,
.irq_process = &evergreen_irq_process, .irq_process = &evergreen_irq_process,
.get_vblank_counter = &evergreen_get_vblank_counter, .get_vblank_counter = &evergreen_get_vblank_counter,
.fence_ring_emit = &r600_fence_ring_emit,
.semaphore_ring_emit = &r600_semaphore_ring_emit,
.cs_parse = &evergreen_cs_parse, .cs_parse = &evergreen_cs_parse,
.copy_blit = &r600_copy_blit, .copy_blit = &r600_copy_blit,
.copy_dma = NULL, .copy_dma = NULL,
...@@ -899,12 +963,26 @@ static struct radeon_asic cayman_asic = { ...@@ -899,12 +963,26 @@ static struct radeon_asic cayman_asic = {
.gart_tlb_flush = &cayman_pcie_gart_tlb_flush, .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page, .gart_set_page = &rs600_gart_set_page,
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ring_ib_execute = &evergreen_ring_ib_execute, .ring = {
[RADEON_RING_TYPE_GFX_INDEX] = {
.ib_execute = &evergreen_ring_ib_execute,
.emit_fence = &r600_fence_ring_emit,
.emit_semaphore = &r600_semaphore_ring_emit,
},
[CAYMAN_RING_TYPE_CP1_INDEX] = {
.ib_execute = &r600_ring_ib_execute,
.emit_fence = &r600_fence_ring_emit,
.emit_semaphore = &r600_semaphore_ring_emit,
},
[CAYMAN_RING_TYPE_CP2_INDEX] = {
.ib_execute = &r600_ring_ib_execute,
.emit_fence = &r600_fence_ring_emit,
.emit_semaphore = &r600_semaphore_ring_emit,
}
},
.irq_set = &evergreen_irq_set, .irq_set = &evergreen_irq_set,
.irq_process = &evergreen_irq_process, .irq_process = &evergreen_irq_process,
.get_vblank_counter = &evergreen_get_vblank_counter, .get_vblank_counter = &evergreen_get_vblank_counter,
.fence_ring_emit = &r600_fence_ring_emit,
.semaphore_ring_emit = &r600_semaphore_ring_emit,
.cs_parse = &evergreen_cs_parse, .cs_parse = &evergreen_cs_parse,
.copy_blit = &r600_copy_blit, .copy_blit = &r600_copy_blit,
.copy_dma = NULL, .copy_dma = NULL,
......
drivers/gpu/drm/radeon/radeon_fence.c
View file @ 4c87bc26
...@@ -90,7 +90,7 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) ...@@ -90,7 +90,7 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
*/ */
radeon_fence_write(rdev, fence->seq, fence->ring); radeon_fence_write(rdev, fence->seq, fence->ring);
else else
radeon_fence_ring_emit(rdev, fence); radeon_fence_ring_emit(rdev, fence->ring, fence);
trace_radeon_fence_emit(rdev->ddev, fence->seq); trace_radeon_fence_emit(rdev->ddev, fence->seq);
fence->emitted = true; fence->emitted = true;
......
drivers/gpu/drm/radeon/radeon_ring.c
View file @ 4c87bc26
...@@ -193,7 +193,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) ...@@ -193,7 +193,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
DRM_ERROR("radeon: scheduling IB failed (%d).\n", r); DRM_ERROR("radeon: scheduling IB failed (%d).\n", r);
return r; return r;
} }
radeon_ring_ib_execute(rdev, ib); radeon_ring_ib_execute(rdev, ib->fence->ring, ib);
radeon_fence_emit(rdev, ib->fence); radeon_fence_emit(rdev, ib->fence);
mutex_lock(&rdev->ib_pool.mutex); mutex_lock(&rdev->ib_pool.mutex);
/* once scheduled IB is considered free and protected by the fence */ /* once scheduled IB is considered free and protected by the fence */
......
drivers/gpu/drm/radeon/radeon_semaphore.c
View file @ 4c87bc26
...@@ -121,13 +121,13 @@ int radeon_semaphore_create(struct radeon_device *rdev, ...@@ -121,13 +121,13 @@ int radeon_semaphore_create(struct radeon_device *rdev,
void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
struct radeon_semaphore *semaphore) struct radeon_semaphore *semaphore)
{ {
radeon_semaphore_ring_emit(rdev, &rdev->cp[ring], semaphore, false); radeon_semaphore_ring_emit(rdev, ring, &rdev->cp[ring], semaphore, false);
} }
void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
struct radeon_semaphore *semaphore) struct radeon_semaphore *semaphore)
{ {
radeon_semaphore_ring_emit(rdev, &rdev->cp[ring], semaphore, true); radeon_semaphore_ring_emit(rdev, ring, &rdev->cp[ring], semaphore, true);
} }
void radeon_semaphore_free(struct radeon_device *rdev, void radeon_semaphore_free(struct radeon_device *rdev,
......
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