Commit 4d20d087 authored by Philipp Zabel's avatar Philipp Zabel Committed by Mauro Carvalho Chehab

media: hantro: make irq names configurable

The i.MX8MQ bindings will use different IRQ names ("g1" instead of
"vdpu", and "g2"), so make them configurable. This also allows to
register more than two IRQs, which will be required for i.MX8MM support
later (it will add "h1" instead of "vepu").
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 0fd7ada1
...@@ -44,6 +44,17 @@ struct hantro_codec_ops; ...@@ -44,6 +44,17 @@ struct hantro_codec_ops;
#define HANTRO_MPEG2_DECODER BIT(16) #define HANTRO_MPEG2_DECODER BIT(16)
#define HANTRO_DECODERS 0xffff0000 #define HANTRO_DECODERS 0xffff0000
/**
* struct hantro_irq - irq handler and name
*
* @name: irq name for device tree lookup
* @handler: interrupt handler
*/
struct hantro_irq {
const char *name;
irqreturn_t (*handler)(int irq, void *priv);
};
/** /**
* struct hantro_variant - information about VPU hardware variant * struct hantro_variant - information about VPU hardware variant
* *
...@@ -57,8 +68,8 @@ struct hantro_codec_ops; ...@@ -57,8 +68,8 @@ struct hantro_codec_ops;
* @codec_ops: Codec ops. * @codec_ops: Codec ops.
* @init: Initialize hardware. * @init: Initialize hardware.
* @runtime_resume: reenable hardware after power gating * @runtime_resume: reenable hardware after power gating
* @vepu_irq: encoder interrupt handler * @irqs: array of irq names and interrupt handlers
* @vdpu_irq: decoder interrupt handler * @num_irqs: number of irqs in the array
* @clk_names: array of clock names * @clk_names: array of clock names
* @num_clocks: number of clocks in the array * @num_clocks: number of clocks in the array
*/ */
...@@ -73,8 +84,8 @@ struct hantro_variant { ...@@ -73,8 +84,8 @@ struct hantro_variant {
const struct hantro_codec_ops *codec_ops; const struct hantro_codec_ops *codec_ops;
int (*init)(struct hantro_dev *vpu); int (*init)(struct hantro_dev *vpu);
int (*runtime_resume)(struct hantro_dev *vpu); int (*runtime_resume)(struct hantro_dev *vpu);
irqreturn_t (*vepu_irq)(int irq, void *priv); const struct hantro_irq *irqs;
irqreturn_t (*vdpu_irq)(int irq, void *priv); int num_irqs;
const char *clk_names[HANTRO_MAX_CLOCKS]; const char *clk_names[HANTRO_MAX_CLOCKS];
int num_clocks; int num_clocks;
}; };
......
...@@ -706,36 +706,25 @@ static int hantro_probe(struct platform_device *pdev) ...@@ -706,36 +706,25 @@ static int hantro_probe(struct platform_device *pdev)
return ret; return ret;
} }
if (vpu->variant->vdpu_irq) { for (i = 0; i < vpu->variant->num_irqs; i++) {
const char *irq_name = vpu->variant->irqs[i].name;
int irq; int irq;
irq = platform_get_irq_byname(vpu->pdev, "vdpu"); if (!vpu->variant->irqs[i].handler)
if (irq <= 0) { continue;
dev_err(vpu->dev, "Could not get vdpu IRQ.\n");
return -ENXIO;
}
ret = devm_request_irq(vpu->dev, irq, vpu->variant->vdpu_irq,
0, dev_name(vpu->dev), vpu);
if (ret) {
dev_err(vpu->dev, "Could not request vdpu IRQ.\n");
return ret;
}
}
if (vpu->variant->vepu_irq) {
int irq;
irq = platform_get_irq_byname(vpu->pdev, "vepu"); irq = platform_get_irq_byname(vpu->pdev, irq_name);
if (irq <= 0) { if (irq <= 0) {
dev_err(vpu->dev, "Could not get vepu IRQ.\n"); dev_err(vpu->dev, "Could not get %s IRQ.\n", irq_name);
return -ENXIO; return -ENXIO;
} }
ret = devm_request_irq(vpu->dev, irq, vpu->variant->vepu_irq, ret = devm_request_irq(vpu->dev, irq,
0, dev_name(vpu->dev), vpu); vpu->variant->irqs[i].handler, 0,
dev_name(vpu->dev), vpu);
if (ret) { if (ret) {
dev_err(vpu->dev, "Could not request vepu IRQ.\n"); dev_err(vpu->dev, "Could not request %s IRQ.\n",
irq_name);
return ret; return ret;
} }
} }
......
...@@ -161,6 +161,11 @@ static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = { ...@@ -161,6 +161,11 @@ static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
* VPU variant. * VPU variant.
*/ */
static const struct hantro_irq rk3288_irqs[] = {
{ "vepu", rk3288_vepu_irq },
{ "vdpu", rk3288_vdpu_irq },
};
const struct hantro_variant rk3288_vpu_variant = { const struct hantro_variant rk3288_vpu_variant = {
.enc_offset = 0x0, .enc_offset = 0x0,
.enc_fmts = rk3288_vpu_enc_fmts, .enc_fmts = rk3288_vpu_enc_fmts,
...@@ -170,8 +175,8 @@ const struct hantro_variant rk3288_vpu_variant = { ...@@ -170,8 +175,8 @@ const struct hantro_variant rk3288_vpu_variant = {
.num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts), .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER, .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER,
.codec_ops = rk3288_vpu_codec_ops, .codec_ops = rk3288_vpu_codec_ops,
.vepu_irq = rk3288_vepu_irq, .irqs = rk3288_irqs,
.vdpu_irq = rk3288_vdpu_irq, .num_irqs = ARRAY_SIZE(rk3288_irqs),
.init = rk3288_vpu_hw_init, .init = rk3288_vpu_hw_init,
.clk_names = {"aclk", "hclk"}, .clk_names = {"aclk", "hclk"},
.num_clocks = 2 .num_clocks = 2
......
...@@ -160,6 +160,11 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { ...@@ -160,6 +160,11 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
* VPU variant. * VPU variant.
*/ */
static const struct hantro_irq rk3399_irqs[] = {
{ "vepu", rk3399_vepu_irq },
{ "vdpu", rk3399_vdpu_irq },
};
const struct hantro_variant rk3399_vpu_variant = { const struct hantro_variant rk3399_vpu_variant = {
.enc_offset = 0x0, .enc_offset = 0x0,
.enc_fmts = rk3399_vpu_enc_fmts, .enc_fmts = rk3399_vpu_enc_fmts,
...@@ -169,8 +174,8 @@ const struct hantro_variant rk3399_vpu_variant = { ...@@ -169,8 +174,8 @@ const struct hantro_variant rk3399_vpu_variant = {
.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER, .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER,
.codec_ops = rk3399_vpu_codec_ops, .codec_ops = rk3399_vpu_codec_ops,
.vepu_irq = rk3399_vepu_irq, .irqs = rk3399_irqs,
.vdpu_irq = rk3399_vdpu_irq, .num_irqs = ARRAY_SIZE(rk3399_irqs),
.init = rk3399_vpu_hw_init, .init = rk3399_vpu_hw_init,
.clk_names = {"aclk", "hclk"}, .clk_names = {"aclk", "hclk"},
.num_clocks = 2 .num_clocks = 2
......
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