Commit 4dbee510 authored by Vijendar Mukunda's avatar Vijendar Mukunda Committed by Mark Brown

ASoC: SOF: amd: increase DSP cache window range

Increase DSP cache window range to 2.5MB to align with ACP memory.
Signed-off-by: default avatarVijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://lore.kernel.org/r/20231020062822.3913760-3-Vijendar.Mukunda@amd.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 848c0d34
......@@ -84,7 +84,7 @@
#define EXCEPT_MAX_HDR_SIZE 0x400
#define AMD_STACK_DUMP_SIZE 32
#define SRAM1_SIZE 0x13A000
#define SRAM1_SIZE 0x280000
#define PROBE_STATUS_BIT BIT(31)
#define ACP_FIRMWARE_SIGNATURE 0x100
......
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